1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-flat-for-global,+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s 3; RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s 4 5; FIXME: Broken on evergreen 6; FIXME: For some reason the 8 and 16 vectors are being stored as 7; individual elements instead of 128-bit stores. 8 9 10; FIXME: Why is the constant moved into the intermediate register and 11; not just directly into the vector component? 12define amdgpu_kernel void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 13; SI-LABEL: insertelement_v4f32_0: 14; SI: ; %bb.0: 15; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 16; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4 17; SI-NEXT: s_waitcnt lgkmcnt(0) 18; SI-NEXT: s_mov_b32 s4, 0x40a00000 19; SI-NEXT: s_mov_b32 s3, 0x100f000 20; SI-NEXT: s_mov_b32 s2, -1 21; SI-NEXT: v_mov_b32_e32 v0, s4 22; SI-NEXT: v_mov_b32_e32 v1, s5 23; SI-NEXT: v_mov_b32_e32 v2, s6 24; SI-NEXT: v_mov_b32_e32 v3, s7 25; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 26; SI-NEXT: s_endpgm 27; 28; VI-LABEL: insertelement_v4f32_0: 29; VI: ; %bb.0: 30; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 31; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10 32; VI-NEXT: s_waitcnt lgkmcnt(0) 33; VI-NEXT: s_mov_b32 s4, 0x40a00000 34; VI-NEXT: s_mov_b32 s3, 0x1100f000 35; VI-NEXT: s_mov_b32 s2, -1 36; VI-NEXT: v_mov_b32_e32 v0, s4 37; VI-NEXT: v_mov_b32_e32 v1, s5 38; VI-NEXT: v_mov_b32_e32 v2, s6 39; VI-NEXT: v_mov_b32_e32 v3, s7 40; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 41; VI-NEXT: s_endpgm 42 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0 43 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 44 ret void 45} 46 47define amdgpu_kernel void @insertelement_v4f32_1(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 48; SI-LABEL: insertelement_v4f32_1: 49; SI: ; %bb.0: 50; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 51; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4 52; SI-NEXT: s_waitcnt lgkmcnt(0) 53; SI-NEXT: s_mov_b32 s5, 0x40a00000 54; SI-NEXT: s_mov_b32 s3, 0x100f000 55; SI-NEXT: s_mov_b32 s2, -1 56; SI-NEXT: v_mov_b32_e32 v0, s4 57; SI-NEXT: v_mov_b32_e32 v1, s5 58; SI-NEXT: v_mov_b32_e32 v2, s6 59; SI-NEXT: v_mov_b32_e32 v3, s7 60; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 61; SI-NEXT: s_endpgm 62; 63; VI-LABEL: insertelement_v4f32_1: 64; VI: ; %bb.0: 65; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 66; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10 67; VI-NEXT: s_waitcnt lgkmcnt(0) 68; VI-NEXT: s_mov_b32 s5, 0x40a00000 69; VI-NEXT: s_mov_b32 s3, 0x1100f000 70; VI-NEXT: s_mov_b32 s2, -1 71; VI-NEXT: v_mov_b32_e32 v0, s4 72; VI-NEXT: v_mov_b32_e32 v1, s5 73; VI-NEXT: v_mov_b32_e32 v2, s6 74; VI-NEXT: v_mov_b32_e32 v3, s7 75; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 76; VI-NEXT: s_endpgm 77 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 1 78 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 79 ret void 80} 81 82define amdgpu_kernel void @insertelement_v4f32_2(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 83; SI-LABEL: insertelement_v4f32_2: 84; SI: ; %bb.0: 85; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 86; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4 87; SI-NEXT: s_waitcnt lgkmcnt(0) 88; SI-NEXT: s_mov_b32 s6, 0x40a00000 89; SI-NEXT: s_mov_b32 s3, 0x100f000 90; SI-NEXT: s_mov_b32 s2, -1 91; SI-NEXT: v_mov_b32_e32 v0, s4 92; SI-NEXT: v_mov_b32_e32 v1, s5 93; SI-NEXT: v_mov_b32_e32 v2, s6 94; SI-NEXT: v_mov_b32_e32 v3, s7 95; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 96; SI-NEXT: s_endpgm 97; 98; VI-LABEL: insertelement_v4f32_2: 99; VI: ; %bb.0: 100; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 101; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10 102; VI-NEXT: s_waitcnt lgkmcnt(0) 103; VI-NEXT: s_mov_b32 s6, 0x40a00000 104; VI-NEXT: s_mov_b32 s3, 0x1100f000 105; VI-NEXT: s_mov_b32 s2, -1 106; VI-NEXT: v_mov_b32_e32 v0, s4 107; VI-NEXT: v_mov_b32_e32 v1, s5 108; VI-NEXT: v_mov_b32_e32 v2, s6 109; VI-NEXT: v_mov_b32_e32 v3, s7 110; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 111; VI-NEXT: s_endpgm 112 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 2 113 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 114 ret void 115} 116 117define amdgpu_kernel void @insertelement_v4f32_3(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { 118; SI-LABEL: insertelement_v4f32_3: 119; SI: ; %bb.0: 120; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 121; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4 122; SI-NEXT: s_waitcnt lgkmcnt(0) 123; SI-NEXT: s_mov_b32 s7, 0x40a00000 124; SI-NEXT: s_mov_b32 s3, 0x100f000 125; SI-NEXT: s_mov_b32 s2, -1 126; SI-NEXT: v_mov_b32_e32 v0, s4 127; SI-NEXT: v_mov_b32_e32 v1, s5 128; SI-NEXT: v_mov_b32_e32 v2, s6 129; SI-NEXT: v_mov_b32_e32 v3, s7 130; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 131; SI-NEXT: s_endpgm 132; 133; VI-LABEL: insertelement_v4f32_3: 134; VI: ; %bb.0: 135; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 136; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10 137; VI-NEXT: s_waitcnt lgkmcnt(0) 138; VI-NEXT: s_mov_b32 s7, 0x40a00000 139; VI-NEXT: s_mov_b32 s3, 0x1100f000 140; VI-NEXT: s_mov_b32 s2, -1 141; VI-NEXT: v_mov_b32_e32 v0, s4 142; VI-NEXT: v_mov_b32_e32 v1, s5 143; VI-NEXT: v_mov_b32_e32 v2, s6 144; VI-NEXT: v_mov_b32_e32 v3, s7 145; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 146; VI-NEXT: s_endpgm 147 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 3 148 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 149 ret void 150} 151 152define amdgpu_kernel void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) nounwind { 153; SI-LABEL: insertelement_v4i32_0: 154; SI: ; %bb.0: 155; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 156; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4 157; SI-NEXT: s_waitcnt lgkmcnt(0) 158; SI-NEXT: s_movk_i32 s4, 0x3e7 159; SI-NEXT: s_mov_b32 s3, 0x100f000 160; SI-NEXT: s_mov_b32 s2, -1 161; SI-NEXT: v_mov_b32_e32 v0, s4 162; SI-NEXT: v_mov_b32_e32 v1, s5 163; SI-NEXT: v_mov_b32_e32 v2, s6 164; SI-NEXT: v_mov_b32_e32 v3, s7 165; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 166; SI-NEXT: s_endpgm 167; 168; VI-LABEL: insertelement_v4i32_0: 169; VI: ; %bb.0: 170; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 171; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10 172; VI-NEXT: s_waitcnt lgkmcnt(0) 173; VI-NEXT: s_movk_i32 s4, 0x3e7 174; VI-NEXT: s_mov_b32 s3, 0x1100f000 175; VI-NEXT: s_mov_b32 s2, -1 176; VI-NEXT: v_mov_b32_e32 v0, s4 177; VI-NEXT: v_mov_b32_e32 v1, s5 178; VI-NEXT: v_mov_b32_e32 v2, s6 179; VI-NEXT: v_mov_b32_e32 v3, s7 180; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 181; VI-NEXT: s_endpgm 182 %vecins = insertelement <4 x i32> %a, i32 999, i32 0 183 store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 184 ret void 185} 186 187define amdgpu_kernel void @insertelement_v3f32_1(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 188; SI-LABEL: insertelement_v3f32_1: 189; SI: ; %bb.0: 190; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 191; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4 192; SI-NEXT: s_mov_b32 s3, 0x100f000 193; SI-NEXT: s_mov_b32 s2, -1 194; SI-NEXT: v_mov_b32_e32 v1, 0x40a00000 195; SI-NEXT: s_waitcnt lgkmcnt(0) 196; SI-NEXT: v_mov_b32_e32 v0, s4 197; SI-NEXT: v_mov_b32_e32 v2, s6 198; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 199; SI-NEXT: s_endpgm 200; 201; VI-LABEL: insertelement_v3f32_1: 202; VI: ; %bb.0: 203; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 204; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10 205; VI-NEXT: s_mov_b32 s3, 0x1100f000 206; VI-NEXT: s_mov_b32 s2, -1 207; VI-NEXT: v_mov_b32_e32 v1, 0x40a00000 208; VI-NEXT: s_waitcnt lgkmcnt(0) 209; VI-NEXT: v_mov_b32_e32 v0, s4 210; VI-NEXT: v_mov_b32_e32 v2, s6 211; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 212; VI-NEXT: s_endpgm 213 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 1 214 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 215 ret void 216} 217 218define amdgpu_kernel void @insertelement_v3f32_2(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 219; SI-LABEL: insertelement_v3f32_2: 220; SI: ; %bb.0: 221; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 222; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x4 223; SI-NEXT: s_mov_b32 s3, 0x100f000 224; SI-NEXT: s_mov_b32 s2, -1 225; SI-NEXT: v_mov_b32_e32 v2, 0x40a00000 226; SI-NEXT: s_waitcnt lgkmcnt(0) 227; SI-NEXT: v_mov_b32_e32 v0, s4 228; SI-NEXT: v_mov_b32_e32 v1, s5 229; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 230; SI-NEXT: s_endpgm 231; 232; VI-LABEL: insertelement_v3f32_2: 233; VI: ; %bb.0: 234; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 235; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x10 236; VI-NEXT: s_mov_b32 s3, 0x1100f000 237; VI-NEXT: s_mov_b32 s2, -1 238; VI-NEXT: v_mov_b32_e32 v2, 0x40a00000 239; VI-NEXT: s_waitcnt lgkmcnt(0) 240; VI-NEXT: v_mov_b32_e32 v0, s4 241; VI-NEXT: v_mov_b32_e32 v1, s5 242; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 243; VI-NEXT: s_endpgm 244 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 2 245 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 246 ret void 247} 248 249define amdgpu_kernel void @insertelement_v3f32_3(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { 250; GCN-LABEL: insertelement_v3f32_3: 251; GCN: ; %bb.0: 252; GCN-NEXT: s_endpgm 253 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 3 254 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 255 ret void 256} 257 258define <4 x float> @insertelement_to_sgpr() nounwind { 259; GCN-LABEL: insertelement_to_sgpr: 260; GCN: ; %bb.0: 261; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 262; GCN-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x0 263; GCN-NEXT: s_waitcnt lgkmcnt(0) 264; GCN-NEXT: s_mov_b32 s12, 0 265; GCN-NEXT: s_mov_b32 s4, s12 266; GCN-NEXT: s_mov_b32 s5, s12 267; GCN-NEXT: s_mov_b32 s6, s12 268; GCN-NEXT: s_mov_b32 s7, s12 269; GCN-NEXT: s_mov_b32 s8, s12 270; GCN-NEXT: s_mov_b32 s9, s12 271; GCN-NEXT: s_mov_b32 s10, s12 272; GCN-NEXT: s_mov_b32 s11, s12 273; GCN-NEXT: image_gather4_lz v[0:3], v[0:1], s[4:11], s[12:15] dmask:0x1 274; GCN-NEXT: s_waitcnt vmcnt(0) 275; GCN-NEXT: s_setpc_b64 s[30:31] 276 %tmp = load <4 x i32>, <4 x i32> addrspace(4)* undef 277 %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0 278 %tmp2 = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32 1, float undef, float undef, <8 x i32> undef, <4 x i32> %tmp1, i1 0, i32 0, i32 0) 279 ret <4 x float> %tmp2 280} 281 282define amdgpu_kernel void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind { 283; SI-LABEL: dynamic_insertelement_v2f32: 284; SI: ; %bb.0: 285; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 286; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2 287; SI-NEXT: s_load_dword s4, s[4:5], 0x4 288; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000 289; SI-NEXT: s_mov_b32 s3, 0x100f000 290; SI-NEXT: s_mov_b32 s2, -1 291; SI-NEXT: s_waitcnt lgkmcnt(0) 292; SI-NEXT: v_mov_b32_e32 v1, s7 293; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 294; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 295; SI-NEXT: v_mov_b32_e32 v2, s6 296; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 297; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 298; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 299; SI-NEXT: s_endpgm 300; 301; VI-LABEL: dynamic_insertelement_v2f32: 302; VI: ; %bb.0: 303; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 304; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8 305; VI-NEXT: s_load_dword s4, s[4:5], 0x10 306; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000 307; VI-NEXT: s_mov_b32 s3, 0x1100f000 308; VI-NEXT: s_mov_b32 s2, -1 309; VI-NEXT: s_waitcnt lgkmcnt(0) 310; VI-NEXT: v_mov_b32_e32 v1, s7 311; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 312; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 313; VI-NEXT: v_mov_b32_e32 v2, s6 314; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 315; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 316; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 317; VI-NEXT: s_endpgm 318 %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b 319 store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8 320 ret void 321} 322 323define amdgpu_kernel void @dynamic_insertelement_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, i32 %b) nounwind { 324; SI-LABEL: dynamic_insertelement_v3f32: 325; SI: ; %bb.0: 326; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 327; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4 328; SI-NEXT: s_load_dword s4, s[4:5], 0x8 329; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000 330; SI-NEXT: s_mov_b32 s3, 0x100f000 331; SI-NEXT: s_mov_b32 s2, -1 332; SI-NEXT: s_waitcnt lgkmcnt(0) 333; SI-NEXT: v_mov_b32_e32 v1, s10 334; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 335; SI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc 336; SI-NEXT: v_mov_b32_e32 v1, s9 337; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 338; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 339; SI-NEXT: v_mov_b32_e32 v3, s8 340; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 341; SI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc 342; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 343; SI-NEXT: s_endpgm 344; 345; VI-LABEL: dynamic_insertelement_v3f32: 346; VI: ; %bb.0: 347; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 348; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 349; VI-NEXT: s_load_dword s4, s[4:5], 0x20 350; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000 351; VI-NEXT: s_mov_b32 s3, 0x1100f000 352; VI-NEXT: s_mov_b32 s2, -1 353; VI-NEXT: s_waitcnt lgkmcnt(0) 354; VI-NEXT: v_mov_b32_e32 v1, s10 355; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 356; VI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc 357; VI-NEXT: v_mov_b32_e32 v1, s9 358; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 359; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 360; VI-NEXT: v_mov_b32_e32 v3, s8 361; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 362; VI-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc 363; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 364; VI-NEXT: s_endpgm 365 %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b 366 store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 367 ret void 368} 369 370define amdgpu_kernel void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind { 371; SI-LABEL: dynamic_insertelement_v4f32: 372; SI: ; %bb.0: 373; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 374; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4 375; SI-NEXT: s_load_dword s4, s[4:5], 0x8 376; SI-NEXT: v_mov_b32_e32 v0, 0x40a00000 377; SI-NEXT: s_mov_b32 s3, 0x100f000 378; SI-NEXT: s_mov_b32 s2, -1 379; SI-NEXT: s_waitcnt lgkmcnt(0) 380; SI-NEXT: v_mov_b32_e32 v1, s11 381; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 382; SI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc 383; SI-NEXT: v_mov_b32_e32 v1, s10 384; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 385; SI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc 386; SI-NEXT: v_mov_b32_e32 v1, s9 387; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 388; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 389; SI-NEXT: v_mov_b32_e32 v4, s8 390; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 391; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc 392; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 393; SI-NEXT: s_endpgm 394; 395; VI-LABEL: dynamic_insertelement_v4f32: 396; VI: ; %bb.0: 397; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 398; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 399; VI-NEXT: s_load_dword s4, s[4:5], 0x20 400; VI-NEXT: v_mov_b32_e32 v0, 0x40a00000 401; VI-NEXT: s_mov_b32 s3, 0x1100f000 402; VI-NEXT: s_mov_b32 s2, -1 403; VI-NEXT: s_waitcnt lgkmcnt(0) 404; VI-NEXT: v_mov_b32_e32 v1, s11 405; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 406; VI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc 407; VI-NEXT: v_mov_b32_e32 v1, s10 408; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 409; VI-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc 410; VI-NEXT: v_mov_b32_e32 v1, s9 411; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 412; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 413; VI-NEXT: v_mov_b32_e32 v4, s8 414; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 415; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc 416; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 417; VI-NEXT: s_endpgm 418 %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b 419 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 420 ret void 421} 422 423define amdgpu_kernel void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind { 424; SI-LABEL: dynamic_insertelement_v8f32: 425; SI: ; %bb.0: 426; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 427; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8 428; SI-NEXT: s_load_dword s4, s[4:5], 0x10 429; SI-NEXT: v_mov_b32_e32 v4, 0x40a00000 430; SI-NEXT: s_mov_b32 s3, 0x100f000 431; SI-NEXT: s_mov_b32 s2, -1 432; SI-NEXT: s_waitcnt lgkmcnt(0) 433; SI-NEXT: v_mov_b32_e32 v0, s11 434; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 435; SI-NEXT: v_cndmask_b32_e32 v3, v4, v0, vcc 436; SI-NEXT: v_mov_b32_e32 v0, s10 437; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 438; SI-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc 439; SI-NEXT: v_mov_b32_e32 v0, s9 440; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 441; SI-NEXT: v_cndmask_b32_e32 v1, v4, v0, vcc 442; SI-NEXT: v_mov_b32_e32 v0, s8 443; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 444; SI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc 445; SI-NEXT: v_mov_b32_e32 v5, s15 446; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7 447; SI-NEXT: v_cndmask_b32_e32 v7, v4, v5, vcc 448; SI-NEXT: v_mov_b32_e32 v5, s14 449; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6 450; SI-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc 451; SI-NEXT: v_mov_b32_e32 v5, s13 452; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5 453; SI-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc 454; SI-NEXT: v_mov_b32_e32 v8, s12 455; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4 456; SI-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc 457; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 458; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 459; SI-NEXT: s_endpgm 460; 461; VI-LABEL: dynamic_insertelement_v8f32: 462; VI: ; %bb.0: 463; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 464; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20 465; VI-NEXT: s_load_dword s4, s[4:5], 0x40 466; VI-NEXT: v_mov_b32_e32 v4, 0x40a00000 467; VI-NEXT: s_mov_b32 s3, 0x1100f000 468; VI-NEXT: s_mov_b32 s2, -1 469; VI-NEXT: s_waitcnt lgkmcnt(0) 470; VI-NEXT: v_mov_b32_e32 v0, s11 471; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 472; VI-NEXT: v_cndmask_b32_e32 v3, v4, v0, vcc 473; VI-NEXT: v_mov_b32_e32 v0, s10 474; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 475; VI-NEXT: v_cndmask_b32_e32 v2, v4, v0, vcc 476; VI-NEXT: v_mov_b32_e32 v0, s9 477; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 478; VI-NEXT: v_cndmask_b32_e32 v1, v4, v0, vcc 479; VI-NEXT: v_mov_b32_e32 v0, s8 480; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 481; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc 482; VI-NEXT: v_mov_b32_e32 v5, s15 483; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7 484; VI-NEXT: v_cndmask_b32_e32 v7, v4, v5, vcc 485; VI-NEXT: v_mov_b32_e32 v5, s14 486; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6 487; VI-NEXT: v_cndmask_b32_e32 v6, v4, v5, vcc 488; VI-NEXT: v_mov_b32_e32 v5, s13 489; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5 490; VI-NEXT: v_cndmask_b32_e32 v5, v4, v5, vcc 491; VI-NEXT: v_mov_b32_e32 v8, s12 492; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4 493; VI-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc 494; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 495; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 496; VI-NEXT: s_endpgm 497 %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b 498 store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32 499 ret void 500} 501 502define amdgpu_kernel void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %b) nounwind { 503; SI-LABEL: dynamic_insertelement_v16f32: 504; SI: ; %bb.0: 505; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 506; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x10 507; SI-NEXT: s_load_dword s4, s[4:5], 0x20 508; SI-NEXT: v_mov_b32_e32 v16, 0x40a00000 509; SI-NEXT: s_mov_b32 s3, 0x100f000 510; SI-NEXT: s_mov_b32 s2, -1 511; SI-NEXT: s_waitcnt lgkmcnt(0) 512; SI-NEXT: v_mov_b32_e32 v0, s8 513; SI-NEXT: v_mov_b32_e32 v1, s9 514; SI-NEXT: v_mov_b32_e32 v2, s10 515; SI-NEXT: v_mov_b32_e32 v3, s11 516; SI-NEXT: v_mov_b32_e32 v4, s12 517; SI-NEXT: v_mov_b32_e32 v5, s13 518; SI-NEXT: v_mov_b32_e32 v6, s14 519; SI-NEXT: v_mov_b32_e32 v7, s15 520; SI-NEXT: v_mov_b32_e32 v8, s16 521; SI-NEXT: v_mov_b32_e32 v9, s17 522; SI-NEXT: v_mov_b32_e32 v10, s18 523; SI-NEXT: v_mov_b32_e32 v11, s19 524; SI-NEXT: v_mov_b32_e32 v12, s20 525; SI-NEXT: v_mov_b32_e32 v13, s21 526; SI-NEXT: v_mov_b32_e32 v14, s22 527; SI-NEXT: v_mov_b32_e32 v15, s23 528; SI-NEXT: s_mov_b32 m0, s4 529; SI-NEXT: v_movreld_b32_e32 v0, v16 530; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48 531; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32 532; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 533; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 534; SI-NEXT: s_endpgm 535; 536; VI-LABEL: dynamic_insertelement_v16f32: 537; VI: ; %bb.0: 538; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 539; VI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x40 540; VI-NEXT: s_load_dword s4, s[4:5], 0x80 541; VI-NEXT: v_mov_b32_e32 v16, 0x40a00000 542; VI-NEXT: s_mov_b32 s3, 0x1100f000 543; VI-NEXT: s_mov_b32 s2, -1 544; VI-NEXT: s_waitcnt lgkmcnt(0) 545; VI-NEXT: v_mov_b32_e32 v0, s8 546; VI-NEXT: v_mov_b32_e32 v1, s9 547; VI-NEXT: v_mov_b32_e32 v2, s10 548; VI-NEXT: v_mov_b32_e32 v3, s11 549; VI-NEXT: v_mov_b32_e32 v4, s12 550; VI-NEXT: v_mov_b32_e32 v5, s13 551; VI-NEXT: v_mov_b32_e32 v6, s14 552; VI-NEXT: v_mov_b32_e32 v7, s15 553; VI-NEXT: v_mov_b32_e32 v8, s16 554; VI-NEXT: v_mov_b32_e32 v9, s17 555; VI-NEXT: v_mov_b32_e32 v10, s18 556; VI-NEXT: v_mov_b32_e32 v11, s19 557; VI-NEXT: v_mov_b32_e32 v12, s20 558; VI-NEXT: v_mov_b32_e32 v13, s21 559; VI-NEXT: v_mov_b32_e32 v14, s22 560; VI-NEXT: v_mov_b32_e32 v15, s23 561; VI-NEXT: s_mov_b32 m0, s4 562; VI-NEXT: v_movreld_b32_e32 v0, v16 563; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48 564; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32 565; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 566; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 567; VI-NEXT: s_endpgm 568 %vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b 569 store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64 570 ret void 571} 572 573define amdgpu_kernel void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, i32 %b) nounwind { 574; SI-LABEL: dynamic_insertelement_v2i32: 575; SI: ; %bb.0: 576; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 577; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2 578; SI-NEXT: s_load_dword s4, s[4:5], 0x4 579; SI-NEXT: s_mov_b32 s3, 0x100f000 580; SI-NEXT: s_mov_b32 s2, -1 581; SI-NEXT: s_waitcnt lgkmcnt(0) 582; SI-NEXT: v_mov_b32_e32 v0, s7 583; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 584; SI-NEXT: v_cndmask_b32_e32 v1, 5, v0, vcc 585; SI-NEXT: v_mov_b32_e32 v0, s6 586; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 587; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc 588; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 589; SI-NEXT: s_endpgm 590; 591; VI-LABEL: dynamic_insertelement_v2i32: 592; VI: ; %bb.0: 593; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 594; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8 595; VI-NEXT: s_load_dword s4, s[4:5], 0x10 596; VI-NEXT: s_mov_b32 s3, 0x1100f000 597; VI-NEXT: s_mov_b32 s2, -1 598; VI-NEXT: s_waitcnt lgkmcnt(0) 599; VI-NEXT: s_cmp_lg_u32 s4, 1 600; VI-NEXT: s_cselect_b32 s5, s7, 5 601; VI-NEXT: s_cmp_lg_u32 s4, 0 602; VI-NEXT: s_cselect_b32 s4, s6, 5 603; VI-NEXT: v_mov_b32_e32 v0, s4 604; VI-NEXT: v_mov_b32_e32 v1, s5 605; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 606; VI-NEXT: s_endpgm 607 %vecins = insertelement <2 x i32> %a, i32 5, i32 %b 608 store <2 x i32> %vecins, <2 x i32> addrspace(1)* %out, align 8 609 ret void 610} 611 612define amdgpu_kernel void @dynamic_insertelement_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a, i32 %b) nounwind { 613; SI-LABEL: dynamic_insertelement_v3i32: 614; SI: ; %bb.0: 615; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 616; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4 617; SI-NEXT: s_load_dword s4, s[4:5], 0x8 618; SI-NEXT: s_mov_b32 s3, 0x100f000 619; SI-NEXT: s_mov_b32 s2, -1 620; SI-NEXT: s_waitcnt lgkmcnt(0) 621; SI-NEXT: v_mov_b32_e32 v0, s10 622; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 623; SI-NEXT: v_cndmask_b32_e32 v2, 5, v0, vcc 624; SI-NEXT: v_mov_b32_e32 v0, s9 625; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 626; SI-NEXT: v_cndmask_b32_e32 v1, 5, v0, vcc 627; SI-NEXT: v_mov_b32_e32 v0, s8 628; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 629; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc 630; SI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 631; SI-NEXT: s_endpgm 632; 633; VI-LABEL: dynamic_insertelement_v3i32: 634; VI: ; %bb.0: 635; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 636; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 637; VI-NEXT: s_load_dword s4, s[4:5], 0x20 638; VI-NEXT: s_mov_b32 s3, 0x1100f000 639; VI-NEXT: s_mov_b32 s2, -1 640; VI-NEXT: s_waitcnt lgkmcnt(0) 641; VI-NEXT: s_cmp_lg_u32 s4, 2 642; VI-NEXT: s_cselect_b32 s5, s10, 5 643; VI-NEXT: s_cmp_lg_u32 s4, 1 644; VI-NEXT: s_cselect_b32 s6, s9, 5 645; VI-NEXT: s_cmp_lg_u32 s4, 0 646; VI-NEXT: s_cselect_b32 s4, s8, 5 647; VI-NEXT: v_mov_b32_e32 v0, s4 648; VI-NEXT: v_mov_b32_e32 v1, s6 649; VI-NEXT: v_mov_b32_e32 v2, s5 650; VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 651; VI-NEXT: s_endpgm 652 %vecins = insertelement <3 x i32> %a, i32 5, i32 %b 653 store <3 x i32> %vecins, <3 x i32> addrspace(1)* %out, align 16 654 ret void 655} 656 657define amdgpu_kernel void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, i32 %b, [8 x i32], i32 %val) nounwind { 658; SI-LABEL: dynamic_insertelement_v4i32: 659; SI: ; %bb.0: 660; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 661; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4 662; SI-NEXT: s_load_dword s6, s[4:5], 0x8 663; SI-NEXT: s_load_dword s4, s[4:5], 0x11 664; SI-NEXT: s_mov_b32 s3, 0x100f000 665; SI-NEXT: s_mov_b32 s2, -1 666; SI-NEXT: s_waitcnt lgkmcnt(0) 667; SI-NEXT: v_mov_b32_e32 v0, s11 668; SI-NEXT: v_cmp_eq_u32_e64 vcc, s6, 3 669; SI-NEXT: v_mov_b32_e32 v4, s4 670; SI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc 671; SI-NEXT: v_mov_b32_e32 v0, s10 672; SI-NEXT: v_cmp_eq_u32_e64 vcc, s6, 2 673; SI-NEXT: v_cndmask_b32_e32 v2, v0, v4, vcc 674; SI-NEXT: v_mov_b32_e32 v0, s9 675; SI-NEXT: v_cmp_eq_u32_e64 vcc, s6, 1 676; SI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc 677; SI-NEXT: v_mov_b32_e32 v0, s8 678; SI-NEXT: v_cmp_eq_u32_e64 vcc, s6, 0 679; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc 680; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 681; SI-NEXT: s_endpgm 682; 683; VI-LABEL: dynamic_insertelement_v4i32: 684; VI: ; %bb.0: 685; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 686; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 687; VI-NEXT: s_load_dword s6, s[4:5], 0x20 688; VI-NEXT: s_load_dword s4, s[4:5], 0x44 689; VI-NEXT: s_mov_b32 s3, 0x1100f000 690; VI-NEXT: s_mov_b32 s2, -1 691; VI-NEXT: s_waitcnt lgkmcnt(0) 692; VI-NEXT: s_cmp_eq_u32 s6, 3 693; VI-NEXT: s_cselect_b32 s5, s4, s11 694; VI-NEXT: s_cmp_eq_u32 s6, 2 695; VI-NEXT: s_cselect_b32 s7, s4, s10 696; VI-NEXT: s_cmp_eq_u32 s6, 1 697; VI-NEXT: s_cselect_b32 s9, s4, s9 698; VI-NEXT: s_cmp_eq_u32 s6, 0 699; VI-NEXT: s_cselect_b32 s4, s4, s8 700; VI-NEXT: v_mov_b32_e32 v0, s4 701; VI-NEXT: v_mov_b32_e32 v1, s9 702; VI-NEXT: v_mov_b32_e32 v2, s7 703; VI-NEXT: v_mov_b32_e32 v3, s5 704; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 705; VI-NEXT: s_endpgm 706 %vecins = insertelement <4 x i32> %a, i32 %val, i32 %b 707 store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 708 ret void 709} 710 711define amdgpu_kernel void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, i32 %b) nounwind { 712; SI-LABEL: dynamic_insertelement_v8i32: 713; SI: ; %bb.0: 714; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 715; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8 716; SI-NEXT: s_load_dword s4, s[4:5], 0x10 717; SI-NEXT: s_mov_b32 s3, 0x100f000 718; SI-NEXT: s_mov_b32 s2, -1 719; SI-NEXT: s_waitcnt lgkmcnt(0) 720; SI-NEXT: v_mov_b32_e32 v0, s11 721; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 722; SI-NEXT: v_cndmask_b32_e32 v3, 5, v0, vcc 723; SI-NEXT: v_mov_b32_e32 v0, s10 724; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 725; SI-NEXT: v_cndmask_b32_e32 v2, 5, v0, vcc 726; SI-NEXT: v_mov_b32_e32 v0, s9 727; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 728; SI-NEXT: v_cndmask_b32_e32 v1, 5, v0, vcc 729; SI-NEXT: v_mov_b32_e32 v0, s8 730; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 731; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc 732; SI-NEXT: v_mov_b32_e32 v4, s15 733; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7 734; SI-NEXT: v_cndmask_b32_e32 v7, 5, v4, vcc 735; SI-NEXT: v_mov_b32_e32 v4, s14 736; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6 737; SI-NEXT: v_cndmask_b32_e32 v6, 5, v4, vcc 738; SI-NEXT: v_mov_b32_e32 v4, s13 739; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5 740; SI-NEXT: v_cndmask_b32_e32 v5, 5, v4, vcc 741; SI-NEXT: v_mov_b32_e32 v4, s12 742; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4 743; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc 744; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 745; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 746; SI-NEXT: s_endpgm 747; 748; VI-LABEL: dynamic_insertelement_v8i32: 749; VI: ; %bb.0: 750; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 751; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20 752; VI-NEXT: s_load_dword s4, s[4:5], 0x40 753; VI-NEXT: s_mov_b32 s3, 0x1100f000 754; VI-NEXT: s_mov_b32 s2, -1 755; VI-NEXT: s_waitcnt lgkmcnt(0) 756; VI-NEXT: s_cmp_lg_u32 s4, 3 757; VI-NEXT: s_cselect_b32 s5, s11, 5 758; VI-NEXT: s_cmp_lg_u32 s4, 2 759; VI-NEXT: s_cselect_b32 s6, s10, 5 760; VI-NEXT: s_cmp_lg_u32 s4, 1 761; VI-NEXT: s_cselect_b32 s7, s9, 5 762; VI-NEXT: s_cmp_lg_u32 s4, 0 763; VI-NEXT: s_cselect_b32 s8, s8, 5 764; VI-NEXT: s_cmp_lg_u32 s4, 7 765; VI-NEXT: s_cselect_b32 s9, s15, 5 766; VI-NEXT: s_cmp_lg_u32 s4, 6 767; VI-NEXT: s_cselect_b32 s10, s14, 5 768; VI-NEXT: s_cmp_lg_u32 s4, 5 769; VI-NEXT: s_cselect_b32 s11, s13, 5 770; VI-NEXT: s_cmp_lg_u32 s4, 4 771; VI-NEXT: s_cselect_b32 s4, s12, 5 772; VI-NEXT: v_mov_b32_e32 v0, s4 773; VI-NEXT: v_mov_b32_e32 v1, s11 774; VI-NEXT: v_mov_b32_e32 v2, s10 775; VI-NEXT: v_mov_b32_e32 v3, s9 776; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16 777; VI-NEXT: s_nop 0 778; VI-NEXT: v_mov_b32_e32 v0, s8 779; VI-NEXT: v_mov_b32_e32 v1, s7 780; VI-NEXT: v_mov_b32_e32 v2, s6 781; VI-NEXT: v_mov_b32_e32 v3, s5 782; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 783; VI-NEXT: s_endpgm 784 %vecins = insertelement <8 x i32> %a, i32 5, i32 %b 785 store <8 x i32> %vecins, <8 x i32> addrspace(1)* %out, align 32 786 ret void 787} 788 789define amdgpu_kernel void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, i32 %b) nounwind { 790; SI-LABEL: dynamic_insertelement_v16i32: 791; SI: ; %bb.0: 792; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 793; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x10 794; SI-NEXT: s_load_dword s4, s[4:5], 0x20 795; SI-NEXT: s_mov_b32 s3, 0x100f000 796; SI-NEXT: s_mov_b32 s2, -1 797; SI-NEXT: s_waitcnt lgkmcnt(0) 798; SI-NEXT: v_mov_b32_e32 v0, s8 799; SI-NEXT: v_mov_b32_e32 v1, s9 800; SI-NEXT: v_mov_b32_e32 v2, s10 801; SI-NEXT: v_mov_b32_e32 v3, s11 802; SI-NEXT: v_mov_b32_e32 v4, s12 803; SI-NEXT: v_mov_b32_e32 v5, s13 804; SI-NEXT: v_mov_b32_e32 v6, s14 805; SI-NEXT: v_mov_b32_e32 v7, s15 806; SI-NEXT: v_mov_b32_e32 v8, s16 807; SI-NEXT: v_mov_b32_e32 v9, s17 808; SI-NEXT: v_mov_b32_e32 v10, s18 809; SI-NEXT: v_mov_b32_e32 v11, s19 810; SI-NEXT: v_mov_b32_e32 v12, s20 811; SI-NEXT: v_mov_b32_e32 v13, s21 812; SI-NEXT: v_mov_b32_e32 v14, s22 813; SI-NEXT: v_mov_b32_e32 v15, s23 814; SI-NEXT: s_mov_b32 m0, s4 815; SI-NEXT: v_movreld_b32_e32 v0, 5 816; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48 817; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32 818; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 819; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 820; SI-NEXT: s_endpgm 821; 822; VI-LABEL: dynamic_insertelement_v16i32: 823; VI: ; %bb.0: 824; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 825; VI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x40 826; VI-NEXT: s_load_dword s4, s[4:5], 0x80 827; VI-NEXT: s_mov_b32 s3, 0x1100f000 828; VI-NEXT: s_mov_b32 s2, -1 829; VI-NEXT: s_waitcnt lgkmcnt(0) 830; VI-NEXT: v_mov_b32_e32 v0, s8 831; VI-NEXT: v_mov_b32_e32 v1, s9 832; VI-NEXT: v_mov_b32_e32 v2, s10 833; VI-NEXT: v_mov_b32_e32 v3, s11 834; VI-NEXT: v_mov_b32_e32 v4, s12 835; VI-NEXT: v_mov_b32_e32 v5, s13 836; VI-NEXT: v_mov_b32_e32 v6, s14 837; VI-NEXT: v_mov_b32_e32 v7, s15 838; VI-NEXT: v_mov_b32_e32 v8, s16 839; VI-NEXT: v_mov_b32_e32 v9, s17 840; VI-NEXT: v_mov_b32_e32 v10, s18 841; VI-NEXT: v_mov_b32_e32 v11, s19 842; VI-NEXT: v_mov_b32_e32 v12, s20 843; VI-NEXT: v_mov_b32_e32 v13, s21 844; VI-NEXT: v_mov_b32_e32 v14, s22 845; VI-NEXT: v_mov_b32_e32 v15, s23 846; VI-NEXT: s_mov_b32 m0, s4 847; VI-NEXT: v_movreld_b32_e32 v0, 5 848; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48 849; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32 850; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 851; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 852; VI-NEXT: s_endpgm 853 %vecins = insertelement <16 x i32> %a, i32 5, i32 %b 854 store <16 x i32> %vecins, <16 x i32> addrspace(1)* %out, align 64 855 ret void 856} 857 858define amdgpu_kernel void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, i32 %b) nounwind { 859; SI-LABEL: dynamic_insertelement_v2i16: 860; SI: ; %bb.0: 861; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 862; SI-NEXT: s_load_dword s6, s[4:5], 0x2 863; SI-NEXT: s_load_dword s4, s[4:5], 0x3 864; SI-NEXT: s_mov_b32 s3, 0x100f000 865; SI-NEXT: s_mov_b32 s2, -1 866; SI-NEXT: s_waitcnt lgkmcnt(0) 867; SI-NEXT: s_lshl_b32 s4, s4, 4 868; SI-NEXT: s_lshl_b32 s4, 0xffff, s4 869; SI-NEXT: s_andn2_b32 s5, s6, s4 870; SI-NEXT: s_and_b32 s4, s4, 0x50005 871; SI-NEXT: s_or_b32 s4, s4, s5 872; SI-NEXT: v_mov_b32_e32 v0, s4 873; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 874; SI-NEXT: s_endpgm 875; 876; VI-LABEL: dynamic_insertelement_v2i16: 877; VI: ; %bb.0: 878; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 879; VI-NEXT: s_load_dword s6, s[4:5], 0x8 880; VI-NEXT: s_load_dword s4, s[4:5], 0xc 881; VI-NEXT: s_mov_b32 s3, 0x1100f000 882; VI-NEXT: s_mov_b32 s2, -1 883; VI-NEXT: s_waitcnt lgkmcnt(0) 884; VI-NEXT: s_lshl_b32 s4, s4, 4 885; VI-NEXT: s_lshl_b32 s4, 0xffff, s4 886; VI-NEXT: s_andn2_b32 s5, s6, s4 887; VI-NEXT: s_and_b32 s4, s4, 0x50005 888; VI-NEXT: s_or_b32 s4, s4, s5 889; VI-NEXT: v_mov_b32_e32 v0, s4 890; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 891; VI-NEXT: s_endpgm 892 %vecins = insertelement <2 x i16> %a, i16 5, i32 %b 893 store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out, align 8 894 ret void 895} 896 897define amdgpu_kernel void @dynamic_insertelement_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %a, i32 %b) nounwind { 898; SI-LABEL: dynamic_insertelement_v3i16: 899; SI: ; %bb.0: 900; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 901; SI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x2 902; SI-NEXT: s_load_dword s4, s[4:5], 0x4 903; SI-NEXT: s_mov_b32 s5, 0 904; SI-NEXT: s_mov_b32 s3, 0x100f000 905; SI-NEXT: s_mov_b32 s2, -1 906; SI-NEXT: s_waitcnt lgkmcnt(0) 907; SI-NEXT: s_lshl_b32 s8, s4, 4 908; SI-NEXT: s_mov_b32 s4, 0xffff 909; SI-NEXT: s_lshl_b64 s[4:5], s[4:5], s8 910; SI-NEXT: s_mov_b32 s8, 0x50005 911; SI-NEXT: s_and_b32 s9, s5, s8 912; SI-NEXT: s_and_b32 s8, s4, s8 913; SI-NEXT: s_andn2_b64 s[4:5], s[6:7], s[4:5] 914; SI-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5] 915; SI-NEXT: v_mov_b32_e32 v0, s5 916; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4 917; SI-NEXT: v_mov_b32_e32 v0, s4 918; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 919; SI-NEXT: s_endpgm 920; 921; VI-LABEL: dynamic_insertelement_v3i16: 922; VI: ; %bb.0: 923; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 924; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x8 925; VI-NEXT: s_load_dword s4, s[4:5], 0x10 926; VI-NEXT: s_mov_b32 s5, 0 927; VI-NEXT: s_mov_b32 s3, 0x1100f000 928; VI-NEXT: s_mov_b32 s2, -1 929; VI-NEXT: s_waitcnt lgkmcnt(0) 930; VI-NEXT: s_lshl_b32 s8, s4, 4 931; VI-NEXT: s_mov_b32 s4, 0xffff 932; VI-NEXT: s_lshl_b64 s[4:5], s[4:5], s8 933; VI-NEXT: s_mov_b32 s8, 0x50005 934; VI-NEXT: s_mov_b32 s9, s8 935; VI-NEXT: s_andn2_b64 s[6:7], s[6:7], s[4:5] 936; VI-NEXT: s_and_b64 s[4:5], s[4:5], s[8:9] 937; VI-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] 938; VI-NEXT: v_mov_b32_e32 v0, s5 939; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4 940; VI-NEXT: v_mov_b32_e32 v0, s4 941; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 942; VI-NEXT: s_endpgm 943 %vecins = insertelement <3 x i16> %a, i16 5, i32 %b 944 store <3 x i16> %vecins, <3 x i16> addrspace(1)* %out, align 8 945 ret void 946} 947 948define amdgpu_kernel void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, [8 x i32], <2 x i8> %a, [8 x i32], i32 %b) nounwind { 949; SI-LABEL: dynamic_insertelement_v2i8: 950; SI: ; %bb.0: 951; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 952; SI-NEXT: s_load_dword s6, s[4:5], 0xa 953; SI-NEXT: s_load_dword s4, s[4:5], 0x13 954; SI-NEXT: s_mov_b32 s3, 0x100f000 955; SI-NEXT: s_mov_b32 s2, -1 956; SI-NEXT: s_waitcnt lgkmcnt(0) 957; SI-NEXT: s_lshl_b32 s4, s4, 3 958; SI-NEXT: s_lshl_b32 s4, -1, s4 959; SI-NEXT: s_andn2_b32 s5, s6, s4 960; SI-NEXT: s_and_b32 s4, s4, 0x505 961; SI-NEXT: s_or_b32 s4, s4, s5 962; SI-NEXT: v_mov_b32_e32 v0, s4 963; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 964; SI-NEXT: s_endpgm 965; 966; VI-LABEL: dynamic_insertelement_v2i8: 967; VI: ; %bb.0: 968; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 969; VI-NEXT: s_load_dword s6, s[4:5], 0x28 970; VI-NEXT: s_load_dword s4, s[4:5], 0x4c 971; VI-NEXT: s_mov_b32 s3, 0x1100f000 972; VI-NEXT: s_mov_b32 s2, -1 973; VI-NEXT: s_waitcnt lgkmcnt(0) 974; VI-NEXT: s_lshl_b32 s4, s4, 3 975; VI-NEXT: v_lshlrev_b16_e64 v0, s4, -1 976; VI-NEXT: v_not_b32_e32 v1, v0 977; VI-NEXT: v_and_b32_e32 v1, s6, v1 978; VI-NEXT: v_and_b32_e32 v0, 0x505, v0 979; VI-NEXT: v_or_b32_e32 v0, v0, v1 980; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 981; VI-NEXT: s_endpgm 982 %vecins = insertelement <2 x i8> %a, i8 5, i32 %b 983 store <2 x i8> %vecins, <2 x i8> addrspace(1)* %out, align 8 984 ret void 985} 986 987; FIXME: post legalize i16 and i32 shifts aren't merged because of 988; isTypeDesirableForOp in SimplifyDemandedBits 989define amdgpu_kernel void @dynamic_insertelement_v3i8(<3 x i8> addrspace(1)* %out, [8 x i32], <3 x i8> %a, [8 x i32], i32 %b) nounwind { 990; SI-LABEL: dynamic_insertelement_v3i8: 991; SI: ; %bb.0: 992; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 993; SI-NEXT: s_load_dword s6, s[4:5], 0xa 994; SI-NEXT: s_load_dword s4, s[4:5], 0x13 995; SI-NEXT: s_mov_b32 s3, 0x100f000 996; SI-NEXT: s_mov_b32 s2, -1 997; SI-NEXT: s_waitcnt lgkmcnt(0) 998; SI-NEXT: s_lshl_b32 s4, s4, 3 999; SI-NEXT: s_lshl_b32 s4, 0xffff, s4 1000; SI-NEXT: s_andn2_b32 s5, s6, s4 1001; SI-NEXT: s_and_b32 s4, s4, 0x5050505 1002; SI-NEXT: s_or_b32 s4, s4, s5 1003; SI-NEXT: v_mov_b32_e32 v0, s4 1004; SI-NEXT: s_lshr_b32 s5, s4, 16 1005; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 1006; SI-NEXT: v_mov_b32_e32 v0, s5 1007; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:2 1008; SI-NEXT: s_endpgm 1009; 1010; VI-LABEL: dynamic_insertelement_v3i8: 1011; VI: ; %bb.0: 1012; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1013; VI-NEXT: s_load_dword s6, s[4:5], 0x28 1014; VI-NEXT: s_load_dword s4, s[4:5], 0x4c 1015; VI-NEXT: s_mov_b32 s3, 0x1100f000 1016; VI-NEXT: s_mov_b32 s2, -1 1017; VI-NEXT: s_waitcnt lgkmcnt(0) 1018; VI-NEXT: s_lshl_b32 s4, s4, 3 1019; VI-NEXT: s_lshl_b32 s4, 0xffff, s4 1020; VI-NEXT: s_andn2_b32 s5, s6, s4 1021; VI-NEXT: s_and_b32 s4, s4, 0x5050505 1022; VI-NEXT: s_or_b32 s4, s4, s5 1023; VI-NEXT: v_mov_b32_e32 v0, s4 1024; VI-NEXT: s_lshr_b32 s5, s4, 16 1025; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 1026; VI-NEXT: v_mov_b32_e32 v0, s5 1027; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:2 1028; VI-NEXT: s_endpgm 1029 %vecins = insertelement <3 x i8> %a, i8 5, i32 %b 1030 store <3 x i8> %vecins, <3 x i8> addrspace(1)* %out, align 4 1031 ret void 1032} 1033 1034define amdgpu_kernel void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, [8 x i32], <4 x i8> %a, [8 x i32], i32 %b) nounwind { 1035; SI-LABEL: dynamic_insertelement_v4i8: 1036; SI: ; %bb.0: 1037; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1038; SI-NEXT: s_load_dword s6, s[4:5], 0xa 1039; SI-NEXT: s_load_dword s4, s[4:5], 0x13 1040; SI-NEXT: s_mov_b32 s3, 0x100f000 1041; SI-NEXT: s_mov_b32 s2, -1 1042; SI-NEXT: s_waitcnt lgkmcnt(0) 1043; SI-NEXT: s_lshl_b32 s4, s4, 3 1044; SI-NEXT: s_lshl_b32 s4, 0xffff, s4 1045; SI-NEXT: s_andn2_b32 s5, s6, s4 1046; SI-NEXT: s_and_b32 s4, s4, 0x5050505 1047; SI-NEXT: s_or_b32 s4, s4, s5 1048; SI-NEXT: v_mov_b32_e32 v0, s4 1049; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1050; SI-NEXT: s_endpgm 1051; 1052; VI-LABEL: dynamic_insertelement_v4i8: 1053; VI: ; %bb.0: 1054; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1055; VI-NEXT: s_load_dword s6, s[4:5], 0x28 1056; VI-NEXT: s_load_dword s4, s[4:5], 0x4c 1057; VI-NEXT: s_mov_b32 s3, 0x1100f000 1058; VI-NEXT: s_mov_b32 s2, -1 1059; VI-NEXT: s_waitcnt lgkmcnt(0) 1060; VI-NEXT: s_lshl_b32 s4, s4, 3 1061; VI-NEXT: s_lshl_b32 s4, 0xffff, s4 1062; VI-NEXT: s_andn2_b32 s5, s6, s4 1063; VI-NEXT: s_and_b32 s4, s4, 0x5050505 1064; VI-NEXT: s_or_b32 s4, s4, s5 1065; VI-NEXT: v_mov_b32_e32 v0, s4 1066; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 1067; VI-NEXT: s_endpgm 1068 %vecins = insertelement <4 x i8> %a, i8 5, i32 %b 1069 store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 4 1070 ret void 1071} 1072 1073define amdgpu_kernel void @s_dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(4)* %a.ptr, i32 %b) nounwind { 1074; SI-LABEL: s_dynamic_insertelement_v8i8: 1075; SI: ; %bb.0: 1076; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 1077; SI-NEXT: s_load_dword s6, s[4:5], 0x4 1078; SI-NEXT: s_mov_b32 s7, 0 1079; SI-NEXT: s_mov_b32 s3, 0x100f000 1080; SI-NEXT: s_mov_b32 s2, -1 1081; SI-NEXT: s_waitcnt lgkmcnt(0) 1082; SI-NEXT: s_load_dwordx2 s[4:5], s[10:11], 0x0 1083; SI-NEXT: s_mov_b32 s0, s8 1084; SI-NEXT: s_lshl_b32 s8, s6, 3 1085; SI-NEXT: s_mov_b32 s6, 0xffff 1086; SI-NEXT: s_lshl_b64 s[6:7], s[6:7], s8 1087; SI-NEXT: s_mov_b32 s8, 0x5050505 1088; SI-NEXT: s_mov_b32 s1, s9 1089; SI-NEXT: s_and_b32 s9, s7, s8 1090; SI-NEXT: s_and_b32 s8, s6, s8 1091; SI-NEXT: s_waitcnt lgkmcnt(0) 1092; SI-NEXT: s_andn2_b64 s[4:5], s[4:5], s[6:7] 1093; SI-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5] 1094; SI-NEXT: v_mov_b32_e32 v0, s4 1095; SI-NEXT: v_mov_b32_e32 v1, s5 1096; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1097; SI-NEXT: s_endpgm 1098; 1099; VI-LABEL: s_dynamic_insertelement_v8i8: 1100; VI: ; %bb.0: 1101; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0 1102; VI-NEXT: s_load_dword s6, s[4:5], 0x10 1103; VI-NEXT: s_mov_b32 s7, 0 1104; VI-NEXT: s_mov_b32 s3, 0x1100f000 1105; VI-NEXT: s_mov_b32 s2, -1 1106; VI-NEXT: s_waitcnt lgkmcnt(0) 1107; VI-NEXT: s_load_dwordx2 s[4:5], s[10:11], 0x0 1108; VI-NEXT: s_mov_b32 s0, s8 1109; VI-NEXT: s_lshl_b32 s8, s6, 3 1110; VI-NEXT: s_mov_b32 s6, 0xffff 1111; VI-NEXT: s_lshl_b64 s[6:7], s[6:7], s8 1112; VI-NEXT: s_mov_b32 s8, 0x5050505 1113; VI-NEXT: s_mov_b32 s1, s9 1114; VI-NEXT: s_and_b32 s9, s7, s8 1115; VI-NEXT: s_and_b32 s8, s6, s8 1116; VI-NEXT: s_waitcnt lgkmcnt(0) 1117; VI-NEXT: s_andn2_b64 s[4:5], s[4:5], s[6:7] 1118; VI-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5] 1119; VI-NEXT: v_mov_b32_e32 v0, s4 1120; VI-NEXT: v_mov_b32_e32 v1, s5 1121; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1122; VI-NEXT: s_endpgm 1123 %a = load <8 x i8>, <8 x i8> addrspace(4)* %a.ptr, align 4 1124 %vecins = insertelement <8 x i8> %a, i8 5, i32 %b 1125 store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 8 1126 ret void 1127} 1128 1129define amdgpu_kernel void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> %a, i32 %b) nounwind { 1130; SI-LABEL: dynamic_insertelement_v16i8: 1131; SI: ; %bb.0: 1132; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1133; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4 1134; SI-NEXT: s_load_dword s4, s[4:5], 0x8 1135; SI-NEXT: s_mov_b32 s3, 0x100f000 1136; SI-NEXT: s_mov_b32 s2, -1 1137; SI-NEXT: s_waitcnt lgkmcnt(0) 1138; SI-NEXT: s_lshr_b32 s5, s11, 24 1139; SI-NEXT: v_mov_b32_e32 v0, s5 1140; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 15 1141; SI-NEXT: s_lshr_b32 s5, s11, 16 1142; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc 1143; SI-NEXT: v_mov_b32_e32 v1, s5 1144; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 14 1145; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc 1146; SI-NEXT: s_movk_i32 s5, 0xff 1147; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0 1148; SI-NEXT: v_and_b32_e32 v1, s5, v1 1149; SI-NEXT: s_lshr_b32 s6, s11, 8 1150; SI-NEXT: v_or_b32_e32 v0, v1, v0 1151; SI-NEXT: v_mov_b32_e32 v1, s6 1152; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 13 1153; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc 1154; SI-NEXT: v_mov_b32_e32 v2, s11 1155; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 12 1156; SI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc 1157; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 1158; SI-NEXT: v_and_b32_e32 v2, s5, v2 1159; SI-NEXT: v_or_b32_e32 v1, v2, v1 1160; SI-NEXT: s_mov_b32 s6, 0xffff 1161; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 1162; SI-NEXT: v_and_b32_e32 v1, s6, v1 1163; SI-NEXT: s_lshr_b32 s7, s10, 24 1164; SI-NEXT: v_or_b32_e32 v3, v1, v0 1165; SI-NEXT: v_mov_b32_e32 v0, s7 1166; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 11 1167; SI-NEXT: s_lshr_b32 s7, s10, 16 1168; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc 1169; SI-NEXT: v_mov_b32_e32 v1, s7 1170; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 10 1171; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc 1172; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0 1173; SI-NEXT: v_and_b32_e32 v1, s5, v1 1174; SI-NEXT: s_lshr_b32 s7, s10, 8 1175; SI-NEXT: v_or_b32_e32 v0, v1, v0 1176; SI-NEXT: v_mov_b32_e32 v1, s7 1177; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 9 1178; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc 1179; SI-NEXT: v_mov_b32_e32 v2, s10 1180; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 8 1181; SI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc 1182; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 1183; SI-NEXT: v_and_b32_e32 v2, s5, v2 1184; SI-NEXT: v_or_b32_e32 v1, v2, v1 1185; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 1186; SI-NEXT: v_and_b32_e32 v1, s6, v1 1187; SI-NEXT: s_lshr_b32 s7, s9, 24 1188; SI-NEXT: v_or_b32_e32 v2, v1, v0 1189; SI-NEXT: v_mov_b32_e32 v0, s7 1190; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7 1191; SI-NEXT: s_lshr_b32 s7, s9, 16 1192; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc 1193; SI-NEXT: v_mov_b32_e32 v1, s7 1194; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6 1195; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc 1196; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0 1197; SI-NEXT: v_and_b32_e32 v1, s5, v1 1198; SI-NEXT: s_lshr_b32 s7, s9, 8 1199; SI-NEXT: v_or_b32_e32 v0, v1, v0 1200; SI-NEXT: v_mov_b32_e32 v1, s7 1201; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5 1202; SI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc 1203; SI-NEXT: v_mov_b32_e32 v4, s9 1204; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4 1205; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc 1206; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v1 1207; SI-NEXT: v_and_b32_e32 v4, s5, v4 1208; SI-NEXT: v_or_b32_e32 v1, v4, v1 1209; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 1210; SI-NEXT: v_and_b32_e32 v1, s6, v1 1211; SI-NEXT: s_lshr_b32 s7, s8, 24 1212; SI-NEXT: v_or_b32_e32 v1, v1, v0 1213; SI-NEXT: v_mov_b32_e32 v0, s7 1214; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 1215; SI-NEXT: s_lshr_b32 s7, s8, 16 1216; SI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc 1217; SI-NEXT: v_mov_b32_e32 v4, s7 1218; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 1219; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc 1220; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0 1221; SI-NEXT: v_and_b32_e32 v4, s5, v4 1222; SI-NEXT: s_lshr_b32 s7, s8, 8 1223; SI-NEXT: v_or_b32_e32 v0, v4, v0 1224; SI-NEXT: v_mov_b32_e32 v4, s7 1225; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 1226; SI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc 1227; SI-NEXT: v_mov_b32_e32 v5, s8 1228; SI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 1229; SI-NEXT: v_cndmask_b32_e32 v5, 5, v5, vcc 1230; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4 1231; SI-NEXT: v_and_b32_e32 v5, s5, v5 1232; SI-NEXT: v_or_b32_e32 v4, v5, v4 1233; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 1234; SI-NEXT: v_and_b32_e32 v4, s6, v4 1235; SI-NEXT: v_or_b32_e32 v0, v4, v0 1236; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 1237; SI-NEXT: s_endpgm 1238; 1239; VI-LABEL: dynamic_insertelement_v16i8: 1240; VI: ; %bb.0: 1241; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1242; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 1243; VI-NEXT: s_load_dword s4, s[4:5], 0x20 1244; VI-NEXT: s_mov_b32 s3, 0x1100f000 1245; VI-NEXT: s_mov_b32 s2, -1 1246; VI-NEXT: s_waitcnt lgkmcnt(0) 1247; VI-NEXT: s_lshr_b32 s5, s11, 24 1248; VI-NEXT: v_mov_b32_e32 v0, s5 1249; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 15 1250; VI-NEXT: s_lshr_b32 s5, s11, 16 1251; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc 1252; VI-NEXT: v_mov_b32_e32 v1, s5 1253; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 14 1254; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc 1255; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 1256; VI-NEXT: s_lshr_b32 s5, s11, 8 1257; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD 1258; VI-NEXT: v_mov_b32_e32 v1, s5 1259; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 13 1260; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc 1261; VI-NEXT: v_mov_b32_e32 v2, s11 1262; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 12 1263; VI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc 1264; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1 1265; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD 1266; VI-NEXT: s_lshr_b32 s5, s10, 24 1267; VI-NEXT: v_or_b32_sdwa v3, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1268; VI-NEXT: v_mov_b32_e32 v0, s5 1269; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 11 1270; VI-NEXT: s_lshr_b32 s5, s10, 16 1271; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc 1272; VI-NEXT: v_mov_b32_e32 v1, s5 1273; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 10 1274; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc 1275; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 1276; VI-NEXT: s_lshr_b32 s5, s10, 8 1277; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD 1278; VI-NEXT: v_mov_b32_e32 v1, s5 1279; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 9 1280; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc 1281; VI-NEXT: v_mov_b32_e32 v2, s10 1282; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 8 1283; VI-NEXT: v_cndmask_b32_e32 v2, 5, v2, vcc 1284; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1 1285; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD 1286; VI-NEXT: s_lshr_b32 s5, s9, 24 1287; VI-NEXT: v_or_b32_sdwa v2, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1288; VI-NEXT: v_mov_b32_e32 v0, s5 1289; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 7 1290; VI-NEXT: s_lshr_b32 s5, s9, 16 1291; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc 1292; VI-NEXT: v_mov_b32_e32 v1, s5 1293; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 6 1294; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc 1295; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 1296; VI-NEXT: s_lshr_b32 s5, s9, 8 1297; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD 1298; VI-NEXT: v_mov_b32_e32 v1, s5 1299; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 5 1300; VI-NEXT: v_cndmask_b32_e32 v1, 5, v1, vcc 1301; VI-NEXT: v_mov_b32_e32 v4, s9 1302; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 4 1303; VI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc 1304; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1 1305; VI-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD 1306; VI-NEXT: s_lshr_b32 s5, s8, 24 1307; VI-NEXT: v_or_b32_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1308; VI-NEXT: v_mov_b32_e32 v0, s5 1309; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 3 1310; VI-NEXT: s_lshr_b32 s5, s8, 16 1311; VI-NEXT: v_cndmask_b32_e32 v0, 5, v0, vcc 1312; VI-NEXT: v_mov_b32_e32 v4, s5 1313; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 2 1314; VI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc 1315; VI-NEXT: v_lshlrev_b16_e32 v0, 8, v0 1316; VI-NEXT: s_lshr_b32 s5, s8, 8 1317; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD 1318; VI-NEXT: v_mov_b32_e32 v4, s5 1319; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 1 1320; VI-NEXT: v_cndmask_b32_e32 v4, 5, v4, vcc 1321; VI-NEXT: v_mov_b32_e32 v5, s8 1322; VI-NEXT: v_cmp_ne_u32_e64 vcc, s4, 0 1323; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v4 1324; VI-NEXT: v_cndmask_b32_e32 v5, 5, v5, vcc 1325; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD 1326; VI-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 1327; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 1328; VI-NEXT: s_endpgm 1329 %vecins = insertelement <16 x i8> %a, i8 5, i32 %b 1330 store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16 1331 ret void 1332} 1333 1334; This test requires handling INSERT_SUBREG in SIFixSGPRCopies. Check that 1335; the compiler doesn't crash. 1336define amdgpu_kernel void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) { 1337; SI-LABEL: insert_split_bb: 1338; SI: ; %bb.0: ; %entry 1339; SI-NEXT: s_load_dword s0, s[4:5], 0x4 1340; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 1341; SI-NEXT: s_waitcnt lgkmcnt(0) 1342; SI-NEXT: s_cmp_lg_u32 s0, 0 1343; SI-NEXT: s_cbranch_scc0 BB26_2 1344; SI-NEXT: ; %bb.1: ; %else 1345; SI-NEXT: s_load_dword s1, s[6:7], 0x1 1346; SI-NEXT: s_mov_b64 s[2:3], 0 1347; SI-NEXT: s_andn2_b64 vcc, exec, s[2:3] 1348; SI-NEXT: s_waitcnt lgkmcnt(0) 1349; SI-NEXT: s_mov_b64 vcc, vcc 1350; SI-NEXT: s_cbranch_vccz BB26_3 1351; SI-NEXT: s_branch BB26_4 1352; SI-NEXT: BB26_2: 1353; SI-NEXT: BB26_3: ; %if 1354; SI-NEXT: s_load_dword s1, s[6:7], 0x0 1355; SI-NEXT: BB26_4: ; %endif 1356; SI-NEXT: s_waitcnt lgkmcnt(0) 1357; SI-NEXT: v_mov_b32_e32 v0, s0 1358; SI-NEXT: s_mov_b32 s7, 0x100f000 1359; SI-NEXT: s_mov_b32 s6, -1 1360; SI-NEXT: v_mov_b32_e32 v1, s1 1361; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1362; SI-NEXT: s_endpgm 1363; 1364; VI-LABEL: insert_split_bb: 1365; VI: ; %bb.0: ; %entry 1366; VI-NEXT: s_load_dword s0, s[4:5], 0x10 1367; VI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 1368; VI-NEXT: s_waitcnt lgkmcnt(0) 1369; VI-NEXT: s_cmp_lg_u32 s0, 0 1370; VI-NEXT: s_cbranch_scc0 BB26_2 1371; VI-NEXT: ; %bb.1: ; %else 1372; VI-NEXT: s_load_dword s1, s[6:7], 0x4 1373; VI-NEXT: s_cbranch_execz BB26_3 1374; VI-NEXT: s_branch BB26_4 1375; VI-NEXT: BB26_2: 1376; VI-NEXT: BB26_3: ; %if 1377; VI-NEXT: s_waitcnt lgkmcnt(0) 1378; VI-NEXT: s_load_dword s1, s[6:7], 0x0 1379; VI-NEXT: BB26_4: ; %endif 1380; VI-NEXT: s_waitcnt lgkmcnt(0) 1381; VI-NEXT: v_mov_b32_e32 v0, s0 1382; VI-NEXT: s_mov_b32 s7, 0x1100f000 1383; VI-NEXT: s_mov_b32 s6, -1 1384; VI-NEXT: v_mov_b32_e32 v1, s1 1385; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1386; VI-NEXT: s_endpgm 1387entry: 1388 %0 = insertelement <2 x i32> undef, i32 %a, i32 0 1389 %1 = icmp eq i32 %a, 0 1390 br i1 %1, label %if, label %else 1391 1392if: 1393 %2 = load i32, i32 addrspace(1)* %in 1394 %3 = insertelement <2 x i32> %0, i32 %2, i32 1 1395 br label %endif 1396 1397else: 1398 %4 = getelementptr i32, i32 addrspace(1)* %in, i32 1 1399 %5 = load i32, i32 addrspace(1)* %4 1400 %6 = insertelement <2 x i32> %0, i32 %5, i32 1 1401 br label %endif 1402 1403endif: 1404 %7 = phi <2 x i32> [%3, %if], [%6, %else] 1405 store <2 x i32> %7, <2 x i32> addrspace(1)* %out 1406 ret void 1407} 1408 1409define amdgpu_kernel void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, [8 x i32], <2 x double> %a, [8 x i32], i32 %b) nounwind { 1410; SI-LABEL: dynamic_insertelement_v2f64: 1411; SI: ; %bb.0: 1412; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1413; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xc 1414; SI-NEXT: s_load_dword s4, s[4:5], 0x18 1415; SI-NEXT: v_mov_b32_e32 v1, 0x40200000 1416; SI-NEXT: s_mov_b32 s3, 0x100f000 1417; SI-NEXT: s_mov_b32 s2, -1 1418; SI-NEXT: s_waitcnt lgkmcnt(0) 1419; SI-NEXT: v_mov_b32_e32 v0, s11 1420; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1 1421; SI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc 1422; SI-NEXT: v_mov_b32_e32 v0, s10 1423; SI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc 1424; SI-NEXT: v_mov_b32_e32 v0, s9 1425; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0 1426; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 1427; SI-NEXT: v_mov_b32_e32 v0, s8 1428; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 1429; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 1430; SI-NEXT: s_endpgm 1431; 1432; VI-LABEL: dynamic_insertelement_v2f64: 1433; VI: ; %bb.0: 1434; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1435; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x30 1436; VI-NEXT: s_load_dword s4, s[4:5], 0x60 1437; VI-NEXT: v_mov_b32_e32 v1, 0x40200000 1438; VI-NEXT: s_mov_b32 s3, 0x1100f000 1439; VI-NEXT: s_mov_b32 s2, -1 1440; VI-NEXT: s_waitcnt lgkmcnt(0) 1441; VI-NEXT: v_mov_b32_e32 v0, s11 1442; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1 1443; VI-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc 1444; VI-NEXT: v_mov_b32_e32 v0, s10 1445; VI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc 1446; VI-NEXT: v_mov_b32_e32 v0, s9 1447; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0 1448; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc 1449; VI-NEXT: v_mov_b32_e32 v0, s8 1450; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 1451; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 1452; VI-NEXT: s_endpgm 1453 %vecins = insertelement <2 x double> %a, double 8.0, i32 %b 1454 store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16 1455 ret void 1456} 1457 1458define amdgpu_kernel void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind { 1459; SI-LABEL: dynamic_insertelement_v2i64: 1460; SI: ; %bb.0: 1461; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1462; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x4 1463; SI-NEXT: s_load_dword s6, s[4:5], 0x8 1464; SI-NEXT: s_mov_b32 s3, 0x100f000 1465; SI-NEXT: s_mov_b32 s2, -1 1466; SI-NEXT: s_waitcnt lgkmcnt(0) 1467; SI-NEXT: v_mov_b32_e32 v0, s11 1468; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 1 1469; SI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] 1470; SI-NEXT: v_mov_b32_e32 v0, s10 1471; SI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5] 1472; SI-NEXT: v_mov_b32_e32 v0, s9 1473; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 0 1474; SI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5] 1475; SI-NEXT: v_mov_b32_e32 v0, s8 1476; SI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5] 1477; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 1478; SI-NEXT: s_endpgm 1479; 1480; VI-LABEL: dynamic_insertelement_v2i64: 1481; VI: ; %bb.0: 1482; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1483; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x10 1484; VI-NEXT: s_load_dword s6, s[4:5], 0x20 1485; VI-NEXT: s_mov_b32 s3, 0x1100f000 1486; VI-NEXT: s_mov_b32 s2, -1 1487; VI-NEXT: s_waitcnt lgkmcnt(0) 1488; VI-NEXT: v_mov_b32_e32 v0, s11 1489; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 1 1490; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] 1491; VI-NEXT: v_mov_b32_e32 v0, s10 1492; VI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5] 1493; VI-NEXT: v_mov_b32_e32 v0, s9 1494; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 0 1495; VI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5] 1496; VI-NEXT: v_mov_b32_e32 v0, s8 1497; VI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5] 1498; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 1499; VI-NEXT: s_endpgm 1500 %vecins = insertelement <2 x i64> %a, i64 5, i32 %b 1501 store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8 1502 ret void 1503} 1504 1505define amdgpu_kernel void @dynamic_insertelement_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %a, i32 %b) nounwind { 1506; SI-LABEL: dynamic_insertelement_v3i64: 1507; SI: ; %bb.0: 1508; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1509; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8 1510; SI-NEXT: s_load_dword s6, s[4:5], 0x10 1511; SI-NEXT: s_mov_b32 s3, 0x100f000 1512; SI-NEXT: s_mov_b32 s2, -1 1513; SI-NEXT: s_waitcnt lgkmcnt(0) 1514; SI-NEXT: v_mov_b32_e32 v0, s13 1515; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 2 1516; SI-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5] 1517; SI-NEXT: v_mov_b32_e32 v0, s12 1518; SI-NEXT: v_cndmask_b32_e64 v4, v0, 5, s[4:5] 1519; SI-NEXT: v_mov_b32_e32 v0, s11 1520; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 1 1521; SI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] 1522; SI-NEXT: v_mov_b32_e32 v0, s10 1523; SI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5] 1524; SI-NEXT: v_mov_b32_e32 v0, s9 1525; SI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 0 1526; SI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5] 1527; SI-NEXT: v_mov_b32_e32 v0, s8 1528; SI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5] 1529; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16 1530; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 1531; SI-NEXT: s_endpgm 1532; 1533; VI-LABEL: dynamic_insertelement_v3i64: 1534; VI: ; %bb.0: 1535; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1536; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20 1537; VI-NEXT: s_load_dword s6, s[4:5], 0x40 1538; VI-NEXT: s_mov_b32 s3, 0x1100f000 1539; VI-NEXT: s_mov_b32 s2, -1 1540; VI-NEXT: s_waitcnt lgkmcnt(0) 1541; VI-NEXT: v_mov_b32_e32 v0, s13 1542; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 2 1543; VI-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5] 1544; VI-NEXT: v_mov_b32_e32 v0, s12 1545; VI-NEXT: v_cndmask_b32_e64 v4, v0, 5, s[4:5] 1546; VI-NEXT: v_mov_b32_e32 v0, s11 1547; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 1 1548; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] 1549; VI-NEXT: v_mov_b32_e32 v0, s10 1550; VI-NEXT: v_cndmask_b32_e64 v2, v0, 5, s[4:5] 1551; VI-NEXT: v_mov_b32_e32 v0, s9 1552; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], s6, 0 1553; VI-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[4:5] 1554; VI-NEXT: v_mov_b32_e32 v0, s8 1555; VI-NEXT: v_cndmask_b32_e64 v0, v0, 5, s[4:5] 1556; VI-NEXT: buffer_store_dwordx2 v[4:5], off, s[0:3], 0 offset:16 1557; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 1558; VI-NEXT: s_endpgm 1559 %vecins = insertelement <3 x i64> %a, i64 5, i32 %b 1560 store <3 x i64> %vecins, <3 x i64> addrspace(1)* %out, align 32 1561 ret void 1562} 1563 1564define amdgpu_kernel void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind { 1565; SI-LABEL: dynamic_insertelement_v4f64: 1566; SI: ; %bb.0: 1567; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1568; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x8 1569; SI-NEXT: s_load_dword s4, s[4:5], 0x10 1570; SI-NEXT: v_mov_b32_e32 v4, 0x40200000 1571; SI-NEXT: s_mov_b32 s3, 0x100f000 1572; SI-NEXT: s_mov_b32 s2, -1 1573; SI-NEXT: s_waitcnt lgkmcnt(0) 1574; SI-NEXT: v_mov_b32_e32 v0, s11 1575; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1 1576; SI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc 1577; SI-NEXT: v_mov_b32_e32 v0, s10 1578; SI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc 1579; SI-NEXT: v_mov_b32_e32 v0, s9 1580; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0 1581; SI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc 1582; SI-NEXT: v_mov_b32_e32 v0, s8 1583; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 1584; SI-NEXT: v_mov_b32_e32 v5, s15 1585; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 3 1586; SI-NEXT: v_cndmask_b32_e32 v7, v5, v4, vcc 1587; SI-NEXT: v_mov_b32_e32 v5, s14 1588; SI-NEXT: v_cndmask_b32_e64 v6, v5, 0, vcc 1589; SI-NEXT: v_mov_b32_e32 v5, s13 1590; SI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 2 1591; SI-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc 1592; SI-NEXT: v_mov_b32_e32 v4, s12 1593; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc 1594; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 1595; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 1596; SI-NEXT: s_endpgm 1597; 1598; VI-LABEL: dynamic_insertelement_v4f64: 1599; VI: ; %bb.0: 1600; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1601; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x20 1602; VI-NEXT: s_load_dword s4, s[4:5], 0x40 1603; VI-NEXT: v_mov_b32_e32 v4, 0x40200000 1604; VI-NEXT: s_mov_b32 s3, 0x1100f000 1605; VI-NEXT: s_mov_b32 s2, -1 1606; VI-NEXT: s_waitcnt lgkmcnt(0) 1607; VI-NEXT: v_mov_b32_e32 v0, s11 1608; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 1 1609; VI-NEXT: v_cndmask_b32_e32 v3, v0, v4, vcc 1610; VI-NEXT: v_mov_b32_e32 v0, s10 1611; VI-NEXT: v_cndmask_b32_e64 v2, v0, 0, vcc 1612; VI-NEXT: v_mov_b32_e32 v0, s9 1613; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 0 1614; VI-NEXT: v_cndmask_b32_e32 v1, v0, v4, vcc 1615; VI-NEXT: v_mov_b32_e32 v0, s8 1616; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc 1617; VI-NEXT: v_mov_b32_e32 v5, s15 1618; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 3 1619; VI-NEXT: v_cndmask_b32_e32 v7, v5, v4, vcc 1620; VI-NEXT: v_mov_b32_e32 v5, s14 1621; VI-NEXT: v_cndmask_b32_e64 v6, v5, 0, vcc 1622; VI-NEXT: v_mov_b32_e32 v5, s13 1623; VI-NEXT: v_cmp_eq_u32_e64 vcc, s4, 2 1624; VI-NEXT: v_cndmask_b32_e32 v5, v5, v4, vcc 1625; VI-NEXT: v_mov_b32_e32 v4, s12 1626; VI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc 1627; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 1628; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 1629; VI-NEXT: s_endpgm 1630 %vecins = insertelement <4 x double> %a, double 8.0, i32 %b 1631 store <4 x double> %vecins, <4 x double> addrspace(1)* %out, align 16 1632 ret void 1633} 1634 1635define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) #0 { 1636; SI-LABEL: dynamic_insertelement_v8f64: 1637; SI: ; %bb.0: 1638; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1639; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x10 1640; SI-NEXT: s_load_dword s4, s[4:5], 0x20 1641; SI-NEXT: v_mov_b32_e32 v16, 0x40200000 1642; SI-NEXT: s_mov_b32 s3, 0x100f000 1643; SI-NEXT: s_mov_b32 s2, -1 1644; SI-NEXT: s_waitcnt lgkmcnt(0) 1645; SI-NEXT: v_mov_b32_e32 v0, s8 1646; SI-NEXT: s_lshl_b32 s4, s4, 1 1647; SI-NEXT: v_mov_b32_e32 v1, s9 1648; SI-NEXT: v_mov_b32_e32 v2, s10 1649; SI-NEXT: v_mov_b32_e32 v3, s11 1650; SI-NEXT: v_mov_b32_e32 v4, s12 1651; SI-NEXT: v_mov_b32_e32 v5, s13 1652; SI-NEXT: v_mov_b32_e32 v6, s14 1653; SI-NEXT: v_mov_b32_e32 v7, s15 1654; SI-NEXT: v_mov_b32_e32 v8, s16 1655; SI-NEXT: v_mov_b32_e32 v9, s17 1656; SI-NEXT: v_mov_b32_e32 v10, s18 1657; SI-NEXT: v_mov_b32_e32 v11, s19 1658; SI-NEXT: v_mov_b32_e32 v12, s20 1659; SI-NEXT: v_mov_b32_e32 v13, s21 1660; SI-NEXT: v_mov_b32_e32 v14, s22 1661; SI-NEXT: v_mov_b32_e32 v15, s23 1662; SI-NEXT: s_mov_b32 m0, s4 1663; SI-NEXT: v_movreld_b32_e32 v0, 0 1664; SI-NEXT: v_movreld_b32_e32 v1, v16 1665; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48 1666; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32 1667; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 1668; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 1669; SI-NEXT: s_endpgm 1670; 1671; VI-LABEL: dynamic_insertelement_v8f64: 1672; VI: ; %bb.0: 1673; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 1674; VI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x40 1675; VI-NEXT: s_load_dword s4, s[4:5], 0x80 1676; VI-NEXT: v_mov_b32_e32 v16, 0x40200000 1677; VI-NEXT: s_mov_b32 s3, 0x1100f000 1678; VI-NEXT: s_mov_b32 s2, -1 1679; VI-NEXT: s_waitcnt lgkmcnt(0) 1680; VI-NEXT: v_mov_b32_e32 v0, s8 1681; VI-NEXT: s_lshl_b32 s4, s4, 1 1682; VI-NEXT: v_mov_b32_e32 v1, s9 1683; VI-NEXT: v_mov_b32_e32 v2, s10 1684; VI-NEXT: v_mov_b32_e32 v3, s11 1685; VI-NEXT: v_mov_b32_e32 v4, s12 1686; VI-NEXT: v_mov_b32_e32 v5, s13 1687; VI-NEXT: v_mov_b32_e32 v6, s14 1688; VI-NEXT: v_mov_b32_e32 v7, s15 1689; VI-NEXT: v_mov_b32_e32 v8, s16 1690; VI-NEXT: v_mov_b32_e32 v9, s17 1691; VI-NEXT: v_mov_b32_e32 v10, s18 1692; VI-NEXT: v_mov_b32_e32 v11, s19 1693; VI-NEXT: v_mov_b32_e32 v12, s20 1694; VI-NEXT: v_mov_b32_e32 v13, s21 1695; VI-NEXT: v_mov_b32_e32 v14, s22 1696; VI-NEXT: v_mov_b32_e32 v15, s23 1697; VI-NEXT: s_mov_b32 m0, s4 1698; VI-NEXT: v_movreld_b32_e32 v0, 0 1699; VI-NEXT: v_movreld_b32_e32 v1, v16 1700; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48 1701; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32 1702; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16 1703; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 1704; VI-NEXT: s_endpgm 1705 %vecins = insertelement <8 x double> %a, double 8.0, i32 %b 1706 store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16 1707 ret void 1708} 1709 1710declare <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1 1711 1712attributes #0 = { nounwind } 1713attributes #1 = { nounwind readnone } 1714