1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 3; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=IR %s 4; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 5 6; After structurizing, there are 3 levels of loops. The i1 phi 7; conditions mutually depend on each other, so it isn't safe to delete 8; the condition that appears to have no uses until the loop is 9; completely processed. 10 11define amdgpu_kernel void @reduced_nested_loop_conditions(i64 addrspace(3)* nocapture %arg) #0 { 12; GCN-LABEL: reduced_nested_loop_conditions: 13; GCN: ; %bb.0: ; %bb 14; GCN-NEXT: s_load_dword s0, s[0:1], 0x9 15; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0 16; GCN-NEXT: s_mov_b32 m0, -1 17; GCN-NEXT: s_mov_b64 s[2:3], -1 18; GCN-NEXT: s_waitcnt lgkmcnt(0) 19; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0 20; GCN-NEXT: ds_read_b64 v[0:1], v0 21; GCN-NEXT: s_and_b64 s[0:1], exec, -1 22; GCN-NEXT: s_branch BB0_2 23; GCN-NEXT: BB0_1: ; %bb10 24; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1 25; GCN-NEXT: s_mov_b64 s[4:5], 0 26; GCN-NEXT: s_andn2_b64 vcc, exec, s[2:3] 27; GCN-NEXT: s_cbranch_vccz BB0_4 28; GCN-NEXT: BB0_2: ; %bb5 29; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 30; GCN-NEXT: s_mov_b64 vcc, s[0:1] 31; GCN-NEXT: s_cbranch_vccnz BB0_1 32; GCN-NEXT: ; %bb.3: ; in Loop: Header=BB0_2 Depth=1 33; GCN-NEXT: s_mov_b64 s[4:5], -1 34; GCN-NEXT: s_andn2_b64 vcc, exec, s[2:3] 35; GCN-NEXT: s_cbranch_vccnz BB0_2 36; GCN-NEXT: BB0_4: ; %loop.exit.guard 37; GCN-NEXT: s_and_b64 vcc, exec, s[4:5] 38; GCN-NEXT: s_cbranch_vccz BB0_7 39; GCN-NEXT: ; %bb.5: ; %bb8 40; GCN-NEXT: s_waitcnt lgkmcnt(0) 41; GCN-NEXT: ds_read_b32 v0, v0 42; GCN-NEXT: s_and_b64 vcc, exec, 0 43; GCN-NEXT: BB0_6: ; %bb9 44; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 45; GCN-NEXT: s_mov_b64 vcc, vcc 46; GCN-NEXT: s_cbranch_vccz BB0_6 47; GCN-NEXT: BB0_7: ; %DummyReturnBlock 48; GCN-NEXT: s_endpgm 49; IR-LABEL: @reduced_nested_loop_conditions( 50; IR-NEXT: bb: 51; IR-NEXT: [[MY_TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() #4 52; IR-NEXT: [[MY_TMP1:%.*]] = getelementptr inbounds i64, i64 addrspace(3)* [[ARG:%.*]], i32 [[MY_TMP]] 53; IR-NEXT: [[MY_TMP2:%.*]] = load volatile i64, i64 addrspace(3)* [[MY_TMP1]] 54; IR-NEXT: br label [[BB5:%.*]] 55; IR: bb3: 56; IR-NEXT: br i1 true, label [[BB4:%.*]], label [[BB13:%.*]] 57; IR: bb4: 58; IR-NEXT: br label [[FLOW:%.*]] 59; IR: bb5: 60; IR-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP6:%.*]], [[BB10:%.*]] ], [ 0, [[BB:%.*]] ] 61; IR-NEXT: [[MY_TMP6:%.*]] = phi i32 [ 0, [[BB]] ], [ [[TMP5:%.*]], [[BB10]] ] 62; IR-NEXT: [[MY_TMP7:%.*]] = icmp eq i32 [[MY_TMP6]], 1 63; IR-NEXT: [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[MY_TMP7]]) 64; IR-NEXT: [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0 65; IR-NEXT: [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP0]], 1 66; IR-NEXT: br i1 [[TMP1]], label [[BB8:%.*]], label [[FLOW]] 67; IR: bb8: 68; IR-NEXT: br label [[BB13]] 69; IR: bb9: 70; IR-NEXT: br i1 false, label [[BB3:%.*]], label [[BB9:%.*]] 71; IR: bb10: 72; IR-NEXT: [[TMP3:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP6]]) 73; IR-NEXT: br i1 [[TMP3]], label [[BB23:%.*]], label [[BB5]] 74; IR: Flow: 75; IR-NEXT: [[TMP4:%.*]] = phi i1 [ [[MY_TMP22:%.*]], [[BB4]] ], [ true, [[BB5]] ] 76; IR-NEXT: [[TMP5]] = phi i32 [ [[MY_TMP21:%.*]], [[BB4]] ], [ undef, [[BB5]] ] 77; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]]) 78; IR-NEXT: [[TMP6]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP4]], i64 [[PHI_BROKEN]]) 79; IR-NEXT: br label [[BB10]] 80; IR: bb13: 81; IR-NEXT: [[MY_TMP14:%.*]] = phi i1 [ [[MY_TMP22]], [[BB3]] ], [ true, [[BB8]] ] 82; IR-NEXT: [[MY_TMP15:%.*]] = bitcast i64 [[MY_TMP2]] to <2 x i32> 83; IR-NEXT: br i1 [[MY_TMP14]], label [[BB16:%.*]], label [[BB20:%.*]] 84; IR: bb16: 85; IR-NEXT: [[MY_TMP17:%.*]] = extractelement <2 x i32> [[MY_TMP15]], i64 1 86; IR-NEXT: [[MY_TMP18:%.*]] = getelementptr inbounds i32, i32 addrspace(3)* undef, i32 [[MY_TMP17]] 87; IR-NEXT: [[MY_TMP19:%.*]] = load volatile i32, i32 addrspace(3)* [[MY_TMP18]] 88; IR-NEXT: br label [[BB20]] 89; IR: bb20: 90; IR-NEXT: [[MY_TMP21]] = phi i32 [ [[MY_TMP19]], [[BB16]] ], [ 0, [[BB13]] ] 91; IR-NEXT: [[MY_TMP22]] = phi i1 [ false, [[BB16]] ], [ [[MY_TMP14]], [[BB13]] ] 92; IR-NEXT: br label [[BB9]] 93; IR: bb23: 94; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP6]]) 95; IR-NEXT: ret void 96bb: 97 %my.tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #1 98 %my.tmp1 = getelementptr inbounds i64, i64 addrspace(3)* %arg, i32 %my.tmp 99 %my.tmp2 = load volatile i64, i64 addrspace(3)* %my.tmp1 100 br label %bb5 101 102bb3: ; preds = %bb9 103 br i1 true, label %bb4, label %bb13 104 105bb4: ; preds = %bb3 106 br label %bb10 107 108bb5: ; preds = %bb10, %bb 109 %my.tmp6 = phi i32 [ 0, %bb ], [ %my.tmp11, %bb10 ] 110 %my.tmp7 = icmp eq i32 %my.tmp6, 1 111 br i1 %my.tmp7, label %bb8, label %bb10 112 113bb8: ; preds = %bb5 114 br label %bb13 115 116bb9: ; preds = %bb20, %bb9 117 br i1 false, label %bb3, label %bb9 118 119bb10: ; preds = %bb5, %bb4 120 %my.tmp11 = phi i32 [ %my.tmp21, %bb4 ], [ undef, %bb5 ] 121 %my.tmp12 = phi i1 [ %my.tmp22, %bb4 ], [ true, %bb5 ] 122 br i1 %my.tmp12, label %bb23, label %bb5 123 124bb13: ; preds = %bb8, %bb3 125 %my.tmp14 = phi i1 [ %my.tmp22, %bb3 ], [ true, %bb8 ] 126 %my.tmp15 = bitcast i64 %my.tmp2 to <2 x i32> 127 br i1 %my.tmp14, label %bb16, label %bb20 128 129bb16: ; preds = %bb13 130 %my.tmp17 = extractelement <2 x i32> %my.tmp15, i64 1 131 %my.tmp18 = getelementptr inbounds i32, i32 addrspace(3)* undef, i32 %my.tmp17 132 %my.tmp19 = load volatile i32, i32 addrspace(3)* %my.tmp18 133 br label %bb20 134 135bb20: ; preds = %bb16, %bb13 136 %my.tmp21 = phi i32 [ %my.tmp19, %bb16 ], [ 0, %bb13 ] 137 %my.tmp22 = phi i1 [ false, %bb16 ], [ %my.tmp14, %bb13 ] 138 br label %bb9 139 140bb23: ; preds = %bb10 141 ret void 142} 143 144; Earlier version of above, before a run of the structurizer. 145 146define amdgpu_kernel void @nested_loop_conditions(i64 addrspace(1)* nocapture %arg) #0 { 147; GCN-LABEL: nested_loop_conditions: 148; GCN: ; %bb.0: ; %bb 149; GCN-NEXT: s_mov_b32 s3, 0xf000 150; GCN-NEXT: s_mov_b32 s2, -1 151; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0 152; GCN-NEXT: s_waitcnt vmcnt(0) 153; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 8, v0 154; GCN-NEXT: s_and_b64 vcc, exec, vcc 155; GCN-NEXT: s_cbranch_vccnz BB1_6 156; GCN-NEXT: ; %bb.1: ; %bb14.lr.ph 157; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0 158; GCN-NEXT: s_branch BB1_3 159; GCN-NEXT: BB1_2: ; in Loop: Header=BB1_3 Depth=1 160; GCN-NEXT: s_mov_b64 s[0:1], -1 161; GCN-NEXT: ; implicit-def: $vgpr0 162; GCN-NEXT: s_cbranch_execnz BB1_6 163; GCN-NEXT: BB1_3: ; %bb14 164; GCN-NEXT: ; =>This Loop Header: Depth=1 165; GCN-NEXT: ; Child Loop BB1_4 Depth 2 166; GCN-NEXT: s_waitcnt vmcnt(0) 167; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 1, v0 168; GCN-NEXT: s_and_b64 vcc, exec, vcc 169; GCN-NEXT: s_cbranch_vccnz BB1_2 170; GCN-NEXT: BB1_4: ; %bb18 171; GCN-NEXT: ; Parent Loop BB1_3 Depth=1 172; GCN-NEXT: ; => This Inner Loop Header: Depth=2 173; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0 174; GCN-NEXT: s_waitcnt vmcnt(0) 175; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 8, v0 176; GCN-NEXT: s_and_b64 vcc, exec, vcc 177; GCN-NEXT: s_cbranch_vccnz BB1_4 178; GCN-NEXT: ; %bb.5: ; %bb21 179; GCN-NEXT: ; in Loop: Header=BB1_3 Depth=1 180; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0 181; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 182; GCN-NEXT: s_waitcnt vmcnt(0) 183; GCN-NEXT: v_cmp_lt_i32_e64 s[0:1], 8, v1 184; GCN-NEXT: s_and_b64 vcc, exec, s[0:1] 185; GCN-NEXT: s_cbranch_vccz BB1_3 186; GCN-NEXT: BB1_6: ; %bb31 187; GCN-NEXT: v_mov_b32_e32 v0, 0 188; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 189; GCN-NEXT: s_waitcnt vmcnt(0) 190; GCN-NEXT: s_endpgm 191; IR-LABEL: @nested_loop_conditions( 192; IR-NEXT: bb: 193; IR-NEXT: [[MY_TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() #4 194; IR-NEXT: [[MY_TMP1:%.*]] = zext i32 [[MY_TMP]] to i64 195; IR-NEXT: [[MY_TMP2:%.*]] = getelementptr inbounds i64, i64 addrspace(1)* [[ARG:%.*]], i64 [[MY_TMP1]] 196; IR-NEXT: [[MY_TMP3:%.*]] = load i64, i64 addrspace(1)* [[MY_TMP2]], align 16 197; IR-NEXT: [[MY_TMP932:%.*]] = load <4 x i32>, <4 x i32> addrspace(1)* undef, align 16 198; IR-NEXT: [[MY_TMP1033:%.*]] = extractelement <4 x i32> [[MY_TMP932]], i64 0 199; IR-NEXT: [[MY_TMP1134:%.*]] = load volatile i32, i32 addrspace(1)* undef 200; IR-NEXT: [[MY_TMP1235:%.*]] = icmp slt i32 [[MY_TMP1134]], 9 201; IR-NEXT: br i1 [[MY_TMP1235]], label [[BB14_LR_PH:%.*]], label [[FLOW:%.*]] 202; IR: bb14.lr.ph: 203; IR-NEXT: br label [[BB14:%.*]] 204; IR: Flow3: 205; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP21:%.*]]) 206; IR-NEXT: [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP14:%.*]]) 207; IR-NEXT: [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0 208; IR-NEXT: [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP0]], 1 209; IR-NEXT: br i1 [[TMP1]], label [[BB4_BB13_CRIT_EDGE:%.*]], label [[FLOW4:%.*]] 210; IR: bb4.bb13_crit_edge: 211; IR-NEXT: br label [[FLOW4]] 212; IR: Flow4: 213; IR-NEXT: [[TMP3:%.*]] = phi i1 [ true, [[BB4_BB13_CRIT_EDGE]] ], [ false, [[FLOW3:%.*]] ] 214; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]]) 215; IR-NEXT: br label [[FLOW]] 216; IR: bb13: 217; IR-NEXT: br label [[BB31:%.*]] 218; IR: Flow: 219; IR-NEXT: [[TMP4:%.*]] = phi i1 [ [[TMP3]], [[FLOW4]] ], [ true, [[BB:%.*]] ] 220; IR-NEXT: [[TMP5:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP4]]) 221; IR-NEXT: [[TMP6:%.*]] = extractvalue { i1, i64 } [[TMP5]], 0 222; IR-NEXT: [[TMP7:%.*]] = extractvalue { i1, i64 } [[TMP5]], 1 223; IR-NEXT: br i1 [[TMP6]], label [[BB13:%.*]], label [[BB31]] 224; IR: bb14: 225; IR-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP16:%.*]], [[FLOW1:%.*]] ], [ 0, [[BB14_LR_PH]] ] 226; IR-NEXT: [[MY_TMP1037:%.*]] = phi i32 [ [[MY_TMP1033]], [[BB14_LR_PH]] ], [ [[TMP12:%.*]], [[FLOW1]] ] 227; IR-NEXT: [[MY_TMP936:%.*]] = phi <4 x i32> [ [[MY_TMP932]], [[BB14_LR_PH]] ], [ [[TMP11:%.*]], [[FLOW1]] ] 228; IR-NEXT: [[MY_TMP15:%.*]] = icmp eq i32 [[MY_TMP1037]], 1 229; IR-NEXT: [[TMP8:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[MY_TMP15]]) 230; IR-NEXT: [[TMP9:%.*]] = extractvalue { i1, i64 } [[TMP8]], 0 231; IR-NEXT: [[TMP10:%.*]] = extractvalue { i1, i64 } [[TMP8]], 1 232; IR-NEXT: br i1 [[TMP9]], label [[BB16:%.*]], label [[FLOW1]] 233; IR: bb16: 234; IR-NEXT: [[MY_TMP17:%.*]] = bitcast i64 [[MY_TMP3]] to <2 x i32> 235; IR-NEXT: br label [[BB18:%.*]] 236; IR: Flow1: 237; IR-NEXT: [[TMP11]] = phi <4 x i32> [ [[MY_TMP9:%.*]], [[BB21:%.*]] ], [ undef, [[BB14]] ] 238; IR-NEXT: [[TMP12]] = phi i32 [ [[MY_TMP10:%.*]], [[BB21]] ], [ undef, [[BB14]] ] 239; IR-NEXT: [[TMP13:%.*]] = phi i1 [ [[TMP18:%.*]], [[BB21]] ], [ true, [[BB14]] ] 240; IR-NEXT: [[TMP14]] = phi i1 [ [[TMP18]], [[BB21]] ], [ false, [[BB14]] ] 241; IR-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[BB21]] ], [ true, [[BB14]] ] 242; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP10]]) 243; IR-NEXT: [[TMP16]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP13]], i64 [[PHI_BROKEN]]) 244; IR-NEXT: [[TMP17:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP16]]) 245; IR-NEXT: br i1 [[TMP17]], label [[FLOW2:%.*]], label [[BB14]] 246; IR: bb18: 247; IR-NEXT: [[MY_TMP19:%.*]] = load volatile i32, i32 addrspace(1)* undef 248; IR-NEXT: [[MY_TMP20:%.*]] = icmp slt i32 [[MY_TMP19]], 9 249; IR-NEXT: br i1 [[MY_TMP20]], label [[BB21]], label [[BB18]] 250; IR: bb21: 251; IR-NEXT: [[MY_TMP22:%.*]] = extractelement <2 x i32> [[MY_TMP17]], i64 1 252; IR-NEXT: [[MY_TMP23:%.*]] = lshr i32 [[MY_TMP22]], 16 253; IR-NEXT: [[MY_TMP24:%.*]] = select i1 undef, i32 undef, i32 [[MY_TMP23]] 254; IR-NEXT: [[MY_TMP25:%.*]] = uitofp i32 [[MY_TMP24]] to float 255; IR-NEXT: [[MY_TMP26:%.*]] = fmul float [[MY_TMP25]], 0x3EF0001000000000 256; IR-NEXT: [[MY_TMP27:%.*]] = fsub float [[MY_TMP26]], undef 257; IR-NEXT: [[MY_TMP28:%.*]] = fcmp olt float [[MY_TMP27]], 5.000000e-01 258; IR-NEXT: [[MY_TMP29:%.*]] = select i1 [[MY_TMP28]], i64 1, i64 2 259; IR-NEXT: [[MY_TMP30:%.*]] = extractelement <4 x i32> [[MY_TMP936]], i64 [[MY_TMP29]] 260; IR-NEXT: [[MY_TMP7:%.*]] = zext i32 [[MY_TMP30]] to i64 261; IR-NEXT: [[MY_TMP8:%.*]] = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* undef, i64 [[MY_TMP7]] 262; IR-NEXT: [[MY_TMP9]] = load <4 x i32>, <4 x i32> addrspace(1)* [[MY_TMP8]], align 16 263; IR-NEXT: [[MY_TMP10]] = extractelement <4 x i32> [[MY_TMP9]], i64 0 264; IR-NEXT: [[MY_TMP11:%.*]] = load volatile i32, i32 addrspace(1)* undef 265; IR-NEXT: [[MY_TMP12:%.*]] = icmp slt i32 [[MY_TMP11]], 9 266; IR-NEXT: [[TMP18]] = xor i1 [[MY_TMP12]], true 267; IR-NEXT: br label [[FLOW1]] 268; IR: Flow2: 269; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP16]]) 270; IR-NEXT: [[TMP19:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP15]]) 271; IR-NEXT: [[TMP20:%.*]] = extractvalue { i1, i64 } [[TMP19]], 0 272; IR-NEXT: [[TMP21]] = extractvalue { i1, i64 } [[TMP19]], 1 273; IR-NEXT: br i1 [[TMP20]], label [[BB31_LOOPEXIT:%.*]], label [[FLOW3]] 274; IR: bb31.loopexit: 275; IR-NEXT: br label [[FLOW3]] 276; IR: bb31: 277; IR-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP7]]) 278; IR-NEXT: store volatile i32 0, i32 addrspace(1)* undef 279; IR-NEXT: ret void 280bb: 281 %my.tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #1 282 %my.tmp1 = zext i32 %my.tmp to i64 283 %my.tmp2 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 %my.tmp1 284 %my.tmp3 = load i64, i64 addrspace(1)* %my.tmp2, align 16 285 %my.tmp932 = load <4 x i32>, <4 x i32> addrspace(1)* undef, align 16 286 %my.tmp1033 = extractelement <4 x i32> %my.tmp932, i64 0 287 %my.tmp1134 = load volatile i32, i32 addrspace(1)* undef 288 %my.tmp1235 = icmp slt i32 %my.tmp1134, 9 289 br i1 %my.tmp1235, label %bb14.lr.ph, label %bb13 290 291bb14.lr.ph: ; preds = %bb 292 br label %bb14 293 294bb4.bb13_crit_edge: ; preds = %bb21 295 br label %bb13 296 297bb13: ; preds = %bb4.bb13_crit_edge, %bb 298 br label %bb31 299 300bb14: ; preds = %bb21, %bb14.lr.ph 301 %my.tmp1037 = phi i32 [ %my.tmp1033, %bb14.lr.ph ], [ %my.tmp10, %bb21 ] 302 %my.tmp936 = phi <4 x i32> [ %my.tmp932, %bb14.lr.ph ], [ %my.tmp9, %bb21 ] 303 %my.tmp15 = icmp eq i32 %my.tmp1037, 1 304 br i1 %my.tmp15, label %bb16, label %bb31.loopexit 305 306bb16: ; preds = %bb14 307 %my.tmp17 = bitcast i64 %my.tmp3 to <2 x i32> 308 br label %bb18 309 310bb18: ; preds = %bb18, %bb16 311 %my.tmp19 = load volatile i32, i32 addrspace(1)* undef 312 %my.tmp20 = icmp slt i32 %my.tmp19, 9 313 br i1 %my.tmp20, label %bb21, label %bb18 314 315bb21: ; preds = %bb18 316 %my.tmp22 = extractelement <2 x i32> %my.tmp17, i64 1 317 %my.tmp23 = lshr i32 %my.tmp22, 16 318 %my.tmp24 = select i1 undef, i32 undef, i32 %my.tmp23 319 %my.tmp25 = uitofp i32 %my.tmp24 to float 320 %my.tmp26 = fmul float %my.tmp25, 0x3EF0001000000000 321 %my.tmp27 = fsub float %my.tmp26, undef 322 %my.tmp28 = fcmp olt float %my.tmp27, 5.000000e-01 323 %my.tmp29 = select i1 %my.tmp28, i64 1, i64 2 324 %my.tmp30 = extractelement <4 x i32> %my.tmp936, i64 %my.tmp29 325 %my.tmp7 = zext i32 %my.tmp30 to i64 326 %my.tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* undef, i64 %my.tmp7 327 %my.tmp9 = load <4 x i32>, <4 x i32> addrspace(1)* %my.tmp8, align 16 328 %my.tmp10 = extractelement <4 x i32> %my.tmp9, i64 0 329 %my.tmp11 = load volatile i32, i32 addrspace(1)* undef 330 %my.tmp12 = icmp slt i32 %my.tmp11, 9 331 br i1 %my.tmp12, label %bb14, label %bb4.bb13_crit_edge 332 333bb31.loopexit: ; preds = %bb14 334 br label %bb31 335 336bb31: ; preds = %bb31.loopexit, %bb13 337 store volatile i32 0, i32 addrspace(1)* undef 338 ret void 339} 340 341declare i32 @llvm.amdgcn.workitem.id.x() #1 342 343attributes #0 = { nounwind } 344attributes #1 = { nounwind readnone } 345