1// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+WavefrontSize32,-WavefrontSize64 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace 2 3//============================================================================== 4// destination must be different than all sources 5 6v_mqsad_pk_u16_u8 v[0:1], v[1:2], v9, v[4:5] 7// CHECK: error: destination must be different than all sources 8// CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[1:2], v9, v[4:5] 9// CHECK-NEXT:{{^}} ^ 10 11v_mqsad_pk_u16_u8 v[0:1], v[2:3], v0, v[4:5] 12// CHECK: error: destination must be different than all sources 13// CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[2:3], v0, v[4:5] 14// CHECK-NEXT:{{^}} ^ 15 16v_mqsad_pk_u16_u8 v[0:1], v[2:3], v1, v[4:5] 17// CHECK: error: destination must be different than all sources 18// CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[2:3], v1, v[4:5] 19// CHECK-NEXT:{{^}} ^ 20 21v_mqsad_pk_u16_u8 v[0:1], v[2:3], v9, v[0:1] 22// CHECK: error: destination must be different than all sources 23// CHECK-NEXT:{{^}}v_mqsad_pk_u16_u8 v[0:1], v[2:3], v9, v[0:1] 24// CHECK-NEXT:{{^}} ^ 25 26//============================================================================== 27// dim modifier is required on this GPU 28 29image_atomic_add v252, v2, s[8:15] 30// CHECK: error: dim modifier is required on this GPU 31// CHECK-NEXT:{{^}}image_atomic_add v252, v2, s[8:15] 32// CHECK-NEXT:{{^}}^ 33 34//============================================================================== 35// duplicate data format 36 37tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8] 38// CHECK: error: duplicate data format 39// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8] 40// CHECK-NEXT:{{^}} ^ 41 42//============================================================================== 43// duplicate numeric format 44 45tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT,BUF_NUM_FORMAT_FLOAT] 46// CHECK: error: duplicate numeric format 47// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT,BUF_NUM_FORMAT_FLOAT] 48// CHECK-NEXT:{{^}} ^ 49 50//============================================================================== 51// expected ')' in parentheses expression 52 53v_bfe_u32 v0, 1+(100, v1, v2 54// CHECK: error: expected ')' in parentheses expression 55// CHECK-NEXT:{{^}}v_bfe_u32 v0, 1+(100, v1, v2 56// CHECK-NEXT:{{^}} ^ 57 58//============================================================================== 59// expected a 12-bit signed offset 60 61global_load_dword v1, v[3:4] off, offset:-4097 62// CHECK: error: expected a 12-bit signed offset 63// CHECK-NEXT:{{^}}global_load_dword v1, v[3:4] off, offset:-4097 64// CHECK-NEXT:{{^}} ^ 65 66scratch_load_dword v0, v1, off offset:-2049 glc slc 67// CHECK: error: expected a 12-bit signed offset 68// CHECK-NEXT:{{^}}scratch_load_dword v0, v1, off offset:-2049 glc slc 69// CHECK-NEXT:{{^}} ^ 70 71//============================================================================== 72// expected a 16-bit signed jump offset 73 74s_branch 0x10000 75// CHECK: error: expected a 16-bit signed jump offset 76// CHECK-NEXT:{{^}}s_branch 0x10000 77// CHECK-NEXT:{{^}} ^ 78 79//============================================================================== 80// expected a 2-bit lane id 81 82ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3) 83// CHECK: error: expected a 2-bit lane id 84// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3) 85// CHECK-NEXT:{{^}} ^ 86 87//============================================================================== 88// expected a 20-bit unsigned offset 89 90s_atc_probe_buffer 0x1, s[8:11], -1 91// CHECK: error: expected a 20-bit unsigned offset 92// CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], -1 93// CHECK-NEXT:{{^}} ^ 94 95s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000 96// CHECK: error: expected a 20-bit unsigned offset 97// CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000 98// CHECK-NEXT:{{^}} ^ 99 100s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF 101// CHECK: error: expected a 20-bit unsigned offset 102// CHECK-NEXT:{{^}}s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF 103// CHECK-NEXT:{{^}} ^ 104 105//============================================================================== 106// expected a 21-bit signed offset 107 108s_atc_probe 0x7, s[4:5], 0x1FFFFF 109// CHECK: error: expected a 21-bit signed offset 110// CHECK-NEXT:{{^}}s_atc_probe 0x7, s[4:5], 0x1FFFFF 111// CHECK-NEXT:{{^}} ^ 112 113s_atomic_swap s5, s[2:3], 0x1FFFFF 114// CHECK: error: expected a 21-bit signed offset 115// CHECK-NEXT:{{^}}s_atomic_swap s5, s[2:3], 0x1FFFFF 116// CHECK-NEXT:{{^}} ^ 117 118//============================================================================== 119// expected a 2-bit value 120 121v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,4] row_mask:0x0 bank_mask:0x0 122// CHECK: error: expected a 2-bit value 123// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,4] row_mask:0x0 bank_mask:0x0 124// CHECK-NEXT:{{^}} ^ 125 126v_mov_b32_dpp v5, v1 quad_perm:[3,-1,1,3] row_mask:0x0 bank_mask:0x0 127// CHECK: error: expected a 2-bit value 128// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,-1,1,3] row_mask:0x0 bank_mask:0x0 129// CHECK-NEXT:{{^}} ^ 130 131//============================================================================== 132// expected a 3-bit value 133 134v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7] 135// CHECK: error: expected a 3-bit value 136// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7] 137// CHECK-NEXT:{{^}} ^ 138 139v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7] 140// CHECK: error: expected a 3-bit value 141// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7] 142// CHECK-NEXT:{{^}} ^ 143 144//============================================================================== 145// expected a 5-character mask 146 147ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii") 148// CHECK: error: expected a 5-character mask 149// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii") 150// CHECK-NEXT:{{^}} ^ 151 152//============================================================================== 153// expected a closing parentheses 154 155ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3 156// CHECK: error: expected a closing parentheses 157// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3 158// CHECK-NEXT:{{^}} ^ 159 160ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4) 161// CHECK: error: expected a closing parentheses 162// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4) 163// CHECK-NEXT:{{^}} ^ 164 165//============================================================================== 166// expected a closing parenthesis 167 168s_sendmsg sendmsg(2, 2, 0, 0) 169// CHECK: error: expected a closing parenthesis 170// CHECK-NEXT:{{^}}s_sendmsg sendmsg(2, 2, 0, 0) 171// CHECK-NEXT:{{^}} ^ 172 173s_waitcnt vmcnt(0 174// CHECK: error: expected a closing parenthesis 175// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0 176// CHECK-NEXT:{{^}} ^ 177 178//============================================================================== 179// expected a closing square bracket 180 181s_mov_b32 s1, s[0 1 182// CHECK: error: expected a closing square bracket 183// CHECK-NEXT:{{^}}s_mov_b32 s1, s[0 1 184// CHECK-NEXT:{{^}} ^ 185 186s_mov_b32 s1, s[0 s0 187// CHECK: error: expected a closing square bracket 188// CHECK-NEXT:{{^}}s_mov_b32 s1, s[0 s0 189// CHECK-NEXT:{{^}} ^ 190 191tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT,BUF_DATA_FORMAT_8] 192// CHECK: error: expected a closing square bracket 193// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT,BUF_DATA_FORMAT_8] 194// CHECK-NEXT:{{^}} ^ 195 196tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT 197// CHECK: error: expected a closing square bracket 198// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT 199// CHECK-NEXT:{{^}} ^ 200 201v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1 1 202// CHECK: error: expected a closing square bracket 203// CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1 1 204// CHECK-NEXT:{{^}} ^ 205 206v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1, 207// CHECK: error: expected a closing square bracket 208// CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1, 209// CHECK-NEXT:{{^}} ^ 210 211v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[ 212// CHECK: error: expected a closing square bracket 213// CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[ 214// CHECK-NEXT:{{^}} ^ 215 216v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0] 217// CHECK: error: expected a closing square bracket 218// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0] 219// CHECK-NEXT:{{^}} ^ 220 221v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7) 222// CHECK: error: expected a closing square bracket 223// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7) 224// CHECK-NEXT:{{^}} ^ 225 226v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0) row_mask:0x0 bank_mask:0x0 227// CHECK: error: expected a closing square bracket 228// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0) row_mask:0x0 bank_mask:0x0 229// CHECK-NEXT:{{^}} ^ 230 231//============================================================================== 232// expected a colon 233 234ds_swizzle_b32 v8, v2 offset 235// CHECK: error: expected a colon 236// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset 237// CHECK-NEXT:{{^}} ^ 238 239ds_swizzle_b32 v8, v2 offset- 240// CHECK: error: expected a colon 241// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset- 242// CHECK-NEXT:{{^}} ^ 243 244//============================================================================== 245// expected a comma 246 247ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM 248// CHECK: error: expected a comma 249// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM 250// CHECK-NEXT:{{^}} ^ 251 252ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2) 253// CHECK: error: expected a comma 254// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2) 255// CHECK-NEXT:{{^}} ^ 256 257s_setreg_b32 hwreg(1,2 3), s2 258// CHECK: error: expected a comma 259// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(1,2 3), s2 260// CHECK-NEXT:{{^}} ^ 261 262v_pk_add_u16 v1, v2, v3 op_sel:[0 0] 263// CHECK: error: expected a comma 264// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0 0] 265// CHECK-NEXT:{{^}} ^ 266 267v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6] 268// CHECK: error: expected a comma 269// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6] 270// CHECK-NEXT:{{^}} ^ 271 272v_mov_b32_dpp v5, v1 quad_perm:[3,2] row_mask:0x0 bank_mask:0x0 273// CHECK: error: expected a comma 274// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2] row_mask:0x0 bank_mask:0x0 275// CHECK-NEXT:{{^}} ^ 276 277//============================================================================== 278// expected a comma or a closing parenthesis 279 280s_setreg_b32 hwreg(1 2,3), s2 281// CHECK: error: expected a comma or a closing parenthesis 282// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(1 2,3), s2 283// CHECK-NEXT:{{^}} ^ 284 285//============================================================================== 286// expected a comma or a closing square bracket 287 288s_mov_b64 s[10:11], [s0 289// CHECK: error: expected a comma or a closing square bracket 290// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0 291// CHECK-NEXT:{{^}} ^ 292 293s_mov_b64 s[10:11], [s0,s1 294// CHECK: error: expected a comma or a closing square bracket 295// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s1 296// CHECK-NEXT:{{^}} ^ 297 298//============================================================================== 299// expected a counter name 300 301s_waitcnt vmcnt(0) & expcnt(0) & 1 302// CHECK: error: expected a counter name 303// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & 1 304// CHECK-NEXT:{{^}} ^ 305 306s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)& 307// CHECK: error: expected a counter name 308// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)& 309// CHECK-NEXT:{{^}} ^ 310 311s_waitcnt vmcnt(0) & expcnt(0) 1 312// CHECK: error: expected a counter name 313// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) 1 314// CHECK-NEXT:{{^}} ^ 315 316s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0), 317// CHECK: error: expected a counter name 318// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0), 319// CHECK-NEXT:{{^}} ^ 320 321//============================================================================== 322// expected a format string 323 324tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[] 325// CHECK: error: expected a format string 326// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[] 327// CHECK-NEXT:{{^}} ^ 328 329//============================================================================== 330// expected a left parenthesis 331 332s_waitcnt vmcnt(0) & expcnt(0) & x 333// CHECK: error: expected a left parenthesis 334// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & x 335// CHECK-NEXT:{{^}} ^ 336 337//============================================================================== 338// expected a left square bracket 339 340v_pk_add_u16 v1, v2, v3 op_sel: 341// CHECK: error: expected a left square bracket 342// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel: 343// CHECK-NEXT:{{^}} ^ 344 345//============================================================================== 346// expected a register or a list of registers 347 348s_mov_b32 s1, [s0, 1 349// CHECK: error: expected a register or a list of registers 350// CHECK-NEXT:{{^}}s_mov_b32 s1, [s0, 1 351// CHECK-NEXT:{{^}} ^ 352 353//============================================================================== 354// expected a single 32-bit register 355 356s_mov_b64 s[10:11], [s0,s[2:3]] 357// CHECK: error: expected a single 32-bit register 358// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s[2:3]] 359// CHECK-NEXT:{{^}} ^ 360 361//============================================================================== 362// expected a string 363 364ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii) 365// CHECK: error: expected a string 366// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii) 367// CHECK-NEXT:{{^}} ^ 368 369//============================================================================== 370// expected a swizzle mode 371 372ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1) 373// CHECK: error: expected a swizzle mode 374// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1) 375// CHECK-NEXT:{{^}} ^ 376 377//============================================================================== 378// expected absolute expression 379 380s_waitcnt vmcnt(x) 381// CHECK: error: expected absolute expression 382// CHECK-NEXT:{{^}}s_waitcnt vmcnt(x) 383// CHECK-NEXT:{{^}} ^ 384 385tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32] 386// CHECK: error: expected absolute expression 387// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32] 388// CHECK-NEXT:{{^}} ^ 389 390tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52 391// CHECK: error: expected absolute expression 392// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52 393// CHECK-NEXT:{{^}} ^ 394 395tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT] 396// CHECK: error: expected absolute expression 397// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT] 398// CHECK-NEXT:{{^}} ^ 399 400v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7] 401// CHECK: error: expected absolute expression 402// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7] 403// CHECK-NEXT:{{^}} ^ 404 405v_mov_b32_dpp v5, v1 quad_perm:[3,x,1,0] row_mask:0x0 bank_mask:0x0 406// CHECK: error: expected absolute expression 407// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,x,1,0] row_mask:0x0 bank_mask:0x0 408// CHECK-NEXT:{{^}} ^ 409 410v_mov_b32_dpp v5, v1 row_share:x row_mask:0x0 bank_mask:0x0 411// CHECK: error: expected absolute expression 412// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:x row_mask:0x0 bank_mask:0x0 413// CHECK-NEXT:{{^}} ^ 414 415//============================================================================== 416// expected a message name or an absolute expression 417 418s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0) 419// CHECK: error: expected a message name or an absolute expression 420// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0) 421// CHECK-NEXT:{{^}} ^ 422 423//============================================================================== 424// expected a register name or an absolute expression 425 426s_setreg_b32 hwreg(HW_REG_WRONG), s2 427// CHECK: error: expected a register name or an absolute expression 428// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(HW_REG_WRONG), s2 429// CHECK-NEXT:{{^}} ^ 430 431//============================================================================== 432// expected a sendmsg macro or an absolute expression 433 434s_sendmsg undef 435// CHECK: error: expected a sendmsg macro or an absolute expression 436// CHECK-NEXT:{{^}}s_sendmsg undef 437// CHECK-NEXT:{{^}} ^ 438 439//============================================================================== 440// expected a swizzle macro or an absolute expression 441 442ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3) 443// CHECK: error: expected a swizzle macro or an absolute expression 444// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3) 445// CHECK-NEXT:{{^}} ^ 446 447//============================================================================== 448// expected a hwreg macro or an absolute expression 449 450s_setreg_b32 undef, s2 451// CHECK: error: expected a hwreg macro or an absolute expression 452// CHECK-NEXT:{{^}}s_setreg_b32 undef, s2 453// CHECK-NEXT:{{^}} ^ 454 455//============================================================================== 456// expected an 11-bit unsigned offset 457 458flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc 459// CHECK: error: expected a 11-bit unsigned offset 460// CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc 461// CHECK-NEXT:{{^}} ^ 462 463//============================================================================== 464// expected an absolute expression 465 466v_ceil_f32 v1, abs(u) 467// CHECK: error: expected an absolute expression 468// CHECK-NEXT:{{^}}v_ceil_f32 v1, abs(u) 469// CHECK-NEXT:{{^}} ^ 470 471v_ceil_f32 v1, neg(u) 472// CHECK: error: expected an absolute expression 473// CHECK-NEXT:{{^}}v_ceil_f32 v1, neg(u) 474// CHECK-NEXT:{{^}} ^ 475 476v_ceil_f32 v1, |u| 477// CHECK: error: expected an absolute expression 478// CHECK-NEXT:{{^}}v_ceil_f32 v1, |u| 479// CHECK-NEXT:{{^}} ^ 480 481v_mov_b32_sdwa v1, sext(u) 482// CHECK: error: expected an absolute expression 483// CHECK-NEXT:{{^}}v_mov_b32_sdwa v1, sext(u) 484// CHECK-NEXT:{{^}} ^ 485 486//============================================================================== 487// expected an identifier 488 489v_mov_b32_sdwa v5, v1 dst_sel: 490// CHECK: error: expected an identifier 491// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel: 492// CHECK-NEXT:{{^}} ^ 493 494v_mov_b32_sdwa v5, v1 dst_sel:0 495// CHECK: error: expected an identifier 496// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:0 497// CHECK-NEXT:{{^}} ^ 498 499v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:[UNUSED_PAD] 500// CHECK: error: expected an identifier 501// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:[UNUSED_PAD] 502// CHECK-NEXT:{{^}} ^ 503 504//============================================================================== 505// expected an opening square bracket 506 507v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7) 508// CHECK: error: expected an opening square bracket 509// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7) 510// CHECK-NEXT:{{^}} ^ 511 512v_mov_b32_dpp v5, v1 quad_perm:(3,2,1,0) row_mask:0x0 bank_mask:0x0 513// CHECK: error: expected an opening square bracket 514// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:(3,2,1,0) row_mask:0x0 bank_mask:0x0 515// CHECK-NEXT:{{^}} ^ 516 517//============================================================================== 518// expected an operation name or an absolute expression 519 520s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0) 521// CHECK: error: expected an operation name or an absolute expression 522// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0) 523// CHECK-NEXT:{{^}} ^ 524 525//============================================================================== 526// failed parsing operand. 527 528image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D 529// CHECK: error: failed parsing operand. 530// CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D 531// CHECK-NEXT:{{^}} ^ 532 533v_ceil_f16 v0, abs(neg(1)) 534// CHECK: error: failed parsing operand. 535// CHECK-NEXT:{{^}}v_ceil_f16 v0, abs(neg(1)) 536// CHECK-NEXT:{{^}} ^ 537 538//============================================================================== 539// first register index should not exceed second index 540 541s_mov_b64 s[10:11], s[1:0] 542// CHECK: error: first register index should not exceed second index 543// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], s[1:0] 544// CHECK-NEXT:{{^}} ^ 545 546//============================================================================== 547// group size must be a power of two 548 549ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1) 550// CHECK: error: group size must be a power of two 551// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1) 552// CHECK-NEXT:{{^}} ^ 553 554ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3) 555// CHECK: error: group size must be a power of two 556// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3) 557// CHECK-NEXT:{{^}} ^ 558 559ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3) 560// CHECK: error: group size must be a power of two 561// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3) 562// CHECK-NEXT:{{^}} ^ 563 564//============================================================================== 565// group size must be in the interval [1,16] 566 567ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0) 568// CHECK: error: group size must be in the interval [1,16] 569// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0) 570// CHECK-NEXT:{{^}} ^ 571 572//============================================================================== 573// group size must be in the interval [2,32] 574 575ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0) 576// CHECK: error: group size must be in the interval [2,32] 577// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0) 578// CHECK-NEXT:{{^}} ^ 579 580//============================================================================== 581// image address size does not match dim and a16 582 583image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D 584// CHECK: error: image address size does not match dim and a16 585// CHECK-NEXT:{{^}}image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D 586// CHECK-NEXT:{{^}}^ 587 588//============================================================================== 589// image data size does not match dmask and tfe 590 591image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D 592// CHECK: error: image data size does not match dmask and tfe 593// CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D 594// CHECK-NEXT:{{^}}^ 595 596//============================================================================== 597// instruction must use glc 598 599flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047 600// CHECK: error: instruction must use glc 601// CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047 602// CHECK-NEXT:{{^}}^ 603 604//============================================================================== 605// instruction not supported on this GPU 606 607s_cbranch_join 1 608// CHECK: error: instruction not supported on this GPU 609// CHECK-NEXT:{{^}}s_cbranch_join 1 610// CHECK-NEXT:{{^}}^ 611 612//============================================================================== 613// invalid bit offset: only 5-bit values are legal 614 615s_getreg_b32 s2, hwreg(3,32,32) 616// CHECK: error: invalid bit offset: only 5-bit values are legal 617// CHECK-NEXT:{{^}}s_getreg_b32 s2, hwreg(3,32,32) 618// CHECK-NEXT:{{^}} ^ 619 620//============================================================================== 621// invalid bitfield width: only values from 1 to 32 are legal 622 623s_setreg_b32 hwreg(3,0,33), s2 624// CHECK: error: invalid bitfield width: only values from 1 to 32 are legal 625// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(3,0,33), s2 626// CHECK-NEXT:{{^}} ^ 627 628//============================================================================== 629// invalid code of hardware register: only 6-bit values are legal 630 631s_setreg_b32 hwreg(0x40), s2 632// CHECK: error: invalid code of hardware register: only 6-bit values are legal 633// CHECK-NEXT:{{^}}s_setreg_b32 hwreg(0x40), s2 634// CHECK-NEXT:{{^}} ^ 635 636//============================================================================== 637// invalid counter name x 638 639s_waitcnt vmcnt(0) & expcnt(0) x(0) 640// CHECK: error: invalid counter name x 641// CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) x(0) 642// CHECK-NEXT:{{^}} ^ 643 644//============================================================================== 645// invalid dst_sel value 646 647v_mov_b32_sdwa v5, v1 dst_sel:WORD 648// CHECK: error: invalid dst_sel value 649// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:WORD 650// CHECK-NEXT:{{^}} ^ 651 652//============================================================================== 653// invalid dst_unused value 654 655v_mov_b32_sdwa v5, v1 dst_unused:UNUSED 656// CHECK: error: invalid dst_unused value 657// CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_unused:UNUSED 658// CHECK-NEXT:{{^}} ^ 659 660//============================================================================== 661// invalid exp target 662 663exp invalid_target_10 v3, v2, v1, v0 664// CHECK: error: invalid exp target 665// CHECK-NEXT:{{^}}exp invalid_target_10 v3, v2, v1, v0 666// CHECK-NEXT:{{^}} ^ 667 668exp pos00 v3, v2, v1, v0 669// CHECK: error: invalid exp target 670// CHECK-NEXT:{{^}}exp pos00 v3, v2, v1, v0 671// CHECK-NEXT:{{^}} ^ 672 673//============================================================================== 674// invalid immediate: only 16-bit values are legal 675 676s_setreg_b32 0x1f803, s2 677// CHECK: error: invalid immediate: only 16-bit values are legal 678// CHECK-NEXT:{{^}}s_setreg_b32 0x1f803, s2 679// CHECK-NEXT:{{^}} ^ 680 681//============================================================================== 682// invalid instruction 683 684v_dot_f32_f16 v0, v1, v2 685// CHECK: error: invalid instruction 686// CHECK-NEXT:{{^}}v_dot_f32_f16 v0, v1, v2 687// CHECK-NEXT:{{^}}^ 688 689//============================================================================== 690// invalid interpolation attribute 691 692v_interp_p2_f32 v0, v1, att 693// CHECK: error: invalid interpolation attribute 694// CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, att 695// CHECK-NEXT:{{^}} ^ 696 697//============================================================================== 698// invalid interpolation slot 699 700v_interp_mov_f32 v8, p1, attr0.x 701// CHECK: error: invalid interpolation slot 702// CHECK-NEXT:{{^}}v_interp_mov_f32 v8, p1, attr0.x 703// CHECK-NEXT:{{^}} ^ 704 705//============================================================================== 706// invalid mask 707 708ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2") 709// CHECK: error: invalid mask 710// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2") 711// CHECK-NEXT:{{^}} ^ 712 713//============================================================================== 714// invalid message id 715 716s_sendmsg sendmsg(-1) 717// CHECK: error: invalid message id 718// CHECK-NEXT:{{^}}s_sendmsg sendmsg(-1) 719// CHECK-NEXT:{{^}} ^ 720 721//============================================================================== 722// invalid message stream id 723 724s_sendmsg sendmsg(2, 2, 4) 725// CHECK: error: invalid message stream id 726// CHECK-NEXT:{{^}}s_sendmsg sendmsg(2, 2, 4) 727// CHECK-NEXT:{{^}} ^ 728 729s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4) 730// CHECK: error: invalid message stream id 731// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4) 732// CHECK-NEXT:{{^}} ^ 733 734//============================================================================== 735// invalid mul value. 736 737v_cvt_f64_i32 v[5:6], s1 mul:3 738// CHECK: error: invalid mul value. 739// CHECK-NEXT:{{^}}v_cvt_f64_i32 v[5:6], s1 mul:3 740// CHECK-NEXT:{{^}} ^ 741 742//============================================================================== 743// invalid or missing interpolation attribute channel 744 745v_interp_p2_f32 v0, v1, attr0.q 746// CHECK: error: invalid or missing interpolation attribute channel 747// CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, attr0.q 748// CHECK-NEXT:{{^}} ^ 749 750//============================================================================== 751// invalid or missing interpolation attribute number 752 753v_interp_p2_f32 v7, v1, attr.x 754// CHECK: error: invalid or missing interpolation attribute number 755// CHECK-NEXT:{{^}}v_interp_p2_f32 v7, v1, attr.x 756// CHECK-NEXT:{{^}} ^ 757 758//============================================================================== 759// invalid op_sel operand 760 761v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1] 762// CHECK: error: invalid op_sel operand 763// CHECK-NEXT:{{^}}v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1] 764// CHECK-NEXT:{{^}} ^ 765 766//============================================================================== 767// invalid op_sel value. 768 769v_pk_add_u16 v1, v2, v3 op_sel:[-1,0] 770// CHECK: error: invalid op_sel value. 771// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[-1,0] 772// CHECK-NEXT:{{^}} ^ 773 774//============================================================================== 775// invalid operand (violates constant bus restrictions) 776 777v_ashrrev_i64 v[0:1], 0x100, s[0:1] 778// CHECK: error: invalid operand (violates constant bus restrictions) 779// CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], 0x100, s[0:1] 780// CHECK-NEXT:{{^}} ^ 781 782v_ashrrev_i64 v[0:1], s3, s[0:1] 783// CHECK: error: invalid operand (violates constant bus restrictions) 784// CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], s3, s[0:1] 785// CHECK-NEXT:{{^}} ^ 786 787v_bfe_u32 v0, s1, 0x3039, s2 788// CHECK: error: invalid operand (violates constant bus restrictions) 789// CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, 0x3039, s2 790// CHECK-NEXT:{{^}} ^ 791 792v_bfe_u32 v0, s1, s2, s3 793// CHECK: error: invalid operand (violates constant bus restrictions) 794// CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, s2, s3 795// CHECK-NEXT:{{^}} ^ 796 797v_div_fmas_f32 v5, s3, 0x123, v3 798// CHECK: error: invalid operand (violates constant bus restrictions) 799// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, 0x123, v3 800// CHECK-NEXT:{{^}} ^ 801 802v_div_fmas_f32 v5, s3, v3, 0x123 803// CHECK: error: invalid operand (violates constant bus restrictions) 804// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, v3, 0x123 805// CHECK-NEXT:{{^}} ^ 806 807v_div_fmas_f32 v5, 0x123, v3, s3 808// CHECK: error: invalid operand (violates constant bus restrictions) 809// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, 0x123, v3, s3 810// CHECK-NEXT:{{^}} ^ 811 812v_div_fmas_f32 v5, s3, s4, v3 813// CHECK: error: invalid operand (violates constant bus restrictions) 814// CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, s4, v3 815// CHECK-NEXT:{{^}} ^ 816 817//============================================================================== 818// invalid operand for instruction 819 820buffer_load_dword v5, off, s[8:11], s3 tfe lds 821// CHECK: error: invalid operand for instruction 822// CHECK-NEXT:{{^}}buffer_load_dword v5, off, s[8:11], s3 tfe lds 823// CHECK-NEXT:{{^}} ^ 824 825exp mrt0 0x12345678, v0, v0, v0 826// CHECK: error: invalid operand for instruction 827// CHECK-NEXT:{{^}}exp mrt0 0x12345678, v0, v0, v0 828// CHECK-NEXT:{{^}} ^ 829 830v_cmp_eq_f32 s[0:1], private_base, s0 831// CHECK: error: invalid operand for instruction 832// CHECK-NEXT:{{^}}v_cmp_eq_f32 s[0:1], private_base, s0 833// CHECK-NEXT:{{^}} ^ 834 835//============================================================================== 836// invalid operation id 837 838s_sendmsg sendmsg(15, -1) 839// CHECK: error: invalid operation id 840// CHECK-NEXT:{{^}}s_sendmsg sendmsg(15, -1) 841// CHECK-NEXT:{{^}} ^ 842 843//============================================================================== 844// invalid or unsupported register size 845 846s_mov_b64 s[0:17], -1 847// CHECK: error: invalid or unsupported register size 848// CHECK-NEXT:{{^}}s_mov_b64 s[0:17], -1 849// CHECK-NEXT:{{^}} ^ 850 851//============================================================================== 852// invalid register alignment 853 854s_load_dwordx4 s[1:4], s[2:3], s4 855// CHECK: error: invalid register alignment 856// CHECK-NEXT:{{^}}s_load_dwordx4 s[1:4], s[2:3], s4 857// CHECK-NEXT:{{^}} ^ 858 859//============================================================================== 860// invalid register index 861 862s_mov_b32 s1, s[0:-1] 863// CHECK: error: invalid register index 864// CHECK-NEXT:{{^}}s_mov_b32 s1, s[0:-1] 865// CHECK-NEXT:{{^}} ^ 866 867v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2] 868// CHECK: error: invalid register index 869// CHECK-NEXT:{{^}}v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2] 870// CHECK-NEXT:{{^}} ^ 871 872//============================================================================== 873// invalid register name 874 875s_mov_b64 s[10:11], [x0,s1] 876// CHECK: error: invalid register name 877// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [x0,s1] 878// CHECK-NEXT:{{^}} ^ 879 880//============================================================================== 881// invalid row_share value 882 883v_mov_b32_dpp v5, v1 row_share:16 row_mask:0x0 bank_mask:0x0 884// CHECK: error: invalid row_share value 885// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:16 row_mask:0x0 bank_mask:0x0 886// CHECK-NEXT:{{^}} ^ 887 888v_mov_b32_dpp v5, v1 row_share:-1 row_mask:0x0 bank_mask:0x0 889// CHECK: error: invalid row_share value 890// CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:-1 row_mask:0x0 bank_mask:0x0 891// CHECK-NEXT:{{^}} ^ 892 893//============================================================================== 894// invalid syntax, expected 'neg' modifier 895 896v_ceil_f32 v0, --1 897// CHECK: error: invalid syntax, expected 'neg' modifier 898// CHECK-NEXT:{{^}}v_ceil_f32 v0, --1 899// CHECK-NEXT:{{^}} ^ 900 901//============================================================================== 902// invalid use of lds_direct 903 904v_ashrrev_i16 v0, lds_direct, v0 905// CHECK: error: invalid use of lds_direct 906// CHECK-NEXT:{{^}}v_ashrrev_i16 v0, lds_direct, v0 907// CHECK-NEXT:{{^}} ^ 908 909//============================================================================== 910// lane id must be in the interval [0,group size - 1] 911 912ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1) 913// CHECK: error: lane id must be in the interval [0,group size - 1] 914// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1) 915// CHECK-NEXT:{{^}} ^ 916 917//============================================================================== 918// message does not support operations 919 920s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0) 921// CHECK: error: message does not support operations 922// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0) 923// CHECK-NEXT:{{^}} ^ 924 925//============================================================================== 926// message operation does not support streams 927 928s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0) 929// CHECK: error: message operation does not support streams 930// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0) 931// CHECK-NEXT:{{^}} ^ 932 933//============================================================================== 934// missing message operation 935 936s_sendmsg sendmsg(MSG_SYSMSG) 937// CHECK: error: missing message operation 938// CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_SYSMSG) 939// CHECK-NEXT:{{^}} ^ 940 941//============================================================================== 942// missing register index 943 944s_mov_b64 s[10:11], [s 945// CHECK: error: missing register index 946// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s 947// CHECK-NEXT:{{^}} ^ 948 949s_mov_b64 s[10:11], [s,s1] 950// CHECK: error: missing register index 951// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s,s1] 952// CHECK-NEXT:{{^}} ^ 953 954//============================================================================== 955// not a valid operand. 956 957s_branch offset:1 958// CHECK: error: not a valid operand. 959// CHECK-NEXT:{{^}}s_branch offset:1 960// CHECK-NEXT:{{^}} ^ 961 962v_mov_b32 v0, v0 row_bcast:0 963// CHECK: error: not a valid operand. 964// CHECK-NEXT:{{^}}v_mov_b32 v0, v0 row_bcast:0 965// CHECK-NEXT:{{^}} ^ 966 967//============================================================================== 968// only one literal operand is allowed 969 970s_and_b32 s2, 0x12345678, 0x12345679 971// CHECK: error: only one literal operand is allowed 972// CHECK-NEXT:{{^}}s_and_b32 s2, 0x12345678, 0x12345679 973// CHECK-NEXT:{{^}} ^ 974 975v_add_f64 v[0:1], 1.23456, -abs(1.2345) 976// CHECK: error: only one literal operand is allowed 977// CHECK-NEXT:{{^}}v_add_f64 v[0:1], 1.23456, -abs(1.2345) 978// CHECK-NEXT:{{^}} ^ 979 980v_min3_i16 v5, 0x5678, 0x5678, 0x5679 981// CHECK: error: only one literal operand is allowed 982// CHECK-NEXT:{{^}}v_min3_i16 v5, 0x5678, 0x5678, 0x5679 983// CHECK-NEXT:{{^}} ^ 984 985v_pk_add_f16 v1, 25.0, 25.1 986// CHECK: error: only one literal operand is allowed 987// CHECK-NEXT:{{^}}v_pk_add_f16 v1, 25.0, 25.1 988// CHECK-NEXT:{{^}} ^ 989 990v_fma_mix_f32 v5, 0x7c, 0x7b, 1 991// CHECK: error: only one literal operand is allowed 992// CHECK-NEXT:{{^}}v_fma_mix_f32 v5, 0x7c, 0x7b, 1 993// CHECK-NEXT:{{^}} ^ 994 995v_pk_add_i16 v5, 0x7c, 0x4000 996// CHECK: error: only one literal operand is allowed 997// CHECK-NEXT:{{^}}v_pk_add_i16 v5, 0x7c, 0x4000 998// CHECK-NEXT:{{^}} ^ 999 1000v_pk_add_i16 v5, 0x4400, 0x4000 1001// CHECK: error: only one literal operand is allowed 1002// CHECK-NEXT:{{^}}v_pk_add_i16 v5, 0x4400, 0x4000 1003// CHECK-NEXT:{{^}} ^ 1004 1005v_bfe_u32 v0, v2, 123, undef 1006// CHECK: error: only one literal operand is allowed 1007// CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, 123, undef 1008// CHECK-NEXT:{{^}} ^ 1009 1010v_bfe_u32 v0, v2, undef, 123 1011// CHECK: error: only one literal operand is allowed 1012// CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, undef, 123 1013// CHECK-NEXT:{{^}} ^ 1014 1015//============================================================================== 1016// out of bounds interpolation attribute number 1017 1018v_interp_p1_f32 v0, v1, attr64.w 1019// CHECK: error: out of bounds interpolation attribute number 1020// CHECK-NEXT:{{^}}v_interp_p1_f32 v0, v1, attr64.w 1021// CHECK-NEXT:{{^}} ^ 1022 1023//============================================================================== 1024// out of range format 1025 1026tbuffer_load_format_d16_x v0, off, s[0:3], format:-1, 0 1027// CHECK: error: out of range format 1028// CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:-1, 0 1029// CHECK-NEXT:{{^}} ^ 1030 1031//============================================================================== 1032// register does not fit in the list 1033 1034s_mov_b64 s[10:11], [exec,exec_lo] 1035// CHECK: error: register does not fit in the list 1036// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [exec,exec_lo] 1037// CHECK-NEXT:{{^}} ^ 1038 1039s_mov_b64 s[10:11], [exec_lo,exec] 1040// CHECK: error: register does not fit in the list 1041// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [exec_lo,exec] 1042// CHECK-NEXT:{{^}} ^ 1043 1044//============================================================================== 1045// register index is out of range 1046 1047s_add_i32 s106, s0, s1 1048// CHECK: error: register index is out of range 1049// CHECK-NEXT:{{^}}s_add_i32 s106, s0, s1 1050// CHECK-NEXT:{{^}} ^ 1051 1052s_load_dwordx16 s[100:115], s[2:3], s4 1053// CHECK: error: register index is out of range 1054// CHECK-NEXT:{{^}}s_load_dwordx16 s[100:115], s[2:3], s4 1055// CHECK-NEXT:{{^}} ^ 1056 1057s_mov_b32 ttmp16, 0 1058// CHECK: error: register index is out of range 1059// CHECK-NEXT:{{^}}s_mov_b32 ttmp16, 0 1060// CHECK-NEXT:{{^}} ^ 1061 1062v_add_nc_i32 v256, v0, v1 1063// CHECK: error: register index is out of range 1064// CHECK-NEXT:{{^}}v_add_nc_i32 v256, v0, v1 1065// CHECK-NEXT:{{^}} ^ 1066 1067//============================================================================== 1068// register not available on this GPU 1069 1070s_and_b32 ttmp9, tma_hi, 0x0000ffff 1071// CHECK: error: register not available on this GPU 1072// CHECK-NEXT:{{^}}s_and_b32 ttmp9, tma_hi, 0x0000ffff 1073// CHECK-NEXT:{{^}} ^ 1074 1075s_mov_b32 flat_scratch, -1 1076// CHECK: error: register not available on this GPU 1077// CHECK-NEXT:{{^}}s_mov_b32 flat_scratch, -1 1078// CHECK-NEXT:{{^}} ^ 1079 1080//============================================================================== 1081// registers in a list must be of the same kind 1082 1083s_mov_b64 s[10:11], [a0,v1] 1084// CHECK: error: registers in a list must be of the same kind 1085// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [a0,v1] 1086// CHECK-NEXT:{{^}} ^ 1087 1088//============================================================================== 1089// registers in a list must have consecutive indices 1090 1091s_mov_b64 s[10:11], [a0,a2] 1092// CHECK: error: registers in a list must have consecutive indices 1093// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [a0,a2] 1094// CHECK-NEXT:{{^}} ^ 1095 1096s_mov_b64 s[10:11], [s0,s0] 1097// CHECK: error: registers in a list must have consecutive indices 1098// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s0] 1099// CHECK-NEXT:{{^}} ^ 1100 1101s_mov_b64 s[10:11], [s2,s1] 1102// CHECK: error: registers in a list must have consecutive indices 1103// CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s2,s1] 1104// CHECK-NEXT:{{^}} ^ 1105 1106//============================================================================== 1107// source operand must be a VGPR 1108 1109v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD 1110// CHECK: error: source operand must be a VGPR 1111// CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD 1112// CHECK-NEXT:{{^}} ^ 1113 1114v_movrels_b32_sdwa v0, s0 1115// CHECK: error: source operand must be a VGPR 1116// CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, s0 1117// CHECK-NEXT:{{^}} ^ 1118 1119v_movrels_b32_sdwa v0, shared_base 1120// CHECK: error: source operand must be a VGPR 1121// CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, shared_base 1122// CHECK-NEXT:{{^}} ^ 1123 1124//============================================================================== 1125// specified hardware register is not supported on this GPU 1126 1127s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES) 1128// CHECK: error: specified hardware register is not supported on this GPU 1129// CHECK-NEXT:{{^}}s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES) 1130// CHECK-NEXT:{{^}} ^ 1131 1132//============================================================================== 1133// too few operands for instruction 1134 1135tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] 1136// CHECK: error: too few operands for instruction 1137// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7] 1138// CHECK-NEXT:{{^}}^ 1139 1140v_add_f32_e64 v0, v1 1141// CHECK: error: too few operands for instruction 1142// CHECK-NEXT:{{^}}v_add_f32_e64 v0, v1 1143// CHECK-NEXT:{{^}}^ 1144 1145//============================================================================== 1146// too large value for expcnt 1147 1148s_waitcnt expcnt(8) 1149// CHECK: error: too large value for expcnt 1150// CHECK-NEXT:{{^}}s_waitcnt expcnt(8) 1151// CHECK-NEXT:{{^}} ^ 1152 1153//============================================================================== 1154// too large value for lgkmcnt 1155 1156s_waitcnt lgkmcnt(64) 1157// CHECK: error: too large value for lgkmcnt 1158// CHECK-NEXT:{{^}}s_waitcnt lgkmcnt(64) 1159// CHECK-NEXT:{{^}} ^ 1160 1161//============================================================================== 1162// too large value for vmcnt 1163 1164s_waitcnt vmcnt(64) 1165// CHECK: error: too large value for vmcnt 1166// CHECK-NEXT:{{^}}s_waitcnt vmcnt(64) 1167// CHECK-NEXT:{{^}} ^ 1168 1169//============================================================================== 1170// unknown token in expression 1171 1172ds_swizzle_b32 v8, v2 offset: 1173// CHECK: error: unknown token in expression 1174// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset: 1175// CHECK-NEXT:{{^}} ^ 1176 1177s_sendmsg sendmsg(1 -) 1178// CHECK: error: unknown token in expression 1179// CHECK-NEXT:{{^}}s_sendmsg sendmsg(1 -) 1180// CHECK-NEXT:{{^}} ^ 1181 1182tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s0 1183// CHECK: error: unknown token in expression 1184// CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s0 1185// CHECK-NEXT:{{^}} ^ 1186 1187tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s0 1188// CHECK: error: unknown token in expression 1189// CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s0 1190// CHECK-NEXT:{{^}} ^ 1191 1192v_pk_add_u16 v1, v2, v3 op_sel:[ 1193// CHECK: error: unknown token in expression 1194// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[ 1195// CHECK-NEXT:{{^}} ^ 1196 1197v_pk_add_u16 v1, v2, v3 op_sel:[,0] 1198// CHECK: error: unknown token in expression 1199// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[,0] 1200// CHECK-NEXT:{{^}} ^ 1201 1202v_pk_add_u16 v1, v2, v3 op_sel:[,] 1203// CHECK: error: unknown token in expression 1204// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[,] 1205// CHECK-NEXT:{{^}} ^ 1206 1207v_pk_add_u16 v1, v2, v3 op_sel:[0,] 1208// CHECK: error: unknown token in expression 1209// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,] 1210// CHECK-NEXT:{{^}} ^ 1211 1212v_pk_add_u16 v1, v2, v3 op_sel:[] 1213// CHECK: error: unknown token in expression 1214// CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[] 1215// CHECK-NEXT:{{^}} ^ 1216 1217//============================================================================== 1218// unsupported format 1219 1220tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT] 1221// CHECK: error: unsupported format 1222// CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT] 1223// CHECK-NEXT:{{^}} ^ 1224 1225//============================================================================== 1226// expected vertical bar 1227 1228v_ceil_f32 v1, |1+1| 1229// CHECK: error: expected vertical bar 1230// CHECK-NEXT:{{^}}v_ceil_f32 v1, |1+1| 1231// CHECK-NEXT:{{^}} ^ 1232 1233//============================================================================== 1234// expected left paren after neg 1235 1236v_ceil_f32 v1, neg-(v2) 1237// CHECK: error: expected left paren after neg 1238// CHECK-NEXT:{{^}}v_ceil_f32 v1, neg-(v2) 1239// CHECK-NEXT:{{^}} ^ 1240 1241//============================================================================== 1242// expected left paren after abs 1243 1244v_ceil_f32 v1, abs-(v2) 1245// CHECK: error: expected left paren after abs 1246// CHECK-NEXT:{{^}}v_ceil_f32 v1, abs-(v2) 1247// CHECK-NEXT:{{^}} ^ 1248 1249//============================================================================== 1250// expected left paren after sext 1251 1252v_cmpx_f_i32_sdwa sext[v1], v2 src0_sel:DWORD src1_sel:DWORD 1253// CHECK: error: expected left paren after sext 1254// CHECK-NEXT:{{^}}v_cmpx_f_i32_sdwa sext[v1], v2 src0_sel:DWORD src1_sel:DWORD 1255// CHECK-NEXT:{{^}} ^ 1256 1257//============================================================================== 1258// expected closing parentheses 1259 1260v_ceil_f32 v1, abs(v2] 1261// CHECK: error: expected closing parentheses 1262// CHECK-NEXT:{{^}}v_ceil_f32 v1, abs(v2] 1263// CHECK-NEXT:{{^}} ^ 1264 1265v_ceil_f32 v1, neg(v2] 1266// CHECK: error: expected closing parentheses 1267// CHECK-NEXT:{{^}}v_ceil_f32 v1, neg(v2] 1268// CHECK-NEXT:{{^}} ^ 1269 1270v_cmpx_f_i32_sdwa sext(v1], v2 src0_sel:DWORD src1_sel:DWORD 1271// CHECK: error: expected closing parentheses 1272// CHECK-NEXT:{{^}}v_cmpx_f_i32_sdwa sext(v1], v2 src0_sel:DWORD src1_sel:DWORD 1273// CHECK-NEXT:{{^}} ^ 1274 1275//============================================================================== 1276// expected a left parentheses 1277 1278ds_swizzle_b32 v8, v2 offset:swizzle[QUAD_PERM, 0, 1, 2, 3] 1279// CHECK: error: expected a left parentheses 1280// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle[QUAD_PERM, 0, 1, 2, 3] 1281// CHECK-NEXT:{{^}} ^ 1282 1283//============================================================================== 1284// expected an absolute expression or a label 1285 1286s_branch 1+x 1287// CHECK: error: expected an absolute expression or a label 1288// CHECK-NEXT:{{^}}s_branch 1+x 1289// CHECK-NEXT:{{^}} ^ 1290 1291//============================================================================== 1292// expected a 16-bit offset 1293 1294ds_swizzle_b32 v8, v2 offset:0x10000 1295// CHECK: error: expected a 16-bit offset 1296// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:0x10000 1297// CHECK-NEXT:{{^}} ^ 1298