1//===---- AMDCallingConv.td - Calling Conventions for Radeon GPUs ---------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This describes the calling conventions for the AMD Radeon GPUs.
10//
11//===----------------------------------------------------------------------===//
12
13// Inversion of CCIfInReg
14class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
15class CCIfExtend<CCAction A>
16  : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
17
18// Calling convention for SI
19def CC_SI_Gfx : CallingConv<[
20  // 0-3 are reserved for the stack buffer descriptor
21  // 30-31 are reserved for the return address
22  // 32 is reserved for the stack pointer
23  CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
24    SGPR4, SGPR5, SGPR6, SGPR7,
25    SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
26    SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
27    SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29,
28  ]>>>,
29
30  CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
31    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
32    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
33    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
34    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31
35  ]>>>,
36
37  CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>
38]>;
39
40def RetCC_SI_Gfx : CallingConv<[
41  CCIfType<[i1], CCPromoteToType<i32>>,
42  CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
43
44  // 0-3 are reserved for the stack buffer descriptor
45  // 32 is reserved for the stack pointer
46  CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
47    SGPR4, SGPR5, SGPR6, SGPR7,
48    SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
49    SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
50    SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
51    SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39,
52    SGPR40, SGPR41, SGPR42, SGPR43
53  ]>>>,
54
55  CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
56    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
57    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
58    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
59    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
60    VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
61    VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
62    VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
63    VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
64    VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
65    VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
66    VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
67    VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
68    VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
69    VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
70    VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
71    VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
72    VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
73  ]>>>,
74]>;
75
76def CC_SI_SHADER : CallingConv<[
77
78  CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
79    SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
80    SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
81    SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
82    SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
83    SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39,
84    SGPR40, SGPR41, SGPR42, SGPR43
85  ]>>>,
86
87  // 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs.
88  CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
89    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
90    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
91    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
92    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
93    VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
94    VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
95    VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
96    VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
97    VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
98    VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
99    VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
100    VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
101    VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
102    VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
103    VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
104    VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
105    VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
106  ]>>>
107]>;
108
109def RetCC_SI_Shader : CallingConv<[
110  CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
111  CCIfType<[i32, i16] , CCAssignToReg<[
112    SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
113    SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,
114    SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23,
115    SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31,
116    SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39,
117    SGPR40, SGPR41, SGPR42, SGPR43
118  ]>>,
119
120  // 32*4 + 4 is the minimum for a fetch shader with 32 outputs.
121  CCIfType<[f32, f16, v2f16] , CCAssignToReg<[
122    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
123    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
124    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
125    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31,
126    VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39,
127    VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47,
128    VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55,
129    VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63,
130    VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71,
131    VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79,
132    VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87,
133    VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95,
134    VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103,
135    VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111,
136    VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119,
137    VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127,
138    VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135
139  ]>>
140]>;
141
142def CSR_AMDGPU_VGPRs_24_255 : CalleeSavedRegs<
143  (sequence "VGPR%u", 24, 255)
144>;
145
146def CSR_AMDGPU_VGPRs_32_255 : CalleeSavedRegs<
147  (sequence "VGPR%u", 32, 255)
148>;
149
150def CSR_AMDGPU_VGPRs : CalleeSavedRegs<
151  // The CSRs & scratch-registers are interleaved at a split boundary of 8.
152  (add (sequence "VGPR%u", 40, 47),
153    (sequence "VGPR%u", 56, 63),
154    (sequence "VGPR%u", 72, 79),
155    (sequence "VGPR%u", 88, 95),
156    (sequence "VGPR%u", 104, 111),
157    (sequence "VGPR%u", 120, 127),
158    (sequence "VGPR%u", 136, 143),
159    (sequence "VGPR%u", 152, 159),
160    (sequence "VGPR%u", 168, 175),
161    (sequence "VGPR%u", 184, 191),
162    (sequence "VGPR%u", 200, 207),
163    (sequence "VGPR%u", 216, 223),
164    (sequence "VGPR%u", 232, 239),
165    (sequence "VGPR%u", 248, 255))
166>;
167
168def CSR_AMDGPU_AGPRs_32_255 : CalleeSavedRegs<
169  (sequence "AGPR%u", 32, 255)
170>;
171
172def CSR_AMDGPU_SGPRs_32_105 : CalleeSavedRegs<
173  (sequence "SGPR%u", 32, 105)
174>;
175
176// Just to get the regmask, not for calling convention purposes.
177def CSR_AMDGPU_AllVGPRs : CalleeSavedRegs<
178  (sequence "VGPR%u", 0, 255)
179>;
180
181def CSR_AMDGPU_AllAGPRs : CalleeSavedRegs<
182  (sequence "AGPR%u", 0, 255)
183>;
184def CSR_AMDGPU_AllVectorRegs : CalleeSavedRegs<
185  (add CSR_AMDGPU_AllVGPRs, CSR_AMDGPU_AllAGPRs)
186>;
187
188// Just to get the regmask, not for calling convention purposes.
189def CSR_AMDGPU_AllAllocatableSRegs : CalleeSavedRegs<
190  (add (sequence "SGPR%u", 0, 105), VCC_LO, VCC_HI)
191>;
192
193def CSR_AMDGPU_HighRegs : CalleeSavedRegs<
194  (add CSR_AMDGPU_VGPRs, CSR_AMDGPU_SGPRs_32_105)
195>;
196
197def CSR_AMDGPU_HighRegs_With_AGPRs : CalleeSavedRegs<
198  (add CSR_AMDGPU_HighRegs, CSR_AMDGPU_AGPRs_32_255)
199>;
200
201def CSR_AMDGPU_NoRegs : CalleeSavedRegs<(add)>;
202
203// Calling convention for leaf functions
204def CC_AMDGPU_Func : CallingConv<[
205  CCIfByVal<CCPassByVal<4, 4>>,
206  CCIfType<[i1], CCPromoteToType<i32>>,
207  CCIfType<[i8, i16], CCIfExtend<CCPromoteToType<i32>>>,
208  CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1], CCAssignToReg<[
209    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
210    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
211    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
212    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>,
213  CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>
214]>;
215
216// Calling convention for leaf functions
217def RetCC_AMDGPU_Func : CallingConv<[
218  CCIfType<[i1], CCPromoteToType<i32>>,
219  CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
220  CCIfType<[i32, f32, i16, f16, v2i16, v2f16], CCAssignToReg<[
221    VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
222    VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
223    VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
224    VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>,
225]>;
226
227def CC_AMDGPU : CallingConv<[
228   CCIf<"static_cast<const GCNSubtarget&>"
229         "(State.getMachineFunction().getSubtarget()).getGeneration() >= "
230           "AMDGPUSubtarget::SOUTHERN_ISLANDS",
231        CCDelegateTo<CC_SI_SHADER>>,
232   CCIf<"static_cast<const GCNSubtarget&>"
233         "(State.getMachineFunction().getSubtarget()).getGeneration() >= "
234           "AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C",
235        CCDelegateTo<CC_AMDGPU_Func>>
236]>;
237