1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4...
5---
6name:            v8i8_ST2Twov8b
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10body:             |
11  bb.0:
12    liveins: $d0, $d1, $x0
13
14    ; CHECK-LABEL: name: v8i8_ST2Twov8b
15    ; CHECK: liveins: $d0, $d1, $x0
16    ; CHECK: %ptr:gpr64sp = COPY $x0
17    ; CHECK: %src1:fpr64 = COPY $d0
18    ; CHECK: %src2:fpr64 = COPY $d1
19    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
20    ; CHECK: ST2Twov8b [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
21    ; CHECK: RET_ReallyLR
22    %ptr:gpr(p0) = COPY $x0
23    %src1:fpr(<8 x s8>) = COPY $d0
24    %src2:fpr(<8 x s8>) = COPY $d1
25    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<8 x s8>), %src2(<8 x s8>), %ptr(p0) :: (store (<2 x s64>))
26    RET_ReallyLR
27
28...
29---
30name:            v16i8_ST2Twov16b
31
32legalized:       true
33regBankSelected: true
34tracksRegLiveness: true
35body:             |
36  bb.0:
37    liveins: $q0, $q1, $x0
38
39    ; CHECK-LABEL: name: v16i8_ST2Twov16b
40    ; CHECK: liveins: $q0, $q1, $x0
41    ; CHECK: %ptr:gpr64sp = COPY $x0
42    ; CHECK: %src1:fpr128 = COPY $q0
43    ; CHECK: %src2:fpr128 = COPY $q1
44    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
45    ; CHECK: ST2Twov16b [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
46    ; CHECK: RET_ReallyLR
47    %ptr:gpr(p0) = COPY $x0
48    %src1:fpr(<16 x s8>) = COPY $q0
49    %src2:fpr(<16 x s8>) = COPY $q1
50    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<16 x s8>), %src2(<16 x s8>), %ptr(p0) :: (store (<4 x s64>))
51    RET_ReallyLR
52
53...
54---
55name:            v4i16_ST2Twov4h
56
57legalized:       true
58regBankSelected: true
59tracksRegLiveness: true
60body:             |
61  bb.0:
62    liveins: $d0, $d1, $x0
63
64    ; CHECK-LABEL: name: v4i16_ST2Twov4h
65    ; CHECK: liveins: $d0, $d1, $x0
66    ; CHECK: %ptr:gpr64sp = COPY $x0
67    ; CHECK: %src1:fpr64 = COPY $d0
68    ; CHECK: %src2:fpr64 = COPY $d1
69    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
70    ; CHECK: ST2Twov4h [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
71    ; CHECK: RET_ReallyLR
72    %ptr:gpr(p0) = COPY $x0
73    %src1:fpr(<4 x s16>) = COPY $d0
74    %src2:fpr(<4 x s16>) = COPY $d1
75    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<4 x s16>), %src2(<4 x s16>), %ptr(p0) :: (store (<2 x s64>))
76    RET_ReallyLR
77
78...
79---
80name:            v8i16_ST2Twov8h
81
82legalized:       true
83regBankSelected: true
84tracksRegLiveness: true
85body:             |
86  bb.0:
87    liveins: $q0, $q1, $x0
88
89    ; CHECK-LABEL: name: v8i16_ST2Twov8h
90    ; CHECK: liveins: $q0, $q1, $x0
91    ; CHECK: %ptr:gpr64sp = COPY $x0
92    ; CHECK: %src1:fpr128 = COPY $q0
93    ; CHECK: %src2:fpr128 = COPY $q1
94    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
95    ; CHECK: ST2Twov8h [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
96    ; CHECK: RET_ReallyLR
97    %ptr:gpr(p0) = COPY $x0
98    %src1:fpr(<8 x s16>) = COPY $q0
99    %src2:fpr(<8 x s16>) = COPY $q1
100    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<8 x s16>), %src2(<8 x s16>), %ptr(p0) :: (store (<4 x s64>))
101    RET_ReallyLR
102
103...
104---
105name:            v2i32_ST2Twov2s
106legalized:       true
107regBankSelected: true
108tracksRegLiveness: true
109body:             |
110  bb.0:
111    liveins: $d0, $d1, $x0
112
113    ; CHECK-LABEL: name: v2i32_ST2Twov2s
114    ; CHECK: liveins: $d0, $d1, $x0
115    ; CHECK: %ptr:gpr64sp = COPY $x0
116    ; CHECK: %src1:fpr64 = COPY $d0
117    ; CHECK: %src2:fpr64 = COPY $d1
118    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
119    ; CHECK: ST2Twov2s [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
120    ; CHECK: RET_ReallyLR
121    %ptr:gpr(p0) = COPY $x0
122    %src1:fpr(<2 x s32>) = COPY $d0
123    %src2:fpr(<2 x s32>) = COPY $d1
124    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x s32>), %src2(<2 x s32>), %ptr(p0) :: (store (<2 x s64>))
125    RET_ReallyLR
126
127...
128---
129name:            v4i32_ST2Twov4s
130legalized:       true
131regBankSelected: true
132tracksRegLiveness: true
133body:             |
134  bb.0:
135    liveins: $q0, $q1, $x0
136
137    ; CHECK-LABEL: name: v4i32_ST2Twov4s
138    ; CHECK: liveins: $q0, $q1, $x0
139    ; CHECK: %ptr:gpr64sp = COPY $x0
140    ; CHECK: %src1:fpr128 = COPY $q0
141    ; CHECK: %src2:fpr128 = COPY $q1
142    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
143    ; CHECK: ST2Twov4s [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
144    ; CHECK: RET_ReallyLR
145    %ptr:gpr(p0) = COPY $x0
146    %src1:fpr(<4 x s32>) = COPY $q0
147    %src2:fpr(<4 x s32>) = COPY $q1
148    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<4 x s32>), %src2(<4 x s32>), %ptr(p0) :: (store (<4 x s64>))
149    RET_ReallyLR
150
151...
152---
153name:            v2i64_ST2Twov2d_s64_elts
154legalized:       true
155regBankSelected: true
156tracksRegLiveness: true
157body:             |
158  bb.0:
159    liveins: $q0, $q1, $x0
160
161    ; CHECK-LABEL: name: v2i64_ST2Twov2d_s64_elts
162    ; CHECK: liveins: $q0, $q1, $x0
163    ; CHECK: %ptr:gpr64sp = COPY $x0
164    ; CHECK: %src1:fpr128 = COPY $q0
165    ; CHECK: %src2:fpr128 = COPY $q1
166    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
167    ; CHECK: ST2Twov2d [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
168    ; CHECK: RET_ReallyLR
169    %ptr:gpr(p0) = COPY $x0
170    %src1:fpr(<2 x s64>) = COPY $q0
171    %src2:fpr(<2 x s64>) = COPY $q1
172    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x s64>), %src2(<2 x s64>), %ptr(p0) :: (store (<4 x s64>))
173    RET_ReallyLR
174
175...
176---
177name:            v2i64_ST2Twov2d_s64_p0_elts
178legalized:       true
179regBankSelected: true
180tracksRegLiveness: true
181body:             |
182  bb.0:
183    liveins: $q0, $q1, $x0
184
185    ; CHECK-LABEL: name: v2i64_ST2Twov2d_s64_p0_elts
186    ; CHECK: liveins: $q0, $q1, $x0
187    ; CHECK: %ptr:gpr64sp = COPY $x0
188    ; CHECK: %src1:fpr128 = COPY $q0
189    ; CHECK: %src2:fpr128 = COPY $q1
190    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:qq = REG_SEQUENCE %src1, %subreg.qsub0, %src2, %subreg.qsub1
191    ; CHECK: ST2Twov2d [[REG_SEQUENCE]], %ptr :: (store (<4 x s64>))
192    ; CHECK: RET_ReallyLR
193    %ptr:gpr(p0) = COPY $x0
194    %src1:fpr(<2 x p0>) = COPY $q0
195    %src2:fpr(<2 x p0>) = COPY $q1
196    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(<2 x p0>), %src2(<2 x p0>), %ptr(p0) :: (store (<4 x s64>))
197    RET_ReallyLR
198
199...
200---
201name:            v1i64_ST1Twov1d_s64
202legalized:       true
203regBankSelected: true
204tracksRegLiveness: true
205body:             |
206  bb.0:
207    liveins: $x0, $x1, $x2
208
209    ; CHECK-LABEL: name: v1i64_ST1Twov1d_s64
210    ; CHECK: liveins: $x0, $x1, $x2
211    ; CHECK: %ptr:gpr64sp = COPY $x0
212    ; CHECK: %src1:gpr64all = COPY $x0
213    ; CHECK: %src2:gpr64all = COPY $x1
214    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
215    ; CHECK: ST1Twov1d [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
216    ; CHECK: RET_ReallyLR
217    %ptr:gpr(p0) = COPY $x0
218    %src1:gpr(s64) = COPY $x0
219    %src2:gpr(s64) = COPY $x1
220    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(s64), %src2(s64), %ptr(p0) :: (store (<2 x s64>))
221    RET_ReallyLR
222
223...
224---
225name:            v1i64_ST1Twov1d_p0
226legalized:       true
227regBankSelected: true
228tracksRegLiveness: true
229body:             |
230  bb.0:
231    liveins: $x0, $x1, $x2
232
233    ; CHECK-LABEL: name: v1i64_ST1Twov1d_p0
234    ; CHECK: liveins: $x0, $x1, $x2
235    ; CHECK: %ptr:gpr64sp = COPY $x0
236    ; CHECK: %src1:gpr64all = COPY $x0
237    ; CHECK: %src2:gpr64all = COPY $x1
238    ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:dd = REG_SEQUENCE %src1, %subreg.dsub0, %src2, %subreg.dsub1
239    ; CHECK: ST1Twov1d [[REG_SEQUENCE]], %ptr :: (store (<2 x s64>))
240    ; CHECK: RET_ReallyLR
241    %ptr:gpr(p0) = COPY $x0
242    %src1:gpr(p0) = COPY $x0
243    %src2:gpr(p0) = COPY $x1
244    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.neon.st2), %src1(p0), %src2(p0), %ptr(p0) :: (store (<2 x s64>))
245    RET_ReallyLR
246
247...
248