1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
3
4; fpext <vscale x 2 x half> -> <vscale x 2 x double>
5define <vscale x 2 x double> @ext2_f16_f64(<vscale x 2 x half> *%ptr, i64 %index) {
6; CHECK-LABEL: ext2_f16_f64:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    ptrue p0.d
9; CHECK-NEXT:    ld1h { z0.d }, p0/z, [x0]
10; CHECK-NEXT:    fcvt z0.d, p0/m, z0.h
11; CHECK-NEXT:    ret
12  %load = load <vscale x 2 x half>, <vscale x 2 x half>* %ptr, align 4
13  %load.ext = fpext <vscale x 2 x half> %load to <vscale x 2 x double>
14  ret <vscale x 2 x double> %load.ext
15}
16
17; fpext <vscale x 4 x half> -> <vscale x 4 x double>
18define <vscale x 4 x double> @ext4_f16_f64(<vscale x 4 x half> *%ptr, i64 %index) {
19; CHECK-LABEL: ext4_f16_f64:
20; CHECK:       // %bb.0:
21; CHECK-NEXT:    ptrue p0.s
22; CHECK-NEXT:    ld1h { z0.s }, p0/z, [x0]
23; CHECK-NEXT:    ptrue p0.d
24; CHECK-NEXT:    uunpklo z1.d, z0.s
25; CHECK-NEXT:    uunpkhi z2.d, z0.s
26; CHECK-NEXT:    fcvt z0.d, p0/m, z1.h
27; CHECK-NEXT:    fcvt z1.d, p0/m, z2.h
28; CHECK-NEXT:    ret
29  %load = load <vscale x 4 x half>, <vscale x 4 x half>* %ptr, align 4
30  %load.ext = fpext <vscale x 4 x half> %load to <vscale x 4 x double>
31  ret <vscale x 4 x double> %load.ext
32}
33
34; fpext <vscale x 8 x half> -> <vscale x 8 x double>
35define <vscale x 8 x double> @ext8_f16_f64(<vscale x 8 x half> *%ptr, i64 %index) {
36; CHECK-LABEL: ext8_f16_f64:
37; CHECK:       // %bb.0:
38; CHECK-NEXT:    ptrue p0.h
39; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x0]
40; CHECK-NEXT:    ptrue p0.d
41; CHECK-NEXT:    uunpklo z1.s, z0.h
42; CHECK-NEXT:    uunpkhi z0.s, z0.h
43; CHECK-NEXT:    uunpklo z2.d, z1.s
44; CHECK-NEXT:    uunpkhi z1.d, z1.s
45; CHECK-NEXT:    uunpklo z3.d, z0.s
46; CHECK-NEXT:    uunpkhi z4.d, z0.s
47; CHECK-NEXT:    fcvt z0.d, p0/m, z2.h
48; CHECK-NEXT:    fcvt z1.d, p0/m, z1.h
49; CHECK-NEXT:    fcvt z2.d, p0/m, z3.h
50; CHECK-NEXT:    fcvt z3.d, p0/m, z4.h
51; CHECK-NEXT:    ret
52  %load = load <vscale x 8 x half>, <vscale x 8 x half>* %ptr, align 4
53  %load.ext = fpext <vscale x 8 x half> %load to <vscale x 8 x double>
54  ret <vscale x 8 x double> %load.ext
55}
56
57; fpext <vscale x 2 x float> -> <vscale x 2 x double>
58define <vscale x 2 x double> @ext2_f32_f64(<vscale x 2 x float> *%ptr, i64 %index) {
59; CHECK-LABEL: ext2_f32_f64:
60; CHECK:       // %bb.0:
61; CHECK-NEXT:    ptrue p0.d
62; CHECK-NEXT:    ld1w { z0.d }, p0/z, [x0]
63; CHECK-NEXT:    fcvt z0.d, p0/m, z0.s
64; CHECK-NEXT:    ret
65  %load = load <vscale x 2 x float>, <vscale x 2 x float>* %ptr, align 4
66  %load.ext = fpext <vscale x 2 x float> %load to <vscale x 2 x double>
67  ret <vscale x 2 x double> %load.ext
68}
69
70; fpext <vscale x 4 x float> -> <vscale x 4 x double>
71define <vscale x 4 x double> @ext4_f32_f64(<vscale x 4 x float> *%ptr, i64 %index) {
72; CHECK-LABEL: ext4_f32_f64:
73; CHECK:       // %bb.0:
74; CHECK-NEXT:    ptrue p0.s
75; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
76; CHECK-NEXT:    ptrue p0.d
77; CHECK-NEXT:    uunpklo z1.d, z0.s
78; CHECK-NEXT:    uunpkhi z2.d, z0.s
79; CHECK-NEXT:    fcvt z0.d, p0/m, z1.s
80; CHECK-NEXT:    fcvt z1.d, p0/m, z2.s
81; CHECK-NEXT:    ret
82  %load = load <vscale x 4 x float>, <vscale x 4 x float>* %ptr, align 4
83  %load.ext = fpext <vscale x 4 x float> %load to <vscale x 4 x double>
84  ret <vscale x 4 x double> %load.ext
85}
86