1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji --amdhsa-code-object-version=3 < %s | FileCheck -check-prefix=VI %s
2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 < %s | FileCheck -check-prefix=GFX9 %s
3
4; Make sure the stack is never realigned for entry functions.
5
6define amdgpu_kernel void @max_alignment_128() #0 {
7; VI-LABEL: max_alignment_128:
8; VI:       ; %bb.0:
9; VI-NEXT:    s_add_u32 s0, s0, s7
10; VI-NEXT:    s_addc_u32 s1, s1, 0
11; VI-NEXT:    v_mov_b32_e32 v0, 9
12; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:128
13; VI-NEXT:    s_waitcnt vmcnt(0)
14; VI-NEXT:    s_endpgm
15; VI-NEXT:    .section .rodata,#alloc
16; VI-NEXT:    .p2align 6
17; VI-NEXT:    .amdhsa_kernel max_alignment_128
18; VI-NEXT:     .amdhsa_group_segment_fixed_size 0
19; VI-NEXT:     .amdhsa_private_segment_fixed_size 256
20; VI-NEXT:     .amdhsa_kernarg_size 0
21; VI-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
22; VI-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
23; VI-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
24; VI-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
25; VI-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
26; VI-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
27; VI-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
28; VI-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
29; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
30; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
31; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
32; VI-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
33; VI-NEXT:     .amdhsa_system_vgpr_workitem_id 0
34; VI-NEXT:     .amdhsa_next_free_vgpr 1
35; VI-NEXT:     .amdhsa_next_free_sgpr 8
36; VI-NEXT:     .amdhsa_reserve_vcc 0
37; VI-NEXT:     .amdhsa_reserve_flat_scratch 0
38; VI-NEXT:     .amdhsa_float_round_mode_32 0
39; VI-NEXT:     .amdhsa_float_round_mode_16_64 0
40; VI-NEXT:     .amdhsa_float_denorm_mode_32 3
41; VI-NEXT:     .amdhsa_float_denorm_mode_16_64 3
42; VI-NEXT:     .amdhsa_dx10_clamp 1
43; VI-NEXT:     .amdhsa_ieee_mode 1
44; VI-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
45; VI-NEXT:     .amdhsa_exception_fp_denorm_src 0
46; VI-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
47; VI-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
48; VI-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
49; VI-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
50; VI-NEXT:     .amdhsa_exception_int_div_zero 0
51; VI-NEXT:    .end_amdhsa_kernel
52; VI-NEXT:    .text
53;
54; GFX9-LABEL: max_alignment_128:
55; GFX9:       ; %bb.0:
56; GFX9-NEXT:    s_add_u32 s0, s0, s7
57; GFX9-NEXT:    s_addc_u32 s1, s1, 0
58; GFX9-NEXT:    v_mov_b32_e32 v0, 9
59; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:128
60; GFX9-NEXT:    s_waitcnt vmcnt(0)
61; GFX9-NEXT:    s_endpgm
62; GFX9-NEXT:    .section .rodata,#alloc
63; GFX9-NEXT:    .p2align 6
64; GFX9-NEXT:    .amdhsa_kernel max_alignment_128
65; GFX9-NEXT:     .amdhsa_group_segment_fixed_size 0
66; GFX9-NEXT:     .amdhsa_private_segment_fixed_size 256
67; GFX9-NEXT:     .amdhsa_kernarg_size 0
68; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
69; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
70; GFX9-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
71; GFX9-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
72; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
73; GFX9-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
74; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
75; GFX9-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
76; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
77; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
78; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
79; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
80; GFX9-NEXT:     .amdhsa_system_vgpr_workitem_id 0
81; GFX9-NEXT:     .amdhsa_next_free_vgpr 1
82; GFX9-NEXT:     .amdhsa_next_free_sgpr 8
83; GFX9-NEXT:     .amdhsa_reserve_vcc 0
84; GFX9-NEXT:     .amdhsa_reserve_flat_scratch 0
85; GFX9-NEXT:     .amdhsa_reserve_xnack_mask 1
86; GFX9-NEXT:     .amdhsa_float_round_mode_32 0
87; GFX9-NEXT:     .amdhsa_float_round_mode_16_64 0
88; GFX9-NEXT:     .amdhsa_float_denorm_mode_32 3
89; GFX9-NEXT:     .amdhsa_float_denorm_mode_16_64 3
90; GFX9-NEXT:     .amdhsa_dx10_clamp 1
91; GFX9-NEXT:     .amdhsa_ieee_mode 1
92; GFX9-NEXT:     .amdhsa_fp16_overflow 0
93; GFX9-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
94; GFX9-NEXT:     .amdhsa_exception_fp_denorm_src 0
95; GFX9-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
96; GFX9-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
97; GFX9-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
98; GFX9-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
99; GFX9-NEXT:     .amdhsa_exception_int_div_zero 0
100; GFX9-NEXT:    .end_amdhsa_kernel
101; GFX9-NEXT:    .text
102  %alloca.align = alloca i32, align 128, addrspace(5)
103  store volatile i32 9, i32 addrspace(5)* %alloca.align, align 128
104  ret void
105}
106
107define amdgpu_kernel void @stackrealign_attr() #1 {
108; VI-LABEL: stackrealign_attr:
109; VI:       ; %bb.0:
110; VI-NEXT:    s_add_u32 s0, s0, s7
111; VI-NEXT:    s_addc_u32 s1, s1, 0
112; VI-NEXT:    v_mov_b32_e32 v0, 9
113; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
114; VI-NEXT:    s_waitcnt vmcnt(0)
115; VI-NEXT:    s_endpgm
116; VI-NEXT:    .section .rodata,#alloc
117; VI-NEXT:    .p2align 6
118; VI-NEXT:    .amdhsa_kernel stackrealign_attr
119; VI-NEXT:     .amdhsa_group_segment_fixed_size 0
120; VI-NEXT:     .amdhsa_private_segment_fixed_size 8
121; VI-NEXT:     .amdhsa_kernarg_size 0
122; VI-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
123; VI-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
124; VI-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
125; VI-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
126; VI-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
127; VI-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
128; VI-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
129; VI-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
130; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
131; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
132; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
133; VI-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
134; VI-NEXT:     .amdhsa_system_vgpr_workitem_id 0
135; VI-NEXT:     .amdhsa_next_free_vgpr 1
136; VI-NEXT:     .amdhsa_next_free_sgpr 8
137; VI-NEXT:     .amdhsa_reserve_vcc 0
138; VI-NEXT:     .amdhsa_reserve_flat_scratch 0
139; VI-NEXT:     .amdhsa_float_round_mode_32 0
140; VI-NEXT:     .amdhsa_float_round_mode_16_64 0
141; VI-NEXT:     .amdhsa_float_denorm_mode_32 3
142; VI-NEXT:     .amdhsa_float_denorm_mode_16_64 3
143; VI-NEXT:     .amdhsa_dx10_clamp 1
144; VI-NEXT:     .amdhsa_ieee_mode 1
145; VI-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
146; VI-NEXT:     .amdhsa_exception_fp_denorm_src 0
147; VI-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
148; VI-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
149; VI-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
150; VI-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
151; VI-NEXT:     .amdhsa_exception_int_div_zero 0
152; VI-NEXT:    .end_amdhsa_kernel
153; VI-NEXT:    .text
154;
155; GFX9-LABEL: stackrealign_attr:
156; GFX9:       ; %bb.0:
157; GFX9-NEXT:    s_add_u32 s0, s0, s7
158; GFX9-NEXT:    s_addc_u32 s1, s1, 0
159; GFX9-NEXT:    v_mov_b32_e32 v0, 9
160; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
161; GFX9-NEXT:    s_waitcnt vmcnt(0)
162; GFX9-NEXT:    s_endpgm
163; GFX9-NEXT:    .section .rodata,#alloc
164; GFX9-NEXT:    .p2align 6
165; GFX9-NEXT:    .amdhsa_kernel stackrealign_attr
166; GFX9-NEXT:     .amdhsa_group_segment_fixed_size 0
167; GFX9-NEXT:     .amdhsa_private_segment_fixed_size 8
168; GFX9-NEXT:     .amdhsa_kernarg_size 0
169; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
170; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
171; GFX9-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
172; GFX9-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
173; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
174; GFX9-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
175; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
176; GFX9-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
177; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
178; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
179; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
180; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
181; GFX9-NEXT:     .amdhsa_system_vgpr_workitem_id 0
182; GFX9-NEXT:     .amdhsa_next_free_vgpr 1
183; GFX9-NEXT:     .amdhsa_next_free_sgpr 8
184; GFX9-NEXT:     .amdhsa_reserve_vcc 0
185; GFX9-NEXT:     .amdhsa_reserve_flat_scratch 0
186; GFX9-NEXT:     .amdhsa_reserve_xnack_mask 1
187; GFX9-NEXT:     .amdhsa_float_round_mode_32 0
188; GFX9-NEXT:     .amdhsa_float_round_mode_16_64 0
189; GFX9-NEXT:     .amdhsa_float_denorm_mode_32 3
190; GFX9-NEXT:     .amdhsa_float_denorm_mode_16_64 3
191; GFX9-NEXT:     .amdhsa_dx10_clamp 1
192; GFX9-NEXT:     .amdhsa_ieee_mode 1
193; GFX9-NEXT:     .amdhsa_fp16_overflow 0
194; GFX9-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
195; GFX9-NEXT:     .amdhsa_exception_fp_denorm_src 0
196; GFX9-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
197; GFX9-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
198; GFX9-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
199; GFX9-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
200; GFX9-NEXT:     .amdhsa_exception_int_div_zero 0
201; GFX9-NEXT:    .end_amdhsa_kernel
202; GFX9-NEXT:    .text
203  %alloca.align = alloca i32, align 4, addrspace(5)
204  store volatile i32 9, i32 addrspace(5)* %alloca.align, align 4
205  ret void
206}
207
208define amdgpu_kernel void @alignstack_attr() #2 {
209; VI-LABEL: alignstack_attr:
210; VI:       ; %bb.0:
211; VI-NEXT:    s_add_u32 s0, s0, s7
212; VI-NEXT:    s_addc_u32 s1, s1, 0
213; VI-NEXT:    v_mov_b32_e32 v0, 9
214; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
215; VI-NEXT:    s_waitcnt vmcnt(0)
216; VI-NEXT:    s_endpgm
217; VI-NEXT:    .section .rodata,#alloc
218; VI-NEXT:    .p2align 6
219; VI-NEXT:    .amdhsa_kernel alignstack_attr
220; VI-NEXT:     .amdhsa_group_segment_fixed_size 0
221; VI-NEXT:     .amdhsa_private_segment_fixed_size 128
222; VI-NEXT:     .amdhsa_kernarg_size 0
223; VI-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
224; VI-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
225; VI-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
226; VI-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
227; VI-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
228; VI-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
229; VI-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
230; VI-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
231; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
232; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
233; VI-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
234; VI-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
235; VI-NEXT:     .amdhsa_system_vgpr_workitem_id 0
236; VI-NEXT:     .amdhsa_next_free_vgpr 1
237; VI-NEXT:     .amdhsa_next_free_sgpr 8
238; VI-NEXT:     .amdhsa_reserve_vcc 0
239; VI-NEXT:     .amdhsa_reserve_flat_scratch 0
240; VI-NEXT:     .amdhsa_float_round_mode_32 0
241; VI-NEXT:     .amdhsa_float_round_mode_16_64 0
242; VI-NEXT:     .amdhsa_float_denorm_mode_32 3
243; VI-NEXT:     .amdhsa_float_denorm_mode_16_64 3
244; VI-NEXT:     .amdhsa_dx10_clamp 1
245; VI-NEXT:     .amdhsa_ieee_mode 1
246; VI-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
247; VI-NEXT:     .amdhsa_exception_fp_denorm_src 0
248; VI-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
249; VI-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
250; VI-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
251; VI-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
252; VI-NEXT:     .amdhsa_exception_int_div_zero 0
253; VI-NEXT:    .end_amdhsa_kernel
254; VI-NEXT:    .text
255;
256; GFX9-LABEL: alignstack_attr:
257; GFX9:       ; %bb.0:
258; GFX9-NEXT:    s_add_u32 s0, s0, s7
259; GFX9-NEXT:    s_addc_u32 s1, s1, 0
260; GFX9-NEXT:    v_mov_b32_e32 v0, 9
261; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
262; GFX9-NEXT:    s_waitcnt vmcnt(0)
263; GFX9-NEXT:    s_endpgm
264; GFX9-NEXT:    .section .rodata,#alloc
265; GFX9-NEXT:    .p2align 6
266; GFX9-NEXT:    .amdhsa_kernel alignstack_attr
267; GFX9-NEXT:     .amdhsa_group_segment_fixed_size 0
268; GFX9-NEXT:     .amdhsa_private_segment_fixed_size 128
269; GFX9-NEXT:     .amdhsa_kernarg_size 0
270; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
271; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
272; GFX9-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
273; GFX9-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
274; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
275; GFX9-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
276; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
277; GFX9-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
278; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
279; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
280; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
281; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
282; GFX9-NEXT:     .amdhsa_system_vgpr_workitem_id 0
283; GFX9-NEXT:     .amdhsa_next_free_vgpr 1
284; GFX9-NEXT:     .amdhsa_next_free_sgpr 8
285; GFX9-NEXT:     .amdhsa_reserve_vcc 0
286; GFX9-NEXT:     .amdhsa_reserve_flat_scratch 0
287; GFX9-NEXT:     .amdhsa_reserve_xnack_mask 1
288; GFX9-NEXT:     .amdhsa_float_round_mode_32 0
289; GFX9-NEXT:     .amdhsa_float_round_mode_16_64 0
290; GFX9-NEXT:     .amdhsa_float_denorm_mode_32 3
291; GFX9-NEXT:     .amdhsa_float_denorm_mode_16_64 3
292; GFX9-NEXT:     .amdhsa_dx10_clamp 1
293; GFX9-NEXT:     .amdhsa_ieee_mode 1
294; GFX9-NEXT:     .amdhsa_fp16_overflow 0
295; GFX9-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0
296; GFX9-NEXT:     .amdhsa_exception_fp_denorm_src 0
297; GFX9-NEXT:     .amdhsa_exception_fp_ieee_div_zero 0
298; GFX9-NEXT:     .amdhsa_exception_fp_ieee_overflow 0
299; GFX9-NEXT:     .amdhsa_exception_fp_ieee_underflow 0
300; GFX9-NEXT:     .amdhsa_exception_fp_ieee_inexact 0
301; GFX9-NEXT:     .amdhsa_exception_int_div_zero 0
302; GFX9-NEXT:    .end_amdhsa_kernel
303; GFX9-NEXT:    .text
304  %alloca.align = alloca i32, align 4, addrspace(5)
305  store volatile i32 9, i32 addrspace(5)* %alloca.align, align 4
306  ret void
307}
308
309attributes #0 = { nounwind }
310attributes #1 = { nounwind "stackrealign" }
311attributes #2 = { nounwind alignstack=128 }
312