1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2
3;;; Test insert intrinsic instructions
4;;;
5;;; Note:
6;;;   We test insert_vm512u and insert_vm512l pseudo instructions.
7
8; Function Attrs: nounwind readnone
9define fastcc <512 x i1> @insert_vm512u(<512 x i1> %0, <256 x i1> %1) {
10; CHECK-LABEL: insert_vm512u:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    andm %vm2, %vm0, %vm4
13; CHECK-NEXT:    b.l.t (, %s10)
14  %3 = tail call <512 x i1> @llvm.ve.vl.insert.vm512u(<512 x i1> %0, <256 x i1> %1)
15  ret <512 x i1> %3
16}
17
18; Function Attrs: nounwind readnone
19declare <512 x i1> @llvm.ve.vl.insert.vm512u(<512 x i1>, <256 x i1>)
20
21; Function Attrs: nounwind readnone
22define fastcc <512 x i1> @insert_vm512l(<512 x i1> %0, <256 x i1> %1) {
23; CHECK-LABEL: insert_vm512l:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    andm %vm3, %vm0, %vm4
26; CHECK-NEXT:    b.l.t (, %s10)
27  %3 = tail call <512 x i1> @llvm.ve.vl.insert.vm512l(<512 x i1> %0, <256 x i1> %1)
28  ret <512 x i1> %3
29}
30
31; Function Attrs: nounwind readnone
32declare <512 x i1> @llvm.ve.vl.insert.vm512l(<512 x i1>, <256 x i1>)
33