1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2
3;;; Test vector shuffle intrinsic instructions
4;;;
5;;; Note:
6;;;   We test VSHF*vvrl, VSHF*vvrl_v, VSHF*vvil, and VSHF*vvil_v instructions.
7
8; Function Attrs: nounwind readnone
9define fastcc <256 x double> @vshf_vvvsl(<256 x double> %0, <256 x double> %1, i64 %2) {
10; CHECK-LABEL: vshf_vvvsl:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    lea %s1, 256
13; CHECK-NEXT:    lvl %s1
14; CHECK-NEXT:    vshf %v0, %v0, %v1, %s0
15; CHECK-NEXT:    b.l.t (, %s10)
16  %4 = tail call fast <256 x double> @llvm.ve.vl.vshf.vvvsl(<256 x double> %0, <256 x double> %1, i64 %2, i32 256)
17  ret <256 x double> %4
18}
19
20; Function Attrs: nounwind readnone
21declare <256 x double> @llvm.ve.vl.vshf.vvvsl(<256 x double>, <256 x double>, i64, i32)
22
23; Function Attrs: nounwind readnone
24define fastcc <256 x double> @vshf_vvvsvl(<256 x double> %0, <256 x double> %1, i64 %2, <256 x double> %3) {
25; CHECK-LABEL: vshf_vvvsvl:
26; CHECK:       # %bb.0:
27; CHECK-NEXT:    lea %s1, 128
28; CHECK-NEXT:    lvl %s1
29; CHECK-NEXT:    vshf %v2, %v0, %v1, %s0
30; CHECK-NEXT:    lea %s16, 256
31; CHECK-NEXT:    lvl %s16
32; CHECK-NEXT:    vor %v0, (0)1, %v2
33; CHECK-NEXT:    b.l.t (, %s10)
34  %5 = tail call fast <256 x double> @llvm.ve.vl.vshf.vvvsvl(<256 x double> %0, <256 x double> %1, i64 %2, <256 x double> %3, i32 128)
35  ret <256 x double> %5
36}
37
38; Function Attrs: nounwind readnone
39declare <256 x double> @llvm.ve.vl.vshf.vvvsvl(<256 x double>, <256 x double>, i64, <256 x double>, i32)
40
41; Function Attrs: nounwind readnone
42define fastcc <256 x double> @vshf_vvvsl_imm(<256 x double> %0, <256 x double> %1) {
43; CHECK-LABEL: vshf_vvvsl_imm:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    lea %s0, 256
46; CHECK-NEXT:    lvl %s0
47; CHECK-NEXT:    vshf %v0, %v0, %v1, 8
48; CHECK-NEXT:    b.l.t (, %s10)
49  %3 = tail call fast <256 x double> @llvm.ve.vl.vshf.vvvsl(<256 x double> %0, <256 x double> %1, i64 8, i32 256)
50  ret <256 x double> %3
51}
52
53; Function Attrs: nounwind readnone
54define fastcc <256 x double> @vshf_vvvsvl_imm(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
55; CHECK-LABEL: vshf_vvvsvl_imm:
56; CHECK:       # %bb.0:
57; CHECK-NEXT:    lea %s0, 128
58; CHECK-NEXT:    lvl %s0
59; CHECK-NEXT:    vshf %v2, %v0, %v1, 8
60; CHECK-NEXT:    lea %s16, 256
61; CHECK-NEXT:    lvl %s16
62; CHECK-NEXT:    vor %v0, (0)1, %v2
63; CHECK-NEXT:    b.l.t (, %s10)
64  %4 = tail call fast <256 x double> @llvm.ve.vl.vshf.vvvsvl(<256 x double> %0, <256 x double> %1, i64 8, <256 x double> %2, i32 128)
65  ret <256 x double> %4
66}
67