1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s 2 3 4// --------------------------------------------------------------------------// 5// Immediate out of lower bound [-16, 14]. 6 7st2h {z12.h, z13.h}, p4, [x12, #-18, MUL VL] 8// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14]. 9// CHECK-NEXT: st2h {z12.h, z13.h}, p4, [x12, #-18, MUL VL] 10// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 11 12st2h {z7.h, z8.h}, p3, [x1, #16, MUL VL] 13// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14]. 14// CHECK-NEXT: st2h {z7.h, z8.h}, p3, [x1, #16, MUL VL] 15// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 16 17 18// --------------------------------------------------------------------------// 19// Immediate not a multiple of two. 20 21st2h {z12.h, z13.h}, p4, [x12, #-7, MUL VL] 22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14]. 23// CHECK-NEXT: st2h {z12.h, z13.h}, p4, [x12, #-7, MUL VL] 24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 25 26st2h {z7.h, z8.h}, p3, [x1, #5, MUL VL] 27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14]. 28// CHECK-NEXT: st2h {z7.h, z8.h}, p3, [x1, #5, MUL VL] 29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 30 31 32// --------------------------------------------------------------------------// 33// Invalid scalar + scalar addressing modes 34 35st2h { z0.h, z1.h }, p0, [x0, x0] 36// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' 37// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, x0] 38// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 39 40st2h { z0.h, z1.h }, p0, [x0, xzr] 41// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' 42// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, xzr] 43// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 44 45st2h { z0.h, z1.h }, p0, [x0, x0, lsl #2] 46// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' 47// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, x0, lsl #2] 48// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 49 50st2h { z0.h, z1.h }, p0, [x0, w0] 51// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' 52// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, w0] 53// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 54 55st2h { z0.h, z1.h }, p0, [x0, w0, uxtw] 56// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' 57// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, w0, uxtw] 58// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 59 60 61// --------------------------------------------------------------------------// 62// Invalid predicate 63 64st2h {z2.h, z3.h}, p8, [x15, #10, MUL VL] 65// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) 66// CHECK-NEXT: st2h {z2.h, z3.h}, p8, [x15, #10, MUL VL] 67// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 68 69st2h {z2.h, z3.h}, p7.b, [x15, #10, MUL VL] 70// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) 71// CHECK-NEXT: st2h {z2.h, z3.h}, p7.b, [x15, #10, MUL VL] 72// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 73 74st2h {z2.h, z3.h}, p7.q, [x15, #10, MUL VL] 75// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) 76// CHECK-NEXT: st2h {z2.h, z3.h}, p7.q, [x15, #10, MUL VL] 77// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 78 79 80// --------------------------------------------------------------------------// 81// Invalid vector list. 82 83st2h { }, p0, [x0] 84// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected 85// CHECK-NEXT: st2h { }, p0, [x0] 86// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 87 88st2h { z0.h, z1.h, z2.h }, p0, [x0] 89// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand 90// CHECK-NEXT: st2h { z0.h, z1.h, z2.h }, p0, [x0] 91// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 92 93st2h { z0.h, z1.s }, p0, [x0] 94// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix 95// CHECK-NEXT: st2h { z0.h, z1.s }, p0, [x0] 96// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 97 98st2h { z0.h, z2.h }, p0, [x0] 99// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential 100// CHECK-NEXT: st2h { z0.h, z2.h }, p0, [x0] 101// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 102 103st2h { v0.2d, v1.2d }, p0, [x0] 104// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand 105// CHECK-NEXT: st2h { v0.2d, v1.2d }, p0, [x0] 106// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 107 108 109// --------------------------------------------------------------------------// 110// Negative tests for instructions that are incompatible with movprfx 111 112movprfx z21.h, p5/z, z28.h 113st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] 114// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 115// CHECK-NEXT: st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] 116// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 117 118movprfx z21, z28 119st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] 120// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov 121// CHECK-NEXT: st2h { z21.h, z22.h }, p5, [x10, #10, mul vl] 122// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 123