1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
4
5 #include <riscv_vector.h>
6
7 //
8 // CHECK-RV64-LABEL: @test_vmclr_m_b1(
9 // CHECK-RV64-NEXT: entry:
10 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64 [[VL:%.*]])
11 // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
12 //
test_vmclr_m_b1(size_t vl)13 vbool1_t test_vmclr_m_b1(size_t vl) { return vmclr_m_b1(vl); }
14
15 //
16 // CHECK-RV64-LABEL: @test_vmclr_m_b2(
17 // CHECK-RV64-NEXT: entry:
18 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i64(i64 [[VL:%.*]])
19 // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
20 //
test_vmclr_m_b2(size_t vl)21 vbool2_t test_vmclr_m_b2(size_t vl) { return vmclr_m_b2(vl); }
22
23 //
24 // CHECK-RV64-LABEL: @test_vmclr_m_b4(
25 // CHECK-RV64-NEXT: entry:
26 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i64(i64 [[VL:%.*]])
27 // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
28 //
test_vmclr_m_b4(size_t vl)29 vbool4_t test_vmclr_m_b4(size_t vl) { return vmclr_m_b4(vl); }
30
31 //
32 // CHECK-RV64-LABEL: @test_vmclr_m_b8(
33 // CHECK-RV64-NEXT: entry:
34 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i64(i64 [[VL:%.*]])
35 // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
36 //
test_vmclr_m_b8(size_t vl)37 vbool8_t test_vmclr_m_b8(size_t vl) { return vmclr_m_b8(vl); }
38
39 //
40 // CHECK-RV64-LABEL: @test_vmclr_m_b16(
41 // CHECK-RV64-NEXT: entry:
42 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i64(i64 [[VL:%.*]])
43 // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
44 //
test_vmclr_m_b16(size_t vl)45 vbool16_t test_vmclr_m_b16(size_t vl) { return vmclr_m_b16(vl); }
46
47 //
48 // CHECK-RV64-LABEL: @test_vmclr_m_b32(
49 // CHECK-RV64-NEXT: entry:
50 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i64(i64 [[VL:%.*]])
51 // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
52 //
test_vmclr_m_b32(size_t vl)53 vbool32_t test_vmclr_m_b32(size_t vl) { return vmclr_m_b32(vl); }
54
55 //
56 // CHECK-RV64-LABEL: @test_vmclr_m_b64(
57 // CHECK-RV64-NEXT: entry:
58 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i64(i64 [[VL:%.*]])
59 // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
60 //
test_vmclr_m_b64(size_t vl)61 vbool64_t test_vmclr_m_b64(size_t vl) { return vmclr_m_b64(vl); }
62