1; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=GCN
2
3; GCN-LABEL: and_zext:
4; GCN: v_and_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
5; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
6define amdgpu_kernel void @and_zext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
7  %id = call i32 @llvm.amdgcn.workitem.id.x() #1
8  %ptr = getelementptr i16, i16 addrspace(1)* %in, i32 %id
9  %a = load i16, i16 addrspace(1)* %in
10  %b = load i16, i16 addrspace(1)* %ptr
11  %c = add i16 %a, %b
12  %val16 = and i16 %c, %a
13  %val32 = zext i16 %val16 to i32
14  store i32 %val32, i32 addrspace(1)* %out
15  ret void
16}
17
18; GCN-LABEL: or_zext:
19; GCN: v_or_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
20; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
21define amdgpu_kernel void @or_zext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
22  %id = call i32 @llvm.amdgcn.workitem.id.x() #1
23  %ptr = getelementptr i16, i16 addrspace(1)* %in, i32 %id
24  %a = load i16, i16 addrspace(1)* %in
25  %b = load i16, i16 addrspace(1)* %ptr
26  %c = add i16 %a, %b
27  %val16 = or i16 %c, %a
28  %val32 = zext i16 %val16 to i32
29  store i32 %val32, i32 addrspace(1)* %out
30  ret void
31}
32
33; GCN-LABEL: xor_zext:
34; GCN: v_xor_b32_e32 [[VAL16:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
35; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[VAL16]]
36define amdgpu_kernel void @xor_zext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
37  %id = call i32 @llvm.amdgcn.workitem.id.x() #1
38  %ptr = getelementptr i16, i16 addrspace(1)* %in, i32 %id
39  %a = load i16, i16 addrspace(1)* %in
40  %b = load i16, i16 addrspace(1)* %ptr
41  %c = add i16 %a, %b
42  %val16 = xor i16 %c, %a
43  %val32 = zext i16 %val16 to i32
44  store i32 %val32, i32 addrspace(1)* %out
45  ret void
46}
47
48declare i32 @llvm.amdgcn.workitem.id.x() #1
49
50attributes #1 = { nounwind readnone }
51