1; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN %s 2; RUN: llc -march=amdgcn -mcpu=gfx908 -mattr=-mfma-inline-literal-bug -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN %s 3; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX90A %s 4 5declare <16 x i32> @llvm.amdgcn.mfma.i32.32x32x8i8(i32, i32, <16 x i32>, i32, i32, i32) 6declare <4 x i32> @llvm.amdgcn.mfma.i32.16x16x16i8(i32, i32, <4 x i32>, i32, i32, i32) 7 8; GCN-LABEL: {{^}}test_mfma_i32_32x32x8i8: 9; GCN-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 10; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 11; GCN: s_load_dwordx16 12; GCN-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} 13; GCN: v_mfma_i32_32x32x8i8 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3 14; GFX908-COUNT-16: v_accvgpr_read_b32 15; GFX908: global_store_dwordx4 16; GFX90A-NOT: v_accvgpr_read_b32 17; GFX90A-COUNT-4: global_store_dwordx4 v{{[0-9]+}}, a[{{[0-9:]+}}] 18define amdgpu_kernel void @test_mfma_i32_32x32x8i8(<16 x i32> addrspace(1)* %arg) { 19bb: 20 %in.1 = load <16 x i32>, <16 x i32> addrspace(1)* %arg 21 %mai.1 = tail call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x8i8(i32 1, i32 2, <16 x i32> %in.1, i32 1, i32 2, i32 3) 22 store <16 x i32> %mai.1, <16 x i32> addrspace(1)* %arg 23 ret void 24} 25 26; GCN-LABEL: {{^}}test_mfma_i32_16x16x16i8: 27; GCN-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 28; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 29; GCN: s_load_dwordx4 30; GCN-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}} 31; GCN: v_mfma_i32_16x16x16i8 [[RES:a\[[0-9]+:[0-9]+\]]], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3 32; GFX908-COUNT-4: v_accvgpr_read_b32 33; GFX908: global_store_dwordx4 34; GFX90A-NOT: v_accvgpr_read_b32 35; GFX90A: global_store_dwordx4 v{{[0-9]+}}, [[RES]] 36define amdgpu_kernel void @test_mfma_i32_16x16x16i8(<4 x i32> addrspace(1)* %arg) { 37bb: 38 %in.1 = load <4 x i32>, <4 x i32> addrspace(1)* %arg 39 %mai.1 = tail call <4 x i32> @llvm.amdgcn.mfma.i32.16x16x16i8(i32 1, i32 2, <4 x i32> %in.1, i32 1, i32 2, i32 3) 40 store <4 x i32> %mai.1, <4 x i32> addrspace(1)* %arg 41 ret void 42} 43