1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 3; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s 4; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 5 6; Ensure two if.break calls, for both the inner and outer loops 7; FIXME: duplicate comparison 8define amdgpu_vs void @multi_else_break(<4 x float> %vec, i32 %ub, i32 %cont) { 9; OPT-LABEL: @multi_else_break( 10; OPT-NEXT: main_body: 11; OPT-NEXT: br label [[LOOP_OUTER:%.*]] 12; OPT: LOOP.outer: 13; OPT-NEXT: [[PHI_BROKEN2:%.*]] = phi i64 [ [[TMP9:%.*]], [[FLOW1:%.*]] ], [ 0, [[MAIN_BODY:%.*]] ] 14; OPT-NEXT: [[TMP43:%.*]] = phi i32 [ 0, [[MAIN_BODY]] ], [ [[TMP4:%.*]], [[FLOW1]] ] 15; OPT-NEXT: br label [[LOOP:%.*]] 16; OPT: LOOP: 17; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP7:%.*]], [[FLOW:%.*]] ], [ 0, [[LOOP_OUTER]] ] 18; OPT-NEXT: [[TMP0:%.*]] = phi i32 [ undef, [[LOOP_OUTER]] ], [ [[TMP4]], [[FLOW]] ] 19; OPT-NEXT: [[TMP45:%.*]] = phi i32 [ [[TMP43]], [[LOOP_OUTER]] ], [ [[TMP47:%.*]], [[FLOW]] ] 20; OPT-NEXT: [[TMP47]] = add i32 [[TMP45]], 1 21; OPT-NEXT: [[TMP48:%.*]] = icmp slt i32 [[TMP45]], [[UB:%.*]] 22; OPT-NEXT: [[TMP1:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP48]]) 23; OPT-NEXT: [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP1]], 0 24; OPT-NEXT: [[TMP3:%.*]] = extractvalue { i1, i64 } [[TMP1]], 1 25; OPT-NEXT: br i1 [[TMP2]], label [[ENDIF:%.*]], label [[FLOW]] 26; OPT: Flow: 27; OPT-NEXT: [[TMP4]] = phi i32 [ [[TMP47]], [[ENDIF]] ], [ [[TMP0]], [[LOOP]] ] 28; OPT-NEXT: [[TMP5:%.*]] = phi i1 [ [[TMP51:%.*]], [[ENDIF]] ], [ true, [[LOOP]] ] 29; OPT-NEXT: [[TMP6:%.*]] = phi i1 [ [[TMP11:%.*]], [[ENDIF]] ], [ true, [[LOOP]] ] 30; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP3]]) 31; OPT-NEXT: [[TMP7]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP6]], i64 [[PHI_BROKEN]]) 32; OPT-NEXT: [[TMP8:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP7]]) 33; OPT-NEXT: [[TMP9]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP5]], i64 [[PHI_BROKEN2]]) 34; OPT-NEXT: br i1 [[TMP8]], label [[FLOW1]], label [[LOOP]] 35; OPT: Flow1: 36; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP7]]) 37; OPT-NEXT: [[TMP10:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP9]]) 38; OPT-NEXT: br i1 [[TMP10]], label [[IF:%.*]], label [[LOOP_OUTER]] 39; OPT: IF: 40; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP9]]) 41; OPT-NEXT: ret void 42; OPT: ENDIF: 43; OPT-NEXT: [[TMP51]] = icmp eq i32 [[TMP47]], [[CONT:%.*]] 44; OPT-NEXT: [[TMP11]] = xor i1 [[TMP51]], true 45; OPT-NEXT: br label [[FLOW]] 46; 47; GCN-LABEL: multi_else_break: 48; GCN: ; %bb.0: ; %main_body 49; GCN-NEXT: s_mov_b64 s[0:1], 0 50; GCN-NEXT: v_mov_b32_e32 v0, 0 51; GCN-NEXT: s_branch BB0_2 52; GCN-NEXT: BB0_1: ; %loop.exit.guard 53; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1 54; GCN-NEXT: s_or_b64 exec, exec, s[4:5] 55; GCN-NEXT: s_and_b64 s[2:3], exec, s[2:3] 56; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] 57; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1] 58; GCN-NEXT: s_cbranch_execz BB0_6 59; GCN-NEXT: BB0_2: ; %LOOP.outer 60; GCN-NEXT: ; =>This Loop Header: Depth=1 61; GCN-NEXT: ; Child Loop BB0_4 Depth 2 62; GCN-NEXT: ; implicit-def: $sgpr6_sgpr7 63; GCN-NEXT: ; implicit-def: $sgpr2_sgpr3 64; GCN-NEXT: s_mov_b64 s[4:5], 0 65; GCN-NEXT: s_branch BB0_4 66; GCN-NEXT: BB0_3: ; %Flow 67; GCN-NEXT: ; in Loop: Header=BB0_4 Depth=2 68; GCN-NEXT: s_or_b64 exec, exec, s[8:9] 69; GCN-NEXT: s_and_b64 s[8:9], exec, s[6:7] 70; GCN-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5] 71; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5] 72; GCN-NEXT: s_cbranch_execz BB0_1 73; GCN-NEXT: BB0_4: ; %LOOP 74; GCN-NEXT: ; Parent Loop BB0_2 Depth=1 75; GCN-NEXT: ; => This Inner Loop Header: Depth=2 76; GCN-NEXT: v_cmp_lt_i32_e32 vcc, v0, v4 77; GCN-NEXT: s_or_b64 s[2:3], s[2:3], exec 78; GCN-NEXT: s_or_b64 s[6:7], s[6:7], exec 79; GCN-NEXT: s_and_saveexec_b64 s[8:9], vcc 80; GCN-NEXT: s_cbranch_execz BB0_3 81; GCN-NEXT: ; %bb.5: ; %ENDIF 82; GCN-NEXT: ; in Loop: Header=BB0_4 Depth=2 83; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v0 84; GCN-NEXT: s_andn2_b64 s[2:3], s[2:3], exec 85; GCN-NEXT: v_cmp_ne_u32_e32 vcc, v5, v0 86; GCN-NEXT: s_andn2_b64 s[6:7], s[6:7], exec 87; GCN-NEXT: s_and_b64 s[10:11], vcc, exec 88; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] 89; GCN-NEXT: s_branch BB0_3 90; GCN-NEXT: BB0_6: ; %IF 91; GCN-NEXT: s_endpgm 92main_body: 93 br label %LOOP.outer 94 95LOOP.outer: ; preds = %ENDIF, %main_body 96 %tmp43 = phi i32 [ 0, %main_body ], [ %tmp47, %ENDIF ] 97 br label %LOOP 98 99LOOP: ; preds = %ENDIF, %LOOP.outer 100 %tmp45 = phi i32 [ %tmp43, %LOOP.outer ], [ %tmp47, %ENDIF ] 101 %tmp47 = add i32 %tmp45, 1 102 %tmp48 = icmp slt i32 %tmp45, %ub 103 br i1 %tmp48, label %ENDIF, label %IF 104 105IF: ; preds = %LOOP 106 ret void 107 108ENDIF: ; preds = %LOOP 109 %tmp51 = icmp eq i32 %tmp47, %cont 110 br i1 %tmp51, label %LOOP, label %LOOP.outer 111} 112 113define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 { 114; OPT-LABEL: @multi_if_break_loop( 115; OPT-NEXT: bb: 116; OPT-NEXT: [[ID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x() 117; OPT-NEXT: [[TMP:%.*]] = sub i32 [[ID]], [[ARG:%.*]] 118; OPT-NEXT: br label [[BB1:%.*]] 119; OPT: bb1: 120; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ [[TMP5:%.*]], [[FLOW4:%.*]] ], [ 0, [[BB:%.*]] ] 121; OPT-NEXT: [[LSR_IV:%.*]] = phi i32 [ undef, [[BB]] ], [ [[LSR_IV_NEXT:%.*]], [[FLOW4]] ] 122; OPT-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1 123; OPT-NEXT: [[CMP0:%.*]] = icmp slt i32 [[LSR_IV_NEXT]], 0 124; OPT-NEXT: [[LOAD0:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4 125; OPT-NEXT: br label [[NODEBLOCK:%.*]] 126; OPT: NodeBlock: 127; OPT-NEXT: [[PIVOT:%.*]] = icmp slt i32 [[LOAD0]], 1 128; OPT-NEXT: [[TMP0:%.*]] = xor i1 [[PIVOT]], true 129; OPT-NEXT: br i1 [[TMP0]], label [[LEAFBLOCK1:%.*]], label [[FLOW:%.*]] 130; OPT: LeafBlock1: 131; OPT-NEXT: [[SWITCHLEAF2:%.*]] = icmp eq i32 [[LOAD0]], 1 132; OPT-NEXT: br i1 [[SWITCHLEAF2]], label [[CASE1:%.*]], label [[FLOW3:%.*]] 133; OPT: Flow3: 134; OPT-NEXT: [[TMP1:%.*]] = phi i1 [ [[TMP11:%.*]], [[CASE1]] ], [ true, [[LEAFBLOCK1]] ] 135; OPT-NEXT: [[TMP2:%.*]] = phi i1 [ false, [[CASE1]] ], [ true, [[LEAFBLOCK1]] ] 136; OPT-NEXT: br label [[FLOW]] 137; OPT: LeafBlock: 138; OPT-NEXT: [[SWITCHLEAF:%.*]] = icmp eq i32 [[LOAD0]], 0 139; OPT-NEXT: br i1 [[SWITCHLEAF]], label [[CASE0:%.*]], label [[FLOW5:%.*]] 140; OPT: Flow4: 141; OPT-NEXT: [[TMP3:%.*]] = phi i1 [ [[TMP12:%.*]], [[FLOW5]] ], [ [[TMP8:%.*]], [[FLOW]] ] 142; OPT-NEXT: [[TMP4:%.*]] = phi i1 [ [[TMP13:%.*]], [[FLOW5]] ], [ [[TMP9:%.*]], [[FLOW]] ] 143; OPT-NEXT: [[TMP5]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP3]], i64 [[PHI_BROKEN]]) 144; OPT-NEXT: [[TMP6:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP5]]) 145; OPT-NEXT: br i1 [[TMP6]], label [[FLOW6:%.*]], label [[BB1]] 146; OPT: case0: 147; OPT-NEXT: [[LOAD1:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4 148; OPT-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP]], [[LOAD1]] 149; OPT-NEXT: [[TMP7:%.*]] = xor i1 [[CMP1]], true 150; OPT-NEXT: br label [[FLOW5]] 151; OPT: Flow: 152; OPT-NEXT: [[TMP8]] = phi i1 [ [[TMP1]], [[FLOW3]] ], [ true, [[NODEBLOCK]] ] 153; OPT-NEXT: [[TMP9]] = phi i1 [ [[TMP2]], [[FLOW3]] ], [ false, [[NODEBLOCK]] ] 154; OPT-NEXT: [[TMP10:%.*]] = phi i1 [ false, [[FLOW3]] ], [ true, [[NODEBLOCK]] ] 155; OPT-NEXT: br i1 [[TMP10]], label [[LEAFBLOCK:%.*]], label [[FLOW4]] 156; OPT: case1: 157; OPT-NEXT: [[LOAD2:%.*]] = load volatile i32, i32 addrspace(1)* undef, align 4 158; OPT-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP]], [[LOAD2]] 159; OPT-NEXT: [[TMP11]] = xor i1 [[CMP2]], true 160; OPT-NEXT: br label [[FLOW3]] 161; OPT: Flow5: 162; OPT-NEXT: [[TMP12]] = phi i1 [ [[TMP7]], [[CASE0]] ], [ [[TMP8]], [[LEAFBLOCK]] ] 163; OPT-NEXT: [[TMP13]] = phi i1 [ false, [[CASE0]] ], [ true, [[LEAFBLOCK]] ] 164; OPT-NEXT: br label [[FLOW4]] 165; OPT: Flow6: 166; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP5]]) 167; OPT-NEXT: [[TMP14:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP4]]) 168; OPT-NEXT: [[TMP15:%.*]] = extractvalue { i1, i64 } [[TMP14]], 0 169; OPT-NEXT: [[TMP16:%.*]] = extractvalue { i1, i64 } [[TMP14]], 1 170; OPT-NEXT: br i1 [[TMP15]], label [[NEWDEFAULT:%.*]], label [[BB9:%.*]] 171; OPT: NewDefault: 172; OPT-NEXT: br label [[BB9]] 173; OPT: bb9: 174; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP16]]) 175; OPT-NEXT: ret void 176; 177; GCN-LABEL: multi_if_break_loop: 178; GCN: ; %bb.0: ; %bb 179; GCN-NEXT: s_load_dword s2, s[0:1], 0x9 180; GCN-NEXT: s_mov_b64 s[0:1], 0 181; GCN-NEXT: s_mov_b32 s3, 0xf000 182; GCN-NEXT: s_waitcnt lgkmcnt(0) 183; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 184; GCN-NEXT: s_mov_b32 s2, -1 185; GCN-NEXT: ; implicit-def: $sgpr4_sgpr5 186; GCN-NEXT: s_branch BB1_2 187; GCN-NEXT: BB1_1: ; %Flow4 188; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 189; GCN-NEXT: s_and_b64 s[6:7], exec, s[6:7] 190; GCN-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1] 191; GCN-NEXT: s_andn2_b64 s[4:5], s[4:5], exec 192; GCN-NEXT: s_and_b64 s[6:7], s[8:9], exec 193; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] 194; GCN-NEXT: s_andn2_b64 exec, exec, s[0:1] 195; GCN-NEXT: s_cbranch_execz BB1_9 196; GCN-NEXT: BB1_2: ; %bb1 197; GCN-NEXT: ; =>This Inner Loop Header: Depth=1 198; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc 199; GCN-NEXT: s_waitcnt vmcnt(0) 200; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1 201; GCN-NEXT: s_mov_b64 s[6:7], -1 202; GCN-NEXT: s_and_b64 vcc, exec, vcc 203; GCN-NEXT: ; implicit-def: $sgpr8_sgpr9 204; GCN-NEXT: s_mov_b64 s[10:11], -1 205; GCN-NEXT: s_cbranch_vccnz BB1_6 206; GCN-NEXT: ; %bb.3: ; %LeafBlock1 207; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 208; GCN-NEXT: s_mov_b64 s[6:7], -1 209; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1 210; GCN-NEXT: s_and_b64 vcc, exec, vcc 211; GCN-NEXT: s_mov_b64 s[8:9], -1 212; GCN-NEXT: s_cbranch_vccz BB1_5 213; GCN-NEXT: ; %bb.4: ; %case1 214; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 215; GCN-NEXT: buffer_load_dword v2, off, s[0:3], 0 glc 216; GCN-NEXT: s_waitcnt vmcnt(0) 217; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v2 218; GCN-NEXT: s_mov_b64 s[8:9], 0 219; GCN-NEXT: s_orn2_b64 s[6:7], vcc, exec 220; GCN-NEXT: BB1_5: ; %Flow3 221; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 222; GCN-NEXT: s_mov_b64 s[10:11], 0 223; GCN-NEXT: BB1_6: ; %Flow 224; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 225; GCN-NEXT: s_and_b64 vcc, exec, s[10:11] 226; GCN-NEXT: s_cbranch_vccz BB1_1 227; GCN-NEXT: ; %bb.7: ; %LeafBlock 228; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 229; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 230; GCN-NEXT: s_and_b64 vcc, exec, vcc 231; GCN-NEXT: s_mov_b64 s[8:9], -1 232; GCN-NEXT: s_cbranch_vccz BB1_1 233; GCN-NEXT: ; %bb.8: ; %case0 234; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 235; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc 236; GCN-NEXT: s_waitcnt vmcnt(0) 237; GCN-NEXT: s_mov_b64 s[8:9], 0 238; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 239; GCN-NEXT: s_andn2_b64 s[6:7], s[6:7], exec 240; GCN-NEXT: s_and_b64 s[10:11], vcc, exec 241; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] 242; GCN-NEXT: s_branch BB1_1 243; GCN-NEXT: BB1_9: ; %loop.exit.guard 244; GCN-NEXT: s_or_b64 exec, exec, s[0:1] 245; GCN-NEXT: s_and_saveexec_b64 s[0:1], s[4:5] 246; GCN-NEXT: s_xor_b64 s[0:1], exec, s[0:1] 247; GCN-NEXT: s_endpgm 248bb: 249 %id = call i32 @llvm.amdgcn.workitem.id.x() 250 %tmp = sub i32 %id, %arg 251 br label %bb1 252 253bb1: 254 %lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %case0 ], [ %lsr.iv.next, %case1 ] 255 %lsr.iv.next = add i32 %lsr.iv, 1 256 %cmp0 = icmp slt i32 %lsr.iv.next, 0 257 %load0 = load volatile i32, i32 addrspace(1)* undef, align 4 258 switch i32 %load0, label %bb9 [ 259 i32 0, label %case0 260 i32 1, label %case1 261 ] 262 263case0: 264 %load1 = load volatile i32, i32 addrspace(1)* undef, align 4 265 %cmp1 = icmp slt i32 %tmp, %load1 266 br i1 %cmp1, label %bb1, label %bb9 267 268case1: 269 %load2 = load volatile i32, i32 addrspace(1)* undef, align 4 270 %cmp2 = icmp slt i32 %tmp, %load2 271 br i1 %cmp2, label %bb1, label %bb9 272 273bb9: 274 ret void 275} 276 277declare i32 @llvm.amdgcn.workitem.id.x() #1 278 279attributes #0 = { nounwind } 280attributes #1 = { nounwind readnone } 281