1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
2
3; CHECK: {{^}}main:
4; CHECK: MULADD_IEEE *
5; CHECK-NOT: MULADD_IEEE *
6
7define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) {
8   %w0 = extractelement <4 x float> %reg0, i32 3
9   %w1 = extractelement <4 x float> %reg1, i32 3
10   %w2 = extractelement <4 x float> %reg2, i32 3
11   %sq0 = fmul float %w0, %w0
12   %r0 = fadd float %sq0, 2.0
13   %sq1 = fmul float %w1, %w1
14   %r1 = fadd float %sq1, 2.0
15   %sq2 = fmul float %w2, %w2
16   %r2 = fadd float %sq2, 2.0
17   %v0 = insertelement <4 x float> undef, float %r0, i32 0
18   %v1 = insertelement <4 x float> %v0, float %r1, i32 1
19   %v2 = insertelement <4 x float> %v1, float %r2, i32 2
20   %res = call float @llvm.r600.dot4(<4 x float> %v2, <4 x float> %v2)
21   %vecres = insertelement <4 x float> undef, float %res, i32 0
22   call void @llvm.r600.store.swizzle(<4 x float> %vecres, i32 0, i32 2)
23   ret void
24}
25
26; Function Attrs: readnone
27declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1
28
29declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
30
31attributes #1 = { readnone }
32