1; RUN: llc -march=arc < %s | FileCheck %s
2
3; CHECK-LABEL: add_r
4; CHECK: add %r0, %r{{[01]}}, %r{{[01]}}
5define i32 @add_r(i32 %a, i32 %b) nounwind {
6entry:
7  %v = add i32 %a, %b
8  ret i32 %v
9}
10
11; CHECK-LABEL: add_u6
12; CHECK: add %r0, %r0, 15
13define i32 @add_u6(i32 %a) nounwind {
14  %v = add i32 %a, 15
15  ret i32 %v
16}
17
18; CHECK-LABEL: add_limm
19; CHECK: add %r0, %r0, 12345
20define i32 @add_limm(i32 %a) nounwind {
21  %v = add i32 %a, 12345
22  ret i32 %v
23}
24
25; CHECK-LABEL: mpy_r
26; CHECK: mpy %r0, %r{{[01]}}, %r{{[01]}}
27define i32 @mpy_r(i32 %a, i32 %b) nounwind {
28entry:
29  %v = mul i32 %a, %b
30  ret i32 %v
31}
32
33; CHECK-LABEL: mpy_u6
34; CHECK: mpy %r0, %r0, 10
35define i32 @mpy_u6(i32 %a) nounwind {
36  %v = mul i32 %a, 10
37  ret i32 %v
38}
39
40; CHECK-LABEL: mpy_limm
41; CHECK: mpy %r0, %r0, 12345
42define i32 @mpy_limm(i32 %a) nounwind {
43  %v = mul i32 %a, 12345
44  ret i32 %v
45}
46
47; CHECK-LABEL: max_r
48; CHECK: max %r0, %r{{[01]}}, %r{{[01]}}
49define i32 @max_r(i32 %a, i32 %b) nounwind {
50  %i = icmp sgt i32 %a, %b
51  %v = select i1 %i, i32 %a, i32 %b
52  ret i32 %v
53}
54
55; CHECK-LABEL: max_u6
56; CHECK: max %r0, %r0, 12
57define i32 @max_u6(i32 %a) nounwind {
58  %i = icmp sgt i32 %a, 12
59  %v = select i1 %i, i32 %a, i32 12
60  ret i32 %v
61}
62
63; CHECK-LABEL: max_limm
64; CHECK: max %r0, %r0, 2345
65define i32 @max_limm(i32 %a) nounwind {
66  %i = icmp sgt i32 %a, 2345
67  %v = select i1 %i, i32 %a, i32 2345
68  ret i32 %v
69}
70
71; CHECK-LABEL: min_r
72; CHECK: min %r0, %r{{[01]}}, %r{{[01]}}
73define i32 @min_r(i32 %a, i32 %b) nounwind {
74  %i = icmp slt i32 %a, %b
75  %v = select i1 %i, i32 %a, i32 %b
76  ret i32 %v
77}
78
79; CHECK-LABEL: min_u6
80; CHECK: min %r0, %r0, 20
81define i32 @min_u6(i32 %a) nounwind {
82  %i = icmp slt i32 %a, 20
83  %v = select i1 %i, i32 %a, i32 20
84  ret i32 %v
85}
86
87; CHECK-LABEL: min_limm
88; CHECK: min %r0, %r0, 2040
89define i32 @min_limm(i32 %a) nounwind {
90  %i = icmp slt i32 %a, 2040
91  %v = select i1 %i, i32 %a, i32 2040
92  ret i32 %v
93}
94
95; CHECK-LABEL: and_r
96; CHECK: and %r0, %r{{[01]}}, %r{{[01]}}
97define i32 @and_r(i32 %a, i32 %b) nounwind {
98  %v = and i32 %a, %b
99  ret i32 %v
100}
101
102; CHECK-LABEL: and_u6
103; CHECK: and %r0, %r0, 7
104define i32 @and_u6(i32 %a) nounwind {
105  %v = and i32 %a, 7
106  ret i32 %v
107}
108
109; 0xfffff == 1048575
110; CHECK-LABEL: and_limm
111; CHECK: and %r0, %r0, 1048575
112define i32 @and_limm(i32 %a) nounwind {
113  %v = and i32 %a, 1048575
114  ret i32 %v
115}
116
117; CHECK-LABEL: or_r
118; CHECK: or %r0, %r{{[01]}}, %r{{[01]}}
119define i32 @or_r(i32 %a, i32 %b) nounwind {
120  %v = or i32 %a, %b
121  ret i32 %v
122}
123
124; CHECK-LABEL: or_u6
125; CHECK: or %r0, %r0, 7
126define i32 @or_u6(i32 %a) nounwind {
127  %v = or i32 %a, 7
128  ret i32 %v
129}
130
131; 0xf0f0f == 986895
132; CHECK-LABEL: or_limm
133define i32 @or_limm(i32 %a) nounwind {
134  %v = or i32 %a, 986895
135  ret i32 %v
136}
137
138; CHECK-LABEL: xor_r
139; CHECK: xor %r0, %r{{[01]}}, %r{{[01]}}
140define i32 @xor_r(i32 %a, i32 %b) nounwind {
141  %v = xor i32 %a, %b
142  ret i32 %v
143}
144
145; CHECK-LABEL: xor_u6
146; CHECK: xor %r0, %r0, 3
147define i32 @xor_u6(i32 %a) nounwind {
148  %v = xor i32 %a, 3
149  ret i32 %v
150}
151
152; CHECK-LABEL: xor_limm
153; CHECK: xor %r0, %r0, 986895
154define i32 @xor_limm(i32 %a) nounwind {
155  %v = xor i32 %a, 986895
156  ret i32 %v
157}
158
159; CHECK-LABEL: asl_r
160; CHECK: asl %r0, %r{{[01]}}, %r{{[01]}}
161define i32 @asl_r(i32 %a, i32 %b) nounwind {
162  %v = shl i32 %a, %b
163  ret i32 %v
164}
165
166; CHECK-LABEL: asl_u6
167; CHECK: asl %r0, %r0, 4
168define i32 @asl_u6(i32 %a) nounwind {
169  %v = shl i32 %a, 4
170  ret i32 %v
171}
172
173; CHECK-LABEL: lsr_r
174; CHECK: lsr %r0, %r{{[01]}}, %r{{[01]}}
175define i32 @lsr_r(i32 %a, i32 %b) nounwind {
176  %v = lshr i32 %a, %b
177  ret i32 %v
178}
179
180; CHECK-LABEL: lsr_u6
181; CHECK: lsr %r0, %r0, 6
182define i32 @lsr_u6(i32 %a) nounwind {
183  %v = lshr i32 %a, 6
184  ret i32 %v
185}
186
187; CHECK-LABEL: asr_r
188; CHECK: asr %r0, %r{{[01]}}, %r{{[01]}}
189define i32 @asr_r(i32 %a, i32 %b) nounwind {
190  %v = ashr i32 %a, %b
191  ret i32 %v
192}
193
194; CHECK-LABEL: asr_u6
195; CHECK: asr %r0, %r0, 8
196define i32 @asr_u6(i32 %a) nounwind {
197  %v = ashr i32 %a, 8
198  ret i32 %v
199}
200
201; CHECK-LABEL: ror_r
202; CHECK: ror %r0, %r{{[01]}}, %r{{[01]}}
203define i32 @ror_r(i32 %a, i32 %b) nounwind {
204  %v1 = lshr i32 %a, %b
205  %ls = sub i32 32, %b
206  %v2 = shl i32 %a, %ls
207  %v = or i32 %v1, %v2
208  ret i32 %v
209}
210
211; CHECK-LABEL: ror_u6
212; CHECK: ror %r0, %r0, 10
213define i32 @ror_u6(i32 %a) nounwind {
214  %v1 = lshr i32 %a, 10
215  %v2 = shl i32 %a, 22
216  %v = or i32 %v1, %v2
217  ret i32 %v
218}
219
220; CHECK-LABEL: sexh_r
221; CHECK: sexh %r0, %r0
222define i32 @sexh_r(i32 %a) nounwind {
223  %v1 = shl i32 %a, 16
224  %v = ashr i32 %v1, 16
225  ret i32 %v
226}
227
228; CHECK-LABEL: sexb_r
229; CHECK: sexb %r0, %r0
230define i32 @sexb_r(i32 %a) nounwind {
231  %v1 = shl i32 %a, 24
232  %v = ashr i32 %v1, 24
233  ret i32 %v
234}
235
236; CHECK-LABEL: mulu64
237; CHECK-DAG: mpy %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
238; CHECK-DAG: mpymu %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
239define i64 @mulu64(i32 %a, i32 %b) nounwind {
240  %a64 = zext i32 %a to i64
241  %b64 = zext i32 %b to i64
242  %v = mul i64 %a64, %b64
243  ret i64 %v
244}
245
246; CHECK-LABEL: muls64
247; CHECK-DAG: mpy %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
248; CHECK-DAG: mpym %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
249define i64 @muls64(i32 %a, i32 %b) nounwind {
250  %a64 = sext i32 %a to i64
251  %b64 = sext i32 %b to i64
252  %v = mul i64 %a64, %b64
253  ret i64 %v
254}
255
256