1; Check that [sl]dc1 are normally emitted. MIPS32r2 should have [sl]dxc1 too. 2; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | \ 3; RUN: FileCheck %s -check-prefixes=ALL,32R1-LDC1 4; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | \ 5; RUN: FileCheck %s -check-prefixes=ALL,32R2-LDXC1 6; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | \ 7; RUN: FileCheck %s -check-prefixes=ALL,32R6-LDC1 8; RUN: llc -march=mipsel -mcpu=mips32r3 -mattr=+micromips \ 9; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MM 10; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \ 11; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MM 12 13; Check that -mno-ldc1-sdc1 disables [sl]dc1 14; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \ 15; RUN: -mcpu=mips32 < %s | \ 16; RUN: FileCheck %s -check-prefixes=ALL,32R1,32R1-LE,32R1-LE-PIC 17; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \ 18; RUN: -mcpu=mips32r2 < %s | \ 19; RUN: FileCheck %s -check-prefixes=ALL,32R2,32R2-LE,32R2-LE-PIC 20; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \ 21; RUN: -mcpu=mips32r6 < %s | \ 22; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-LE,32R6-LE-PIC 23; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \ 24; RUN: -mattr=+micromips < %s | \ 25; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-LE-PIC 26; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \ 27; RUN: -mattr=+micromips < %s | \ 28; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-LE-PIC 29 30; Check again for big-endian 31; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \ 32; RUN: -mcpu=mips32 < %s | \ 33; RUN: FileCheck %s -check-prefixes=ALL,32R1,32R1-BE,32R1-BE-PIC 34; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \ 35; RUN: -mcpu=mips32r2 < %s | \ 36; RUN: FileCheck %s -check-prefixes=ALL,32R2,32R2-BE,32R2-BE-PIC 37; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \ 38; RUN: -mcpu=mips32r6 < %s | \ 39; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-BE,32R6-BE-PIC 40; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \ 41; RUN: -mattr=+micromips < %s | \ 42; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-BE-PIC 43; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \ 44; RUN: -mattr=+micromips < %s | \ 45; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-BE-PIC 46 47; Check again for the static relocation model 48; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \ 49; RUN: -mcpu=mips32 < %s | \ 50; RUN: FileCheck %s -check-prefixes=ALL,32R1,32R1-LE,32R1-LE-STATIC 51; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \ 52; RUN: -mcpu=mips32r2 < %s | \ 53; RUN: FileCheck %s -check-prefixes=ALL,32R2,32R2-LE,32R2-LE-STATIC 54; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \ 55; RUN: -mcpu=mips32r6 < %s | \ 56; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-LE,32R6-LE-STATIC 57; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r3 \ 58; RUN: -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC-PIC 59; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \ 60; RUN: -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC-PIC 61 62@g0 = common global double 0.000000e+00, align 8 63 64; ALL-LABEL: test_ldc1: 65 66; 32R1-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 67; 32R1-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 68; 32R1-LE-PIC-DAG: mtc1 $[[R0]], $f0 69; 32R1-LE-PIC-DAG: mtc1 $[[R1]], $f1 70 71; 32R2-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 72; 32R2-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 73; 32R2-LE-PIC-DAG: mtc1 $[[R0]], $f0 74; 32R2-LE-PIC-DAG: mthc1 $[[R1]], $f0 75 76; 32R6-LE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 77; 32R6-LE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 78; 32R6-LE-PIC-DAG: mtc1 $[[R0]], $f0 79; 32R6-LE-PIC-DAG: mthc1 $[[R1]], $f0 80 81; 32R1-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0) 82; 32R1-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]]) 83; 32R1-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0) 84; 32R1-LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]]) 85; 32R1-LE-STATIC-DAG: mtc1 $[[R1]], $f0 86; 32R1-LE-STATIC-DAG: mtc1 $[[R3]], $f1 87 88; 32R2-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0) 89; 32R2-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]]) 90; 32R2-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0) 91; 32R2-LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]]) 92; 32R2-LE-STATIC-DAG: mtc1 $[[R1]], $f0 93; 32R2-LE-STATIC-DAG: mthc1 $[[R3]], $f0 94 95; 32R6-LE-STATIC-DAG: lui $[[R0:[0-9]+]], %hi(g0) 96; 32R6-LE-STATIC-DAG: lw $[[R1:[0-9]+]], %lo(g0)($[[R0]]) 97; 32R6-LE-STATIC-DAG: addiu $[[R2:[0-9]+]], $[[R0]], %lo(g0) 98; 32R6-LE-STATIC-DAG: lw $[[R3:[0-9]+]], 4($[[R2]]) 99; 32R6-LE-STATIC-DAG: mtc1 $[[R1]], $f0 100; 32R6-LE-STATIC-DAG: mthc1 $[[R3]], $f0 101 102; 32R1-BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 103; 32R1-BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 104; 32R1-BE-PIC-DAG: mtc1 $[[R1]], $f0 105; 32R1-BE-PIC-DAG: mtc1 $[[R0]], $f1 106 107; 32R2-BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 108; 32R2-BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 109; 32R2-BE-PIC-DAG: mtc1 $[[R1]], $f0 110; 32R2-BE-PIC-DAG: mthc1 $[[R0]], $f0 111 112; 32R6-BE-PIC-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 113; 32R6-BE-PIC-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 114; 32R6-BE-PIC-DAG: mtc1 $[[R1]], $f0 115; 32R6-BE-PIC-DAG: mthc1 $[[R0]], $f0 116 117; 32R1-LDC1: ldc1 $f0, 0(${{[0-9]+}}) 118 119; 32R2-LDXC1: ldc1 $f0, 0(${{[0-9]+}}) 120 121; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}}) 122 123; MM: lui $[[R0:[0-9]+]], %hi(_gp_disp) 124; MM: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) 125; MM: addu $[[R2:[0-9]+]], $[[R1]], $25 126; MM: lw $[[R3:[0-9]+]], %got(g0)($[[R2]]) 127; MM: ldc1 $f0, 0($[[R3]]) 128 129; MM-MNO-PIC: lui $[[R0:[0-9]+]], %hi(_gp_disp) 130; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) 131; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25 132; MM-MNO-PIC: lw $[[R3:[0-9]+]], %got(g0)($[[R2]]) 133; MM-MNO-PIC-DAG: lw16 $[[R4:[0-9]+]], 0($[[R3]]) 134; MM-MNO-PIC-DAG: lw16 $[[R5:[0-9]+]], 4($[[R3]]) 135; MM-MNO-LE-PIC-DAG: mtc1 $[[R4]], $f0 136; MM-MNO-LE-PIC-DAG: mthc1 $[[R5]], $f0 137; MM-MNO-BE-PIC-DAG: mtc1 $[[R5]], $f0 138; MM-MNO-BE-PIC-DAG: mthc1 $[[R4]], $f0 139 140; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0) 141; MM-STATIC-PIC: ldc1 $f0, %lo(g0)($[[R0]]) 142 143define double @test_ldc1() { 144entry: 145 %0 = load double, double* @g0, align 8 146 ret double %0 147} 148 149; ALL-LABEL: test_sdc1: 150 151; 32R1-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 152; 32R1-LE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13 153; 32R1-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}}) 154; 32R1-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}}) 155 156; 32R2-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 157; 32R2-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 158; 32R2-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}}) 159; 32R2-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}}) 160 161; 32R6-LE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 162; 32R6-LE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 163; 32R6-LE-PIC-DAG: sw $[[R0]], 0(${{[0-9]+}}) 164; 32R6-LE-PIC-DAG: sw $[[R1]], 4(${{[0-9]+}}) 165 166; 32R1-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 167; 32R1-LE-STATIC-DAG: mfc1 $[[R1:[0-9]+]], $f13 168; 32R1-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0) 169; 32R1-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]]) 170; 32R1-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0) 171; 32R1-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]]) 172 173; 32R2-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 174; 32R2-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 175; 32R2-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0) 176; 32R2-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]]) 177; 32R2-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0) 178; 32R2-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]]) 179 180; 32R6-LE-STATIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 181; 32R6-LE-STATIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 182; 32R6-LE-STATIC-DAG: lui $[[R2:[0-9]+]], %hi(g0) 183; 32R6-LE-STATIC-DAG: sw $[[R0]], %lo(g0)($[[R2]]) 184; 32R6-LE-STATIC-DAG: addiu $[[R3:[0-9]+]], $[[R2]], %lo(g0) 185; 32R6-LE-STATIC-DAG: sw $[[R1]], 4($[[R3]]) 186 187; 32R1-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 188; 32R1-BE-PIC-DAG: mfc1 $[[R1:[0-9]+]], $f13 189; 32R1-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}}) 190; 32R1-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}}) 191 192; 32R2-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 193; 32R2-BE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 194; 32R2-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}}) 195; 32R2-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}}) 196 197; 32R6-BE-PIC-DAG: mfc1 $[[R0:[0-9]+]], $f12 198; 32R6-BE-PIC-DAG: mfhc1 $[[R1:[0-9]+]], $f12 199; 32R6-BE-PIC-DAG: sw $[[R1]], 0(${{[0-9]+}}) 200; 32R6-BE-PIC-DAG: sw $[[R0]], 4(${{[0-9]+}}) 201 202; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) 203 204; 32R2-LDXC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) 205 206; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) 207 208; MM: lui $[[R0:[0-9]+]], %hi(_gp_disp) 209; MM: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) 210; MM: addu $[[R2:[0-9]+]], $[[R1]], $25 211; MM: lw $[[R3:[0-9]+]], %got(g0)($[[R2]]) 212; MM: sdc1 $f12, 0($[[R3]]) 213 214; MM-MNO-PIC: lui $[[R0:[0-9]+]], %hi(_gp_disp) 215; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) 216; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25 217; MM-MNO-LE-PIC-DAG: mfc1 $[[R3:[0-9]+]], $f12 218; MM-MNO-BE-PIC-DAG: mfhc1 $[[R3:[0-9]+]], $f12 219; MM-MNO-PIC-DAG: lw $[[R4:[0-9]+]], %got(g0)($[[R2]]) 220; MM-MNO-PIC-DAG: sw16 $[[R3]], 0($[[R4]]) 221; MM-MNO-LE-PIC-DAG: mfhc1 $[[R5:[0-9]+]], $f12 222; MM-MNO-BE-PIC-DAG: mfc1 $[[R5:[0-9]+]], $f12 223; MM-MNO-PIC-DAG: sw16 $[[R5]], 4($[[R4]]) 224 225; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0) 226; MM-STATIC-PIC: sdc1 $f12, %lo(g0)($[[R0]]) 227 228define void @test_sdc1(double %a) { 229entry: 230 store double %a, double* @g0, align 8 231 ret void 232} 233 234; ALL-LABEL: test_ldxc1: 235 236; 32R1-LE-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 237; 32R1-LE-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 238; 32R1-BE-DAG: lw $[[R0:[0-9]+]], 4(${{[0-9]+}}) 239; 32R1-BE-DAG: lw $[[R1:[0-9]+]], 0(${{[0-9]+}}) 240; 32R1-DAG: mtc1 $[[R0]], $f0 241; 32R1-DAG: mtc1 $[[R1]], $f1 242 243; 32R2-LE-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 244; 32R2-LE-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 245; 32R2-BE-DAG: lw $[[R0:[0-9]+]], 4(${{[0-9]+}}) 246; 32R2-BE-DAG: lw $[[R1:[0-9]+]], 0(${{[0-9]+}}) 247; 32R2-DAG: mtc1 $[[R0]], $f0 248; 32R2-DAG: mthc1 $[[R1]], $f0 249 250; 32R6-LE-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 251; 32R6-LE-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 252; 32R6-BE-DAG: lw $[[R0:[0-9]+]], 4(${{[0-9]+}}) 253; 32R6-BE-DAG: lw $[[R1:[0-9]+]], 0(${{[0-9]+}}) 254; 32R6-DAG: mtc1 $[[R0]], $f0 255; 32R6-DAG: mthc1 $[[R1]], $f0 256 257; 32R1-LDC1: ldc1 $f0, 0(${{[0-9]+}}) 258 259; 32R2-LDXC1: sll $[[OFFSET:[0-9]+]], $5, 3 260; 32R2-LDXC1: ldxc1 $f0, $[[OFFSET]]($4) 261 262; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}}) 263 264; MM: sll16 $[[R0:[0-9]+]], $5, 3 265; MM: addu16 $[[R1:[0-9]+]], $4, $[[R0]] 266; MM: ldc1 $f0, 0($[[R1]]) 267 268; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $5, 3 269; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $4, $[[R0]] 270; MM-MNO-PIC-DAG: lw16 $[[R2:[0-9]+]], 0($[[R1]]) 271; MM-MNO-PIC-DAG: lw16 $[[R3:[0-9]+]], 4($[[R1]]) 272; MM-MNO-LE-PIC: mtc1 $[[R2]], $f0 273; MM-MNO-LE-PIC: mthc1 $[[R3]], $f0 274; MM-MNO-BE-PIC: mtc1 $[[R3]], $f0 275; MM-MNO-BE-PIC: mthc1 $[[R2]], $f0 276 277; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $5, 3 278; MM-STATIC-PIC: addu16 $[[R1:[0-9]+]], $4, $[[R0]] 279; MM-STATIC-PIC: ldc1 $f0, 0($[[R1]]) 280 281define double @test_ldxc1(double* nocapture readonly %a, i32 %i) { 282entry: 283 %arrayidx = getelementptr inbounds double, double* %a, i32 %i 284 %0 = load double, double* %arrayidx, align 8 285 ret double %0 286} 287 288; ALL-LABEL: test_sdxc1: 289 290; 32R1-DAG: mfc1 $[[R0:[0-9]+]], $f12 291; 32R1-DAG: mfc1 $[[R1:[0-9]+]], $f13 292; 32R1-DAG: sw $[[R0]], 0(${{[0-9]+}}) 293; 32R1-DAG: sw $[[R1]], 4(${{[0-9]+}}) 294 295; 32R2-DAG: mfc1 $[[R0:[0-9]+]], $f12 296; 32R2-DAG: mfhc1 $[[R1:[0-9]+]], $f12 297; 32R2-DAG: sw $[[R0]], 0(${{[0-9]+}}) 298; 32R2-DAG: sw $[[R1]], 4(${{[0-9]+}}) 299 300; 32R6-DAG: mfc1 $[[R0:[0-9]+]], $f12 301; 32R6-DAG: mfhc1 $[[R1:[0-9]+]], $f12 302; 32R6-DAG: sw $[[R0]], 0(${{[0-9]+}}) 303; 32R6-DAG: sw $[[R1]], 4(${{[0-9]+}}) 304 305; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) 306 307; 32R2-LDXC1: sll $[[OFFSET:[0-9]+]], $7, 3 308; 32R2-LDXC1: sdxc1 $f{{[0-9]+}}, $[[OFFSET]]($6) 309 310; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) 311 312; MM: sll16 $[[R0:[0-9]+]], $7, 3 313; MM: addu16 $[[R1:[0-9]+]], $6, $[[R0]] 314; MM: sdc1 $f12, 0($[[R1]]) 315 316; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $7, 3 317; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]] 318; MM-MNO-LE-PIC-DAG: mfc1 $[[R2:[0-9]+]], $f12 319; MM-MNO-BE-PIC-DAG: mfhc1 $[[R2:[0-9]+]], $f12 320; MM-MNO-PIC-DAG: sw16 $[[R2]], 0($[[R1]]) 321; MM-MNO-LE-PIC-DAG: mfhc1 $[[R3:[0-9]+]], $f12 322; MM-MNO-BE-PIC-DAG: mfc1 $[[R3:[0-9]+]], $f12 323; MM-MNO-PIC-DAG: sw16 $[[R3]], 4($[[R1]]) 324 325; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $7, 3 326; MM-STATIC-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]] 327; MM-STATIC-PIC: sdc1 $f12, 0($[[R1]]) 328 329define void @test_sdxc1(double %b, double* nocapture %a, i32 %i) { 330entry: 331 %arrayidx = getelementptr inbounds double, double* %a, i32 %i 332 store double %b, double* %arrayidx, align 8 333 ret void 334} 335