1; Test the absence of the andi.b / and.v instructions 2 3; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s 4; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s 5 6@llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 7@llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 8@llvm_mips_bclr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 9 10define void @llvm_mips_bclr_b_test() nounwind { 11entry: 12 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bclr_b_ARG1 13 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bclr_b_ARG2 14 %2 = tail call <16 x i8> @llvm.mips.bclr.b(<16 x i8> %0, <16 x i8> %1) 15 store <16 x i8> %2, <16 x i8>* @llvm_mips_bclr_b_RES 16 ret void 17} 18 19declare <16 x i8> @llvm.mips.bclr.b(<16 x i8>, <16 x i8>) nounwind 20 21; CHECK-LABEL: llvm_mips_bclr_b_test: 22; CHECK-NOT: andi.b 23; CHECK: bclr.b 24 25@llvm_mips_bclr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 26@llvm_mips_bclr_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 27@llvm_mips_bclr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 28 29define void @llvm_mips_bclr_h_test() nounwind { 30entry: 31 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bclr_h_ARG1 32 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_bclr_h_ARG2 33 %2 = tail call <8 x i16> @llvm.mips.bclr.h(<8 x i16> %0, <8 x i16> %1) 34 store <8 x i16> %2, <8 x i16>* @llvm_mips_bclr_h_RES 35 ret void 36} 37 38declare <8 x i16> @llvm.mips.bclr.h(<8 x i16>, <8 x i16>) nounwind 39 40; CHECK-LABEL: llvm_mips_bclr_h_test: 41; CHECK-NOT: and.v 42; CHECK: bclr.h 43 44@llvm_mips_bclr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 45@llvm_mips_bclr_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 46@llvm_mips_bclr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 47 48define void @llvm_mips_bclr_w_test() nounwind { 49entry: 50 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bclr_w_ARG1 51 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_bclr_w_ARG2 52 %2 = tail call <4 x i32> @llvm.mips.bclr.w(<4 x i32> %0, <4 x i32> %1) 53 store <4 x i32> %2, <4 x i32>* @llvm_mips_bclr_w_RES 54 ret void 55} 56 57declare <4 x i32> @llvm.mips.bclr.w(<4 x i32>, <4 x i32>) nounwind 58 59; CHECK-LABEL: llvm_mips_bclr_w_test: 60; CHECK-NOT: and.v 61; CHECK: bclr.w 62 63@llvm_mips_bclr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 64@llvm_mips_bclr_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 65@llvm_mips_bclr_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 66 67define void @llvm_mips_bclr_d_test() nounwind { 68entry: 69 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bclr_d_ARG1 70 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_bclr_d_ARG2 71 %2 = tail call <2 x i64> @llvm.mips.bclr.d(<2 x i64> %0, <2 x i64> %1) 72 store <2 x i64> %2, <2 x i64>* @llvm_mips_bclr_d_RES 73 ret void 74} 75 76declare <2 x i64> @llvm.mips.bclr.d(<2 x i64>, <2 x i64>) nounwind 77 78; CHECK-LABEL: llvm_mips_bclr_d_test: 79; CHECK-NOT: and.v 80; CHECK: bclr.d 81 82@llvm_mips_bneg_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 83@llvm_mips_bneg_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 84@llvm_mips_bneg_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 85 86define void @llvm_mips_bneg_b_test() nounwind { 87entry: 88 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bneg_b_ARG1 89 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bneg_b_ARG2 90 %2 = tail call <16 x i8> @llvm.mips.bneg.b(<16 x i8> %0, <16 x i8> %1) 91 store <16 x i8> %2, <16 x i8>* @llvm_mips_bneg_b_RES 92 ret void 93} 94 95declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind 96 97; CHECK-LABEL: llvm_mips_bneg_b_test: 98; CHECK-NOT: andi.b 99; CHECK: bneg.b 100 101@llvm_mips_bneg_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 102@llvm_mips_bneg_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 103@llvm_mips_bneg_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 104 105define void @llvm_mips_bneg_h_test() nounwind { 106entry: 107 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bneg_h_ARG1 108 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_bneg_h_ARG2 109 %2 = tail call <8 x i16> @llvm.mips.bneg.h(<8 x i16> %0, <8 x i16> %1) 110 store <8 x i16> %2, <8 x i16>* @llvm_mips_bneg_h_RES 111 ret void 112} 113 114declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind 115 116; CHECK-LABEL: llvm_mips_bneg_h_test: 117; CHECK-NOT: and.v 118; CHECK: bneg.h 119 120@llvm_mips_bneg_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 121@llvm_mips_bneg_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 122@llvm_mips_bneg_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 123 124define void @llvm_mips_bneg_w_test() nounwind { 125entry: 126 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bneg_w_ARG1 127 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_bneg_w_ARG2 128 %2 = tail call <4 x i32> @llvm.mips.bneg.w(<4 x i32> %0, <4 x i32> %1) 129 store <4 x i32> %2, <4 x i32>* @llvm_mips_bneg_w_RES 130 ret void 131} 132 133declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind 134 135; CHECK-LABEL: llvm_mips_bneg_w_test: 136; CHECK-NOT: and.v 137; CHECK: bneg.w 138 139@llvm_mips_bneg_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 140@llvm_mips_bneg_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 141@llvm_mips_bneg_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 142 143define void @llvm_mips_bneg_d_test() nounwind { 144entry: 145 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bneg_d_ARG1 146 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_bneg_d_ARG2 147 %2 = tail call <2 x i64> @llvm.mips.bneg.d(<2 x i64> %0, <2 x i64> %1) 148 store <2 x i64> %2, <2 x i64>* @llvm_mips_bneg_d_RES 149 ret void 150} 151 152declare <2 x i64> @llvm.mips.bneg.d(<2 x i64>, <2 x i64>) nounwind 153 154; CHECK-LABEL: llvm_mips_bneg_d_test: 155; CHECK-NOT: and.v 156; CHECK: bneg.d 157 158@llvm_mips_bset_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 159@llvm_mips_bset_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 160@llvm_mips_bset_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 161 162define void @llvm_mips_bset_b_test() nounwind { 163entry: 164 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bset_b_ARG1 165 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bset_b_ARG2 166 %2 = tail call <16 x i8> @llvm.mips.bset.b(<16 x i8> %0, <16 x i8> %1) 167 store <16 x i8> %2, <16 x i8>* @llvm_mips_bset_b_RES 168 ret void 169} 170 171declare <16 x i8> @llvm.mips.bset.b(<16 x i8>, <16 x i8>) nounwind 172 173; CHECK-LABEL: llvm_mips_bset_b_test: 174; CHECK-NOT: andi.b 175; CHECK: bset.b 176 177@llvm_mips_bset_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 178@llvm_mips_bset_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 179@llvm_mips_bset_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 180 181define void @llvm_mips_bset_h_test() nounwind { 182entry: 183 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_bset_h_ARG1 184 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_bset_h_ARG2 185 %2 = tail call <8 x i16> @llvm.mips.bset.h(<8 x i16> %0, <8 x i16> %1) 186 store <8 x i16> %2, <8 x i16>* @llvm_mips_bset_h_RES 187 ret void 188} 189 190declare <8 x i16> @llvm.mips.bset.h(<8 x i16>, <8 x i16>) nounwind 191 192; CHECK-LABEL: llvm_mips_bset_h_test: 193; CHECK-NOT: and.v 194; CHECK: bset.h 195 196@llvm_mips_bset_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 197@llvm_mips_bset_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 198@llvm_mips_bset_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 199 200define void @llvm_mips_bset_w_test() nounwind { 201entry: 202 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_bset_w_ARG1 203 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_bset_w_ARG2 204 %2 = tail call <4 x i32> @llvm.mips.bset.w(<4 x i32> %0, <4 x i32> %1) 205 store <4 x i32> %2, <4 x i32>* @llvm_mips_bset_w_RES 206 ret void 207} 208 209declare <4 x i32> @llvm.mips.bset.w(<4 x i32>, <4 x i32>) nounwind 210 211; CHECK-LABEL: llvm_mips_bset_w_test: 212; CHECK-NOT: and.v 213; CHECK: bset.w 214 215@llvm_mips_bset_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 216@llvm_mips_bset_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 217@llvm_mips_bset_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 218 219define void @llvm_mips_bset_d_test() nounwind { 220entry: 221 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_bset_d_ARG1 222 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_bset_d_ARG2 223 %2 = tail call <2 x i64> @llvm.mips.bset.d(<2 x i64> %0, <2 x i64> %1) 224 store <2 x i64> %2, <2 x i64>* @llvm_mips_bset_d_RES 225 ret void 226} 227 228declare <2 x i64> @llvm.mips.bset.d(<2 x i64>, <2 x i64>) nounwind 229 230; CHECK-LABEL: llvm_mips_bset_d_test: 231; CHECK-NOT: and.v 232; CHECK: bset.d 233 234@llvm_mips_sll_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 235@llvm_mips_sll_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 236@llvm_mips_sll_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 237 238define void @llvm_mips_sll_b_test() nounwind { 239entry: 240 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sll_b_ARG1 241 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sll_b_ARG2 242 %2 = tail call <16 x i8> @llvm.mips.sll.b(<16 x i8> %0, <16 x i8> %1) 243 store <16 x i8> %2, <16 x i8>* @llvm_mips_sll_b_RES 244 ret void 245} 246 247declare <16 x i8> @llvm.mips.sll.b(<16 x i8>, <16 x i8>) nounwind 248 249; CHECK-LABEL: llvm_mips_sll_b_test: 250; CHECK-NOT: andi.b 251; CHECK: sll.b 252 253@llvm_mips_sll_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 254@llvm_mips_sll_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 255@llvm_mips_sll_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 256 257define void @llvm_mips_sll_h_test() nounwind { 258entry: 259 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sll_h_ARG1 260 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sll_h_ARG2 261 %2 = tail call <8 x i16> @llvm.mips.sll.h(<8 x i16> %0, <8 x i16> %1) 262 store <8 x i16> %2, <8 x i16>* @llvm_mips_sll_h_RES 263 ret void 264} 265 266declare <8 x i16> @llvm.mips.sll.h(<8 x i16>, <8 x i16>) nounwind 267 268; CHECK-LABEL: llvm_mips_sll_h_test: 269; CHECK-NOT: and.v 270; CHECK: sll.h 271 272@llvm_mips_sll_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 273@llvm_mips_sll_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 274@llvm_mips_sll_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 275 276define void @llvm_mips_sll_w_test() nounwind { 277entry: 278 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sll_w_ARG1 279 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sll_w_ARG2 280 %2 = tail call <4 x i32> @llvm.mips.sll.w(<4 x i32> %0, <4 x i32> %1) 281 store <4 x i32> %2, <4 x i32>* @llvm_mips_sll_w_RES 282 ret void 283} 284 285declare <4 x i32> @llvm.mips.sll.w(<4 x i32>, <4 x i32>) nounwind 286 287; CHECK-LABEL: llvm_mips_sll_w_test: 288; CHECK-NOT: and.v 289; CHECK: sll.w 290 291@llvm_mips_sll_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 292@llvm_mips_sll_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 293@llvm_mips_sll_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 294 295define void @llvm_mips_sll_d_test() nounwind { 296entry: 297 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sll_d_ARG1 298 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sll_d_ARG2 299 %2 = tail call <2 x i64> @llvm.mips.sll.d(<2 x i64> %0, <2 x i64> %1) 300 store <2 x i64> %2, <2 x i64>* @llvm_mips_sll_d_RES 301 ret void 302} 303 304declare <2 x i64> @llvm.mips.sll.d(<2 x i64>, <2 x i64>) nounwind 305 306; CHECK-LABEL: llvm_mips_sll_d_test: 307; CHECK-NOT: and.v 308; CHECK: sll.d 309 310@llvm_mips_sra_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 311@llvm_mips_sra_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 312@llvm_mips_sra_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 313 314define void @llvm_mips_sra_b_test() nounwind { 315entry: 316 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_sra_b_ARG1 317 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_sra_b_ARG2 318 %2 = tail call <16 x i8> @llvm.mips.sra.b(<16 x i8> %0, <16 x i8> %1) 319 store <16 x i8> %2, <16 x i8>* @llvm_mips_sra_b_RES 320 ret void 321} 322 323declare <16 x i8> @llvm.mips.sra.b(<16 x i8>, <16 x i8>) nounwind 324 325; CHECK-LABEL: llvm_mips_sra_b_test: 326; CHECK-NOT: andi.b 327; CHECK: sra.b 328 329@llvm_mips_sra_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 330@llvm_mips_sra_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 331@llvm_mips_sra_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 332 333define void @llvm_mips_sra_h_test() nounwind { 334entry: 335 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_sra_h_ARG1 336 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_sra_h_ARG2 337 %2 = tail call <8 x i16> @llvm.mips.sra.h(<8 x i16> %0, <8 x i16> %1) 338 store <8 x i16> %2, <8 x i16>* @llvm_mips_sra_h_RES 339 ret void 340} 341 342declare <8 x i16> @llvm.mips.sra.h(<8 x i16>, <8 x i16>) nounwind 343 344; CHECK-LABEL: llvm_mips_sra_h_test: 345; CHECK-NOT: and.v 346; CHECK: sra.h 347 348@llvm_mips_sra_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 349@llvm_mips_sra_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 350@llvm_mips_sra_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 351 352define void @llvm_mips_sra_w_test() nounwind { 353entry: 354 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_sra_w_ARG1 355 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_sra_w_ARG2 356 %2 = tail call <4 x i32> @llvm.mips.sra.w(<4 x i32> %0, <4 x i32> %1) 357 store <4 x i32> %2, <4 x i32>* @llvm_mips_sra_w_RES 358 ret void 359} 360 361declare <4 x i32> @llvm.mips.sra.w(<4 x i32>, <4 x i32>) nounwind 362 363; CHECK-LABEL: llvm_mips_sra_w_test: 364; CHECK-NOT: and.v 365; CHECK: sra.w 366 367@llvm_mips_sra_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 368@llvm_mips_sra_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 369@llvm_mips_sra_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 370 371define void @llvm_mips_sra_d_test() nounwind { 372entry: 373 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_sra_d_ARG1 374 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_sra_d_ARG2 375 %2 = tail call <2 x i64> @llvm.mips.sra.d(<2 x i64> %0, <2 x i64> %1) 376 store <2 x i64> %2, <2 x i64>* @llvm_mips_sra_d_RES 377 ret void 378} 379 380declare <2 x i64> @llvm.mips.sra.d(<2 x i64>, <2 x i64>) nounwind 381 382; CHECK-LABEL: llvm_mips_sra_d_test: 383; CHECK-NOT: and.v 384; CHECK: sra.d 385 386@llvm_mips_srl_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 387@llvm_mips_srl_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 388@llvm_mips_srl_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 389 390define void @llvm_mips_srl_b_test() nounwind { 391entry: 392 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_srl_b_ARG1 393 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_srl_b_ARG2 394 %2 = tail call <16 x i8> @llvm.mips.srl.b(<16 x i8> %0, <16 x i8> %1) 395 store <16 x i8> %2, <16 x i8>* @llvm_mips_srl_b_RES 396 ret void 397} 398 399declare <16 x i8> @llvm.mips.srl.b(<16 x i8>, <16 x i8>) nounwind 400 401; CHECK-LABEL: llvm_mips_srl_b_test: 402; CHECK-NOT: andi.b 403; CHECK: srl.b 404 405@llvm_mips_srl_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 406@llvm_mips_srl_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16 407@llvm_mips_srl_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 408 409define void @llvm_mips_srl_h_test() nounwind { 410entry: 411 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_srl_h_ARG1 412 %1 = load <8 x i16>, <8 x i16>* @llvm_mips_srl_h_ARG2 413 %2 = tail call <8 x i16> @llvm.mips.srl.h(<8 x i16> %0, <8 x i16> %1) 414 store <8 x i16> %2, <8 x i16>* @llvm_mips_srl_h_RES 415 ret void 416} 417 418declare <8 x i16> @llvm.mips.srl.h(<8 x i16>, <8 x i16>) nounwind 419 420; CHECK-LABEL: llvm_mips_srl_h_test: 421; CHECK-NOT: and.v 422; CHECK: srl.h 423 424@llvm_mips_srl_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 425@llvm_mips_srl_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 426@llvm_mips_srl_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 427 428define void @llvm_mips_srl_w_test() nounwind { 429entry: 430 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_srl_w_ARG1 431 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_srl_w_ARG2 432 %2 = tail call <4 x i32> @llvm.mips.srl.w(<4 x i32> %0, <4 x i32> %1) 433 store <4 x i32> %2, <4 x i32>* @llvm_mips_srl_w_RES 434 ret void 435} 436 437declare <4 x i32> @llvm.mips.srl.w(<4 x i32>, <4 x i32>) nounwind 438 439; CHECK-LABEL: llvm_mips_srl_w_test: 440; CHECK-NOT: and.v 441; CHECK: srl.w 442 443@llvm_mips_srl_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16 444@llvm_mips_srl_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 445@llvm_mips_srl_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 446 447define void @llvm_mips_srl_d_test() nounwind { 448entry: 449 %0 = load <2 x i64>, <2 x i64>* @llvm_mips_srl_d_ARG1 450 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_srl_d_ARG2 451 %2 = tail call <2 x i64> @llvm.mips.srl.d(<2 x i64> %0, <2 x i64> %1) 452 store <2 x i64> %2, <2 x i64>* @llvm_mips_srl_d_RES 453 ret void 454} 455 456declare <2 x i64> @llvm.mips.srl.d(<2 x i64>, <2 x i64>) nounwind 457 458; CHECK-LABEL: llvm_mips_srl_d_test: 459; CHECK-NOT: and.v 460; CHECK: srl.d 461