1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,BE 3; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s --check-prefixes=CHECK,BE 4; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,LE 5 6define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { 7; BE-LABEL: test1: 8; BE: # %bb.0: 9; BE-NEXT: lxvw4x 0, 0, 3 10; BE-NEXT: vspltisb 2, -1 11; BE-NEXT: vslw 2, 2, 2 12; BE-NEXT: xxland 0, 0, 34 13; BE-NEXT: stxvw4x 0, 0, 3 14; BE-NEXT: lxvw4x 0, 0, 4 15; BE-NEXT: xxlandc 0, 0, 34 16; BE-NEXT: stxvw4x 0, 0, 4 17; BE-NEXT: lxvw4x 0, 0, 5 18; BE-NEXT: xvabssp 0, 0 19; BE-NEXT: stxvw4x 0, 0, 5 20; BE-NEXT: blr 21; 22; LE-LABEL: test1: 23; LE: # %bb.0: 24; LE-NEXT: lvx 2, 0, 3 25; LE-NEXT: vspltisb 3, -1 26; LE-NEXT: vslw 3, 3, 3 27; LE-NEXT: xxland 34, 34, 35 28; LE-NEXT: stvx 2, 0, 3 29; LE-NEXT: lvx 2, 0, 4 30; LE-NEXT: xxlandc 34, 34, 35 31; LE-NEXT: stvx 2, 0, 4 32; LE-NEXT: lvx 2, 0, 5 33; LE-NEXT: xvabssp 34, 34 34; LE-NEXT: stvx 2, 0, 5 35; LE-NEXT: blr 36 %tmp = load <4 x i32>, <4 x i32>* %P1 ; <<4 x i32>> [#uses=1] 37 %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1] 38 store <4 x i32> %tmp4, <4 x i32>* %P1 39 %tmp7 = load <4 x i32>, <4 x i32>* %P2 ; <<4 x i32>> [#uses=1] 40 %tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1] 41 store <4 x i32> %tmp9, <4 x i32>* %P2 42 %tmp.upgrd.1 = load <4 x float>, <4 x float>* %P3 ; <<4 x float>> [#uses=1] 43 %tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32> ; <<4 x i32>> [#uses=1] 44 %tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1] 45 %tmp13 = bitcast <4 x i32> %tmp12 to <4 x float> ; <<4 x float>> [#uses=1] 46 store <4 x float> %tmp13, <4 x float>* %P3 47 ret void 48 49} 50 51define <4 x i32> @test_30() nounwind { 52; CHECK-LABEL: test_30: 53; CHECK: # %bb.0: 54; CHECK-NEXT: vspltisw 2, 15 55; CHECK-NEXT: vadduwm 2, 2, 2 56; CHECK-NEXT: blr 57 ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 > 58} 59 60define <4 x i32> @test_29() nounwind { 61; CHECK-LABEL: test_29: 62; CHECK: # %bb.0: 63; CHECK-NEXT: vspltisw 3, -16 64; CHECK-NEXT: vspltisw 2, 13 65; CHECK-NEXT: vsubuwm 2, 2, 3 66; CHECK-NEXT: blr 67 ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 > 68} 69 70define <8 x i16> @test_n30() nounwind { 71; CHECK-LABEL: test_n30: 72; CHECK: # %bb.0: 73; CHECK-NEXT: vspltish 2, -15 74; CHECK-NEXT: vadduhm 2, 2, 2 75; CHECK-NEXT: blr 76 ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 > 77} 78 79define <16 x i8> @test_n104() nounwind { 80; CHECK-LABEL: test_n104: 81; CHECK: # %bb.0: 82; CHECK-NEXT: vspltisb 2, -13 83; CHECK-NEXT: vslb 2, 2, 2 84; CHECK-NEXT: blr 85 ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 > 86} 87 88define <4 x i32> @test_vsldoi() nounwind { 89; CHECK-LABEL: test_vsldoi: 90; CHECK: # %bb.0: 91; CHECK-NEXT: vspltisw 2, 2 92; CHECK-NEXT: vsldoi 2, 2, 2, 1 93; CHECK-NEXT: blr 94 ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 > 95} 96 97define <8 x i16> @test_vsldoi_65023() nounwind { 98; CHECK-LABEL: test_vsldoi_65023: 99; CHECK: # %bb.0: 100; CHECK-NEXT: vspltish 2, -3 101; CHECK-NEXT: vsldoi 2, 2, 2, 1 102; CHECK-NEXT: blr 103 ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 > 104} 105 106define <4 x i32> @test_vsldoi_x16() nounwind { 107; CHECK-LABEL: test_vsldoi_x16: 108; CHECK: # %bb.0: 109; CHECK-NEXT: vspltisw 2, -3 110; CHECK-NEXT: vsldoi 2, 2, 2, 2 111; CHECK-NEXT: blr 112 ret <4 x i32> <i32 -131073, i32 -131073, i32 -131073, i32 -131073> 113} 114 115define <4 x i32> @test_vsldoi_x24() nounwind { 116; CHECK-LABEL: test_vsldoi_x24: 117; CHECK: # %bb.0: 118; CHECK-NEXT: vspltisw 2, -3 119; CHECK-NEXT: vsldoi 2, 2, 2, 3 120; CHECK-NEXT: blr 121 ret <4 x i32> <i32 -33554433, i32 -33554433, i32 -33554433, i32 -33554433> 122} 123 124define <4 x i32> @test_rol() nounwind { 125; CHECK-LABEL: test_rol: 126; CHECK: # %bb.0: 127; CHECK-NEXT: vspltisw 2, -12 128; CHECK-NEXT: vrlw 2, 2, 2 129; CHECK-NEXT: blr 130 ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 > 131} 132