1# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z15 -start-before=greedy %s -o - \
2# RUN:   | FileCheck %s
3#
4# Test that regalloc manages (via regalloc hints) to avoid a LOCRMux jump
5# sequence expansion, and a SELR/LOCR instuction is emitted.
6
7--- |
8  ; ModuleID = 'tc.ll'
9  source_filename = "tc.ll"
10  target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
11
12  @globvar = external global i32
13
14  declare void @fun() #0
15
16  define void @fun1() #0 {
17  bb5:
18    br label %bb6
19
20  bb6:                                              ; preds = %bb33, %bb5
21    %tmp = phi i1 [ %tmp34, %bb33 ], [ undef, %bb5 ]
22    br label %bb7
23
24  bb7:                                              ; preds = %bb7, %bb6
25    %lsr.iv1 = phi [512 x i32]* [ %0, %bb7 ], [ undef, %bb6 ]
26    %tmp8 = phi i32 [ %tmp27, %bb7 ], [ -1000000, %bb6 ]
27    %tmp9 = phi i64 [ %tmp28, %bb7 ], [ 0, %bb6 ]
28    %lsr3 = trunc i64 %tmp9 to i32
29    %lsr.iv12 = bitcast [512 x i32]* %lsr.iv1 to i32*
30    %tmp11 = load i32, i32* %lsr.iv12
31    %tmp12 = icmp sgt i32 %tmp11, undef
32    %tmp13 = trunc i64 %tmp9 to i32
33    %tmp14 = select i1 %tmp12, i32 %lsr3, i32 0
34    %tmp15 = select i1 %tmp12, i32 %tmp13, i32 %tmp8
35    %tmp16 = load i32, i32* undef
36    %tmp17 = select i1 false, i32 undef, i32 %tmp14
37    %tmp18 = select i1 false, i32 undef, i32 %tmp15
38    %tmp19 = select i1 false, i32 %tmp16, i32 undef
39    %tmp20 = select i1 undef, i32 undef, i32 %tmp17
40    %tmp21 = select i1 undef, i32 undef, i32 %tmp18
41    %tmp22 = select i1 undef, i32 undef, i32 %tmp19
42    %tmp23 = or i64 %tmp9, 3
43    %tmp24 = icmp sgt i32 undef, %tmp22
44    %tmp25 = trunc i64 %tmp23 to i32
45    %tmp26 = select i1 %tmp24, i32 %tmp25, i32 %tmp20
46    %tmp27 = select i1 %tmp24, i32 %tmp25, i32 %tmp21
47    %tmp28 = add nuw nsw i64 %tmp9, 4
48    %tmp29 = icmp eq i64 undef, 0
49    %scevgep = getelementptr [512 x i32], [512 x i32]* %lsr.iv1, i64 0, i64 4
50    %0 = bitcast i32* %scevgep to [512 x i32]*
51    br i1 %tmp29, label %bb30, label %bb7
52
53  bb30:                                             ; preds = %bb7
54    %tmp32 = icmp sgt i32 %tmp27, -1000000
55    br i1 %tmp32, label %bb33, label %bb35
56
57  bb33:                                             ; preds = %bb30
58    call void @fun()
59    store i32 %tmp26, i32* @globvar
60    %tmp34 = icmp ugt i32 undef, 1
61    br label %bb6
62
63  bb35:                                             ; preds = %bb30
64    br i1 %tmp, label %bb37, label %bb38
65
66  bb37:                                             ; preds = %bb35
67    unreachable
68
69  bb38:                                             ; preds = %bb35
70    unreachable
71  }
72
73  ; Function Attrs: nounwind
74  declare void @llvm.stackprotector(i8*, i8**) #1
75
76  attributes #0 = { "target-cpu"="z15" }
77  attributes #1 = { nounwind }
78
79...
80
81# CHECK: locr
82# CHECK-NOT: risblg
83
84---
85name:            fun1
86alignment:       16
87tracksRegLiveness: true
88registers:
89  - { id: 0, class: grx32bit }
90  - { id: 1, class: addr64bit }
91  - { id: 2, class: grx32bit }
92  - { id: 3, class: addr64bit }
93  - { id: 4, class: gr32bit }
94  - { id: 5, class: grx32bit }
95  - { id: 6, class: gr64bit }
96  - { id: 7, class: gr64bit }
97  - { id: 8, class: grx32bit }
98  - { id: 9, class: grx32bit }
99  - { id: 10, class: gr64bit }
100  - { id: 11, class: grx32bit }
101  - { id: 12, class: gr64bit }
102  - { id: 13, class: grx32bit }
103  - { id: 14, class: gr32bit }
104  - { id: 15, class: gr32bit }
105  - { id: 16, class: grx32bit }
106  - { id: 17, class: grx32bit }
107  - { id: 18, class: gr32bit }
108  - { id: 19, class: addr64bit }
109  - { id: 20, class: grx32bit }
110  - { id: 21, class: gr32bit }
111  - { id: 22, class: gr64bit }
112  - { id: 23, class: grx32bit }
113  - { id: 24, class: grx32bit }
114  - { id: 25, class: grx32bit }
115  - { id: 26, class: addr64bit }
116  - { id: 27, class: grx32bit }
117  - { id: 28, class: addr64bit }
118frameInfo:
119  hasCalls:        true
120body:             |
121  bb.0.bb5:
122    %25:grx32bit = IMPLICIT_DEF
123
124  bb.1.bb6:
125    %28:addr64bit = LGHI 0
126    %27:grx32bit = IIFMux 4293967296
127    %26:addr64bit = IMPLICIT_DEF
128
129  bb.2.bb7:
130    successors: %bb.3(0x04000000), %bb.2(0x7c000000)
131
132    %14:gr32bit = LMux %26, 0, $noreg :: (load (s32) from %ir.lsr.iv12)
133    CR %14, undef %15:gr32bit, implicit-def $cc
134    %16:grx32bit = COPY %28.subreg_l32
135    %16:grx32bit = LOCHIMux %16, 0, 14, 12, implicit $cc
136    %17:grx32bit = SELRMux %27, %28.subreg_l32, 14, 2, implicit killed $cc
137    %18:gr32bit = LMux undef %19:addr64bit, 0, $noreg :: (load (s32) from `i32* undef`)
138    %20:grx32bit = COPY %28.subreg_l32
139    %20:grx32bit = OILMux %20, 3, implicit-def dead $cc
140    CR undef %21:gr32bit, %18, implicit-def $cc
141    %4:gr32bit = SELRMux %16, %20, 14, 2, implicit $cc
142    %27:grx32bit = SELRMux %17, %20, 14, 2, implicit killed $cc
143    %28:addr64bit = nuw nsw LA %28, 4, $noreg
144    %26:addr64bit = LA %26, 16, $noreg
145    CGHI undef %22:gr64bit, 0, implicit-def $cc
146    BRC 14, 6, %bb.2, implicit killed $cc
147    J %bb.3
148
149  bb.3.bb30:
150    successors: %bb.4(0x7fffffff), %bb.5(0x00000001)
151
152    CFIMux %27, -999999, implicit-def $cc
153    BRC 14, 4, %bb.5, implicit killed $cc
154    J %bb.4
155
156  bb.4.bb33:
157    ADJCALLSTACKDOWN 0, 0
158    CallBRASL @fun, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc
159    ADJCALLSTACKUP 0, 0
160    STRL %4, @globvar :: (store (s32) into @globvar)
161    CLFIMux undef %23:grx32bit, 1, implicit-def $cc
162    %25:grx32bit = LHIMux 0
163    %25:grx32bit = LOCHIMux %25, 1, 14, 2, implicit killed $cc
164    J %bb.1
165
166  bb.5.bb35:
167    successors: %bb.6, %bb.7
168
169    TMLMux %25, 1, implicit-def $cc
170    BRC 15, 8, %bb.7, implicit killed $cc
171    J %bb.6
172
173  bb.6.bb37:
174    successors:
175
176
177  bb.7.bb38:
178
179...
180