1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; Test 32-bit shifts left.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
5
6; Check the low end of the SLL range.
7define i32 @f1(i32 %a) {
8; CHECK-LABEL: f1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    sll %r2, 1
11; CHECK-NEXT:    br %r14
12  %shift = shl i32 %a, 1
13  ret i32 %shift
14}
15
16; Check the high end of the defined SLL range.
17define i32 @f2(i32 %a) {
18; CHECK-LABEL: f2:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    sll %r2, 31
21; CHECK-NEXT:    br %r14
22  %shift = shl i32 %a, 31
23  ret i32 %shift
24}
25
26; We don't generate shifts by out-of-range values.
27define i32 @f3(i32 %a) {
28; CHECK-LABEL: f3:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    br %r14
31  %shift = shl i32 %a, 32
32  ret i32 %shift
33}
34
35; Make sure that we don't generate negative shift amounts.
36define i32 @f4(i32 %a, i32 %amt) {
37; CHECK-LABEL: f4:
38; CHECK:       # %bb.0:
39; CHECK-NEXT:    ahi %r3, -1
40; CHECK-NEXT:    sll %r2, 0(%r3)
41; CHECK-NEXT:    br %r14
42  %sub = sub i32 %amt, 1
43  %shift = shl i32 %a, %sub
44  ret i32 %shift
45}
46
47; Check variable shifts.
48define i32 @f5(i32 %a, i32 %amt) {
49; CHECK-LABEL: f5:
50; CHECK:       # %bb.0:
51; CHECK-NEXT:    sll %r2, 0(%r3)
52; CHECK-NEXT:    br %r14
53  %shift = shl i32 %a, %amt
54  ret i32 %shift
55}
56
57; Check shift amounts that have a constant term.
58define i32 @f6(i32 %a, i32 %amt) {
59; CHECK-LABEL: f6:
60; CHECK:       # %bb.0:
61; CHECK-NEXT:    sll %r2, 10(%r3)
62; CHECK-NEXT:    br %r14
63  %add = add i32 %amt, 10
64  %shift = shl i32 %a, %add
65  ret i32 %shift
66}
67
68; ...and again with a truncated 64-bit shift amount.
69define i32 @f7(i32 %a, i64 %amt) {
70; CHECK-LABEL: f7:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    sll %r2, 10(%r3)
73; CHECK-NEXT:    br %r14
74  %add = add i64 %amt, 10
75  %trunc = trunc i64 %add to i32
76  %shift = shl i32 %a, %trunc
77  ret i32 %shift
78}
79
80; Check shift amounts that have the largest in-range constant term.  We could
81; mask the amount instead.
82define i32 @f8(i32 %a, i32 %amt) {
83; CHECK-LABEL: f8:
84; CHECK:       # %bb.0:
85; CHECK-NEXT:    sll %r2, 4095(%r3)
86; CHECK-NEXT:    br %r14
87  %add = add i32 %amt, 4095
88  %shift = shl i32 %a, %add
89  ret i32 %shift
90}
91
92; Check the next value up.  Again, we could mask the amount instead.
93define i32 @f9(i32 %a, i32 %amt) {
94; CHECK-LABEL: f9:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    ahi %r3, 4096
97; CHECK-NEXT:    sll %r2, 0(%r3)
98; CHECK-NEXT:    br %r14
99  %add = add i32 %amt, 4096
100  %shift = shl i32 %a, %add
101  ret i32 %shift
102}
103
104; Check that we don't try to generate "indexed" shifts.
105define i32 @f10(i32 %a, i32 %b, i32 %c) {
106; CHECK-LABEL: f10:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    ar %r3, %r4
109; CHECK-NEXT:    sll %r2, 0(%r3)
110; CHECK-NEXT:    br %r14
111  %add = add i32 %b, %c
112  %shift = shl i32 %a, %add
113  ret i32 %shift
114}
115
116; Check that the shift amount uses an address register.  It cannot be in %r0.
117define i32 @f11(i32 %a, i32 *%ptr) {
118; CHECK-LABEL: f11:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    l %r1, 0(%r3)
121; CHECK-NEXT:    sll %r2, 0(%r1)
122; CHECK-NEXT:    br %r14
123  %amt = load i32, i32 *%ptr
124  %shift = shl i32 %a, %amt
125  ret i32 %shift
126}
127