1; Test v2i64 absolute.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5; Test with slt.
6define <2 x i64> @f1(<2 x i64> %val) {
7; CHECK-LABEL: f1:
8; CHECK: vlpg %v24, %v24
9; CHECK: br %r14
10  %cmp = icmp slt <2 x i64> %val, zeroinitializer
11  %neg = sub <2 x i64> zeroinitializer, %val
12  %ret = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val
13  ret <2 x i64> %ret
14}
15
16; Test with sle.
17define <2 x i64> @f2(<2 x i64> %val) {
18; CHECK-LABEL: f2:
19; CHECK: vlpg %v24, %v24
20; CHECK: br %r14
21  %cmp = icmp sle <2 x i64> %val, zeroinitializer
22  %neg = sub <2 x i64> zeroinitializer, %val
23  %ret = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val
24  ret <2 x i64> %ret
25}
26
27; Test with sgt.
28define <2 x i64> @f3(<2 x i64> %val) {
29; CHECK-LABEL: f3:
30; CHECK: vlpg %v24, %v24
31; CHECK: br %r14
32  %cmp = icmp sgt <2 x i64> %val, zeroinitializer
33  %neg = sub <2 x i64> zeroinitializer, %val
34  %ret = select <2 x i1> %cmp, <2 x i64> %val, <2 x i64> %neg
35  ret <2 x i64> %ret
36}
37
38; Test with sge.
39define <2 x i64> @f4(<2 x i64> %val) {
40; CHECK-LABEL: f4:
41; CHECK: vlpg %v24, %v24
42; CHECK: br %r14
43  %cmp = icmp sge <2 x i64> %val, zeroinitializer
44  %neg = sub <2 x i64> zeroinitializer, %val
45  %ret = select <2 x i1> %cmp, <2 x i64> %val, <2 x i64> %neg
46  ret <2 x i64> %ret
47}
48
49; Test that negative absolute uses VLPG too.  There is no vector equivalent
50; of LOAD NEGATIVE.
51define <2 x i64> @f5(<2 x i64> %val) {
52; CHECK-LABEL: f5:
53; CHECK: vlpg [[REG:%v[0-9]+]], %v24
54; CHECK: vlcg %v24, [[REG]]
55; CHECK: br %r14
56  %cmp = icmp slt <2 x i64> %val, zeroinitializer
57  %neg = sub <2 x i64> zeroinitializer, %val
58  %abs = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val
59  %ret = sub <2 x i64> zeroinitializer, %abs
60  ret <2 x i64> %ret
61}
62
63; Try another form of negative absolute (slt version).
64define <2 x i64> @f6(<2 x i64> %val) {
65; CHECK-LABEL: f6:
66; CHECK: vlpg [[REG:%v[0-9]+]], %v24
67; CHECK: vlcg %v24, [[REG]]
68; CHECK: br %r14
69  %cmp = icmp slt <2 x i64> %val, zeroinitializer
70  %neg = sub <2 x i64> zeroinitializer, %val
71  %ret = select <2 x i1> %cmp, <2 x i64> %val, <2 x i64> %neg
72  ret <2 x i64> %ret
73}
74
75; Test with sle.
76define <2 x i64> @f7(<2 x i64> %val) {
77; CHECK-LABEL: f7:
78; CHECK: vlpg [[REG:%v[0-9]+]], %v24
79; CHECK: vlcg %v24, [[REG]]
80; CHECK: br %r14
81  %cmp = icmp sle <2 x i64> %val, zeroinitializer
82  %neg = sub <2 x i64> zeroinitializer, %val
83  %ret = select <2 x i1> %cmp, <2 x i64> %val, <2 x i64> %neg
84  ret <2 x i64> %ret
85}
86
87; Test with sgt.
88define <2 x i64> @f8(<2 x i64> %val) {
89; CHECK-LABEL: f8:
90; CHECK: vlpg [[REG:%v[0-9]+]], %v24
91; CHECK: vlcg %v24, [[REG]]
92; CHECK: br %r14
93  %cmp = icmp sgt <2 x i64> %val, zeroinitializer
94  %neg = sub <2 x i64> zeroinitializer, %val
95  %ret = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val
96  ret <2 x i64> %ret
97}
98
99; Test with sge.
100define <2 x i64> @f9(<2 x i64> %val) {
101; CHECK-LABEL: f9:
102; CHECK: vlpg [[REG:%v[0-9]+]], %v24
103; CHECK: vlcg %v24, [[REG]]
104; CHECK: br %r14
105  %cmp = icmp sge <2 x i64> %val, zeroinitializer
106  %neg = sub <2 x i64> zeroinitializer, %val
107  %ret = select <2 x i1> %cmp, <2 x i64> %neg, <2 x i64> %val
108  ret <2 x i64> %ret
109}
110
111; Test with an SRA-based boolean vector.
112define <2 x i64> @f10(<2 x i64> %val) {
113; CHECK-LABEL: f10:
114; CHECK: vlpg %v24, %v24
115; CHECK: br %r14
116  %shr = ashr <2 x i64> %val, <i64 63, i64 63>
117  %neg = sub <2 x i64> zeroinitializer, %val
118  %and1 = and <2 x i64> %shr, %neg
119  %not = xor <2 x i64> %shr, <i64 -1, i64 -1>
120  %and2 = and <2 x i64> %not, %val
121  %ret = or <2 x i64> %and1, %and2
122  ret <2 x i64> %ret
123}
124
125; ...and again in reverse
126define <2 x i64> @f11(<2 x i64> %val) {
127; CHECK-LABEL: f11:
128; CHECK: vlpg [[REG:%v[0-9]+]], %v24
129; CHECK: vlcg %v24, [[REG]]
130; CHECK: br %r14
131  %shr = ashr <2 x i64> %val, <i64 63, i64 63>
132  %and1 = and <2 x i64> %shr, %val
133  %not = xor <2 x i64> %shr, <i64 -1, i64 -1>
134  %neg = sub <2 x i64> zeroinitializer, %val
135  %and2 = and <2 x i64> %not, %neg
136  %ret = or <2 x i64> %and1, %and2
137  ret <2 x i64> %ret
138}
139