1; RUN: opt < %s -dfsan -dfsan-track-origins=1 -S | FileCheck %s 2; 3; %15 and %17 have the same key in shadow cache. They should not reuse the same 4; shadow because their blocks do not dominate each other. Origin tracking 5; splt blocks. This test ensures DT is updated correctly, and cached shadows 6; are not mis-used. 7target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 8target triple = "x86_64-unknown-linux-gnu" 9 10; CHECK: @__dfsan_arg_tls = external thread_local(initialexec) global [[TLS_ARR:\[100 x i64\]]] 11; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] 12; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] 13 14define void @cached_shadows(double %0) { 15 ; CHECK: @cached_shadows.dfsan 16 ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 17 ; CHECK: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]] 18 ; CHECK: [[L1:[0-9]+]]: 19 ; CHECK: {{.*}} = phi i[[#SBITS]] 20 ; CHECK: {{.*}} = phi i32 21 ; CHECK: {{.*}} = phi double [ 3.000000e+00 22 ; CHECK: [[S_L1:%.*]] = phi i[[#SBITS]] [ 0, %[[L0:[0-9]+]] ], [ [[S_L7:%.*]], %[[L7:[0-9]+]] ] 23 ; CHECK: [[O_L1:%.*]] = phi i32 [ 0, %[[L0]] ], [ [[O_L7:%.*]], %[[L7]] ] 24 ; CHECK: [[V_L1:%.*]] = phi double [ 4.000000e+00, %[[L0]] ], [ [[V_L7:%.*]], %[[L7]] ] 25 ; CHECK: br i1 {{%[0-9]+}}, label %[[L2:[0-9]+]], label %[[L4:[0-9]+]] 26 ; CHECK: [[L2]]: 27 ; CHECK: br i1 {{%[0-9]+}}, label %[[L3:[0-9]+]], label %[[L7]] 28 ; CHECK: [[L3]]: 29 ; CHECK: [[S_L3:%.*]] = or i[[#SBITS]] 30 ; CHECK: [[AS_NE_L3:%.*]] = icmp ne i[[#SBITS]] [[AS]], 0 31 ; CHECK: [[O_L3:%.*]] = select i1 [[AS_NE_L3]], i32 %2, i32 [[O_L1]] 32 ; CHECK: [[V_L3:%.*]] = fsub double [[V_L1]], %0 33 ; CHECK: br label %[[L7]] 34 ; CHECK: [[L4]]: 35 ; CHECK: br i1 %_dfscmp, label %[[L5:[0-9]+]], label %[[L6:[0-9]+]] 36 ; CHECK: [[L5]]: 37 ; CHECK: br label %[[L6]] 38 ; CHECK: [[L6]]: 39 ; CHECK: [[S_L6:%.*]] = or i[[#SBITS]] 40 ; CHECK: [[AS_NE_L6:%.*]] = icmp ne i[[#SBITS]] [[AS]], 0 41 ; CHECK: [[O_L6:%.*]] = select i1 [[AS_NE_L6]], i32 [[AO]], i32 [[O_L1]] 42 ; CHECK: [[V_L6:%.*]] = fadd double [[V_L1]], %0 43 ; CHECK: br label %[[L7]] 44 ; CHECK: [[L7]]: 45 ; CHECK: [[S_L7]] = phi i[[#SBITS]] [ [[S_L3]], %[[L3]] ], [ [[S_L1]], %[[L2]] ], [ [[S_L6]], %[[L6]] ] 46 ; CHECK: [[O_L7]] = phi i32 [ [[O_L3]], %[[L3]] ], [ [[O_L1]], %[[L2]] ], [ [[O_L6]], %[[L6]] ] 47 ; CHECK: [[V_L7]] = phi double [ [[V_L3]], %[[L3]] ], [ [[V_L1]], %[[L2]] ], [ [[V_L6]], %[[L6]] ] 48 ; CHECK: br i1 {{%[0-9]+}}, label %[[L1]], label %[[L8:[0-9]+]] 49 ; CHECK: [[L8]]: 50 51 %2 = alloca double, align 8 52 %3 = alloca double, align 8 53 %4 = bitcast double* %2 to i8* 54 store volatile double 1.000000e+00, double* %2, align 8 55 %5 = bitcast double* %3 to i8* 56 store volatile double 2.000000e+00, double* %3, align 8 57 br label %6 58 596: ; preds = %18, %1 60 %7 = phi double [ 3.000000e+00, %1 ], [ %19, %18 ] 61 %8 = phi double [ 4.000000e+00, %1 ], [ %20, %18 ] 62 %9 = load volatile double, double* %3, align 8 63 %10 = fcmp une double %9, 0.000000e+00 64 %11 = load volatile double, double* %3, align 8 65 br i1 %10, label %12, label %16 66 6712: ; preds = %6 68 %13 = fcmp une double %11, 0.000000e+00 69 br i1 %13, label %14, label %18 70 7114: ; preds = %12 72 %15 = fsub double %8, %0 73 br label %18 74 7516: ; preds = %6 76 store volatile double %11, double* %2, align 8 77 %17 = fadd double %8, %0 78 br label %18 79 8018: ; preds = %16, %14, %12 81 %19 = phi double [ %8, %14 ], [ %7, %12 ], [ %8, %16 ] 82 %20 = phi double [ %15, %14 ], [ %8, %12 ], [ %17, %16 ] 83 %21 = fcmp olt double %19, 9.900000e+01 84 br i1 %21, label %6, label %22 85 8622: ; preds = %18 87 ret void 88}