1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the functions necessary to decode AArch64 instruction
11 // bitpatterns into MCInsts (with the help of TableGenerated information from
12 // the instruction definitions).
13 //
14 //===----------------------------------------------------------------------===//
15
16 /* Capstone Disassembly Engine */
17 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
18
19 #ifdef CAPSTONE_HAS_ARM64
20
21 #include <stdio.h> // DEBUG
22 #include <stdlib.h>
23
24 #include "../../cs_priv.h"
25 #include "../../utils.h"
26
27 #include "AArch64Disassembler.h"
28
29 #include "../../MCDisassembler.h"
30 #include "../../MCFixedLenDisassembler.h"
31 #include "../../MCInst.h"
32 #include "../../MCInstrDesc.h"
33 #include "../../MCRegisterInfo.h"
34
35 #include "AArch64AddressingModes.h"
36 #include "AArch64BaseInfo.h"
37
38 // Forward declare these because the autogenerated code will reference them.
39 // Definitions are further down.
40 static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst,
41 unsigned RegNo, uint64_t Address, const void *Decoder);
42 static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
43 uint64_t Address, const void *Decoder);
44 static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
45 uint64_t Address, const void *Decoder);
46 static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
47 uint64_t Address, const void *Decoder);
48 static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
49 uint64_t Address, const void *Decoder);
50 static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
51 uint64_t Address, const void *Decoder);
52 static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst,
53 unsigned RegNo, uint64_t Address, const void *Decoder);
54 static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
55 uint64_t Address, const void *Decoder);
56 static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst,
57 unsigned RegNo, uint64_t Address, const void *Decoder);
58 static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo,
59 uint64_t Address, const void *Decoder);
60 static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo,
61 uint64_t Address, const void *Decoder);
62 static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo,
63 uint64_t Address, const void *Decoder);
64 static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo,
65 uint64_t Address, const void *Decoder);
66 static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo,
67 uint64_t Address, const void *Decoder);
68 static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
69 uint64_t Address, const void *Decoder);
70 static DecodeStatus DecodeZPRRegisterClass(MCInst *Inst, unsigned RegNo,
71 uint64_t Address, const void *Decoder);
72 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst *Inst, unsigned RegNo,
73 uint64_t Address, const void *Decoder);
74 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst *Inst, unsigned RegNo,
75 uint64_t Address, const void *Decoder);
76 static DecodeStatus DecodeZPR2RegisterClass(MCInst *Inst, unsigned RegNo,
77 uint64_t Address, const void *Decoder);
78 static DecodeStatus DecodeZPR3RegisterClass(MCInst *Inst, unsigned RegNo,
79 uint64_t Address, const void *Decoder);
80 static DecodeStatus DecodeZPR4RegisterClass(MCInst *Inst, unsigned RegNo,
81 uint64_t Address, const void *Decoder);
82 static DecodeStatus DecodePPRRegisterClass(MCInst *Inst, unsigned RegNo,
83 uint64_t Address, const void *Decoder);
84 static DecodeStatus DecodePPR_3bRegisterClass(MCInst *Inst, unsigned RegNo,
85 uint64_t Address, const void *Decoder);
86 static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
87 uint64_t Address, const void *Decoder);
88 static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm,
89 uint64_t Address, const void *Decoder);
90 static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
91 uint64_t Address, const void *Decoder);
92 static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
93 uint64_t Address, const void *Decoder);
94 static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
95 uint64_t Address, const void *Decoder);
96 static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
97 uint64_t Address, const void *Decoder);
98 static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
99 uint64_t Address, const void *Decoder);
100 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
101 uint32_t insn, uint64_t Address, const void *Decoder);
102 static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
103 uint32_t insn, uint64_t Address, const void *Decoder);
104 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
105 uint32_t insn, uint64_t Address, const void *Decoder);
106 static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
107 uint64_t Address, const void *Decoder);
108 static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
109 uint32_t insn, uint64_t Address, const void *Decoder);
110 static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
111 uint32_t insn, uint64_t Address, const void *Decoder);
112 static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
113 uint64_t Address, const void *Decoder);
114 static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
115 uint32_t insn, uint64_t Address, const void *Decoder);
116 static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
117 uint64_t Address, const void *Decoder);
118 static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
119 uint64_t Address, const void *Decoder);
120 static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
121 uint64_t Address, const void *Decoder);
122 static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
123 uint32_t insn, uint64_t Address, const void *Decoder);
124 static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
125 uint64_t Address, const void *Decoder);
126 static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
127 uint64_t Address, const void *Decoder);
128 static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm,
129 uint64_t Addr, const void *Decoder);
130 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm,
131 uint64_t Addr, const void *Decoder);
132 static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm,
133 uint64_t Addr, const void *Decoder);
134 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm,
135 uint64_t Addr, const void *Decoder);
136 static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm,
137 uint64_t Addr, const void *Decoder);
138 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm,
139 uint64_t Addr, const void *Decoder);
140 static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm,
141 uint64_t Addr, const void *Decoder);
142 static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm,
143 uint64_t Addr, const void *Decoder);
144 static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm,
145 uint64_t Addr, const void *Decoder);
146 static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
147 uint64_t Addr, const void *Decoder);
148 static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
149 uint64_t Addr, const void *Decoder);
150 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst *Inst,
151 unsigned RegNo, uint64_t Addr, const void *Decoder);
152 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst *Inst,
153 unsigned RegNo, uint64_t Addr, const void *Decoder);
154 static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address,
157 const void *Decoder, int Bits);
158 static DecodeStatus DecodeImm8OptLsl(MCInst *Inst, unsigned Imm, uint64_t Addr,
159 const void *Decoder, int ElementWidth);
160 static DecodeStatus DecodeSVEIncDecImm(MCInst *Inst, unsigned Imm,
161 uint64_t Addr, const void *Decoder);
162 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
163 uint32_t insn, uint64_t Addr, const void *Decoder);
164 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst *Inst, unsigned RegNo,
165 uint64_t Addr, const void *Decoder);
166 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo,
167 uint64_t Addr, const void *Decoder);
168
169
Check(DecodeStatus * Out,DecodeStatus In)170 static bool Check(DecodeStatus *Out, DecodeStatus In)
171 {
172 switch (In) {
173 default: // never reach
174 return true;
175
176 case MCDisassembler_Success:
177 // Out stays the same.
178 return true;
179
180 case MCDisassembler_SoftFail:
181 *Out = In;
182 return true;
183
184 case MCDisassembler_Fail:
185 *Out = In;
186 return false;
187 }
188 // llvm_unreachable("Invalid DecodeStatus!");
189 }
190
191 // Hacky: enable all features for disassembler
AArch64_getFeatureBits(int feature)192 uint64_t AArch64_getFeatureBits(int feature)
193 {
194 // enable all features
195 return (uint64_t)-1;
196 }
197
198 #define GET_SUBTARGETINFO_ENUM
199 #include "AArch64GenSubtargetInfo.inc"
200
201 #include "AArch64GenDisassemblerTables.inc"
202
203 #define GET_INSTRINFO_ENUM
204 #include "AArch64GenInstrInfo.inc"
205
206 #define GET_REGINFO_ENUM
207 #define GET_REGINFO_MC_DESC
208 #include "AArch64GenRegisterInfo.inc"
209
210 #define Success MCDisassembler_Success
211 #define Fail MCDisassembler_Fail
212 #define SoftFail MCDisassembler_SoftFail
213
_getInstruction(cs_struct * ud,MCInst * MI,const uint8_t * code,size_t code_len,uint16_t * Size,uint64_t Address,MCRegisterInfo * MRI)214 static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI,
215 const uint8_t *code, size_t code_len,
216 uint16_t *Size,
217 uint64_t Address, MCRegisterInfo *MRI)
218 {
219 uint32_t insn;
220 DecodeStatus result;
221 size_t i;
222
223 if (code_len < 4) {
224 // not enough data
225 *Size = 0;
226 return MCDisassembler_Fail;
227 }
228
229 if (MI->flat_insn->detail) {
230 memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm64)+sizeof(cs_arm64));
231 for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++)
232 MI->flat_insn->detail->arm64.operands[i].vector_index = -1;
233 }
234
235 if (MODE_IS_BIG_ENDIAN(ud->mode))
236 insn = (code[3] << 0) | (code[2] << 8) |
237 (code[1] << 16) | ((uint32_t) code[0] << 24);
238 else
239 insn = ((uint32_t) code[3] << 24) | (code[2] << 16) |
240 (code[1] << 8) | (code[0] << 0);
241
242 // Calling the auto-generated decoder function.
243 result = decodeInstruction_4(DecoderTable32, MI, insn, Address);
244 if (result != MCDisassembler_Fail) {
245 *Size = 4;
246
247 return result;
248 }
249
250 // invalid code
251 MCInst_clear(MI);
252 *Size = 0;
253
254 return MCDisassembler_Fail;
255 }
256
AArch64_getInstruction(csh ud,const uint8_t * code,size_t code_len,MCInst * instr,uint16_t * size,uint64_t address,void * info)257 bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len,
258 MCInst *instr, uint16_t *size, uint64_t address, void *info)
259 {
260 DecodeStatus status = _getInstruction((cs_struct *)ud, instr,
261 code, code_len,
262 size,
263 address, (MCRegisterInfo *)info);
264
265 return status == MCDisassembler_Success;
266 }
267
268 static const unsigned FPR128DecoderTable[] = {
269 AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4,
270 AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9,
271 AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14,
272 AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19,
273 AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24,
274 AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29,
275 AArch64_Q30, AArch64_Q31
276 };
277
DecodeFPR128RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)278 static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
279 uint64_t Addr, const void *Decoder)
280 {
281 unsigned Register;
282
283 if (RegNo > 31)
284 return Fail;
285
286 Register = FPR128DecoderTable[RegNo];
287 MCOperand_CreateReg0(Inst, Register);
288
289 return Success;
290 }
291
DecodeFPR128_loRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)292 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo,
293 uint64_t Addr, const void *Decoder)
294 {
295 if (RegNo > 15)
296 return Fail;
297
298 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
299 }
300
301 static const unsigned FPR64DecoderTable[] = {
302 AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4,
303 AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9,
304 AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14,
305 AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19,
306 AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24,
307 AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29,
308 AArch64_D30, AArch64_D31
309 };
310
DecodeFPR64RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)311 static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
312 uint64_t Addr, const void *Decoder)
313 {
314 unsigned Register;
315
316 if (RegNo > 31)
317 return Fail;
318
319 Register = FPR64DecoderTable[RegNo];
320 MCOperand_CreateReg0(Inst, Register);
321
322 return Success;
323 }
324
325 static const unsigned FPR32DecoderTable[] = {
326 AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4,
327 AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9,
328 AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14,
329 AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19,
330 AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24,
331 AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29,
332 AArch64_S30, AArch64_S31
333 };
334
DecodeFPR32RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)335 static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
336 uint64_t Addr, const void *Decoder)
337 {
338 unsigned Register;
339
340 if (RegNo > 31)
341 return Fail;
342
343 Register = FPR32DecoderTable[RegNo];
344 MCOperand_CreateReg0(Inst, Register);
345
346 return Success;
347 }
348
349 static const unsigned FPR16DecoderTable[] = {
350 AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4,
351 AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9,
352 AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14,
353 AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19,
354 AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24,
355 AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29,
356 AArch64_H30, AArch64_H31
357 };
358
DecodeFPR16RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)359 static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
360 uint64_t Addr, const void *Decoder)
361 {
362 unsigned Register;
363
364 if (RegNo > 31)
365 return Fail;
366
367 Register = FPR16DecoderTable[RegNo];
368 MCOperand_CreateReg0(Inst, Register);
369
370 return Success;
371 }
372
373 static const unsigned FPR8DecoderTable[] = {
374 AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4,
375 AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9,
376 AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14,
377 AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19,
378 AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24,
379 AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29,
380 AArch64_B30, AArch64_B31
381 };
382
DecodeFPR8RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)383 static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
384 uint64_t Addr, const void *Decoder)
385 {
386 unsigned Register;
387
388 if (RegNo > 31)
389 return Fail;
390
391 Register = FPR8DecoderTable[RegNo];
392 MCOperand_CreateReg0(Inst, Register);
393
394 return Success;
395 }
396
397 static const unsigned GPR64DecoderTable[] = {
398 AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4,
399 AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9,
400 AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14,
401 AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19,
402 AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24,
403 AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP,
404 AArch64_LR, AArch64_XZR
405 };
406
DecodeGPR64commonRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)407 static DecodeStatus DecodeGPR64commonRegisterClass(MCInst *Inst, unsigned RegNo,
408 uint64_t Addr, const void *Decoder)
409 {
410 unsigned Register;
411
412 if (RegNo > 30)
413 return Fail;
414
415 Register = GPR64DecoderTable[RegNo];
416 MCOperand_CreateReg0(Inst, Register);
417
418 return Success;
419 }
420
DecodeGPR64RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)421 static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
422 uint64_t Addr, const void *Decoder)
423 {
424 unsigned Register;
425
426 if (RegNo > 31)
427 return Fail;
428
429 Register = GPR64DecoderTable[RegNo];
430 MCOperand_CreateReg0(Inst, Register);
431
432 return Success;
433 }
434
DecodeGPR64spRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)435 static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo,
436 uint64_t Addr, const void *Decoder)
437 {
438 unsigned Register;
439
440 if (RegNo > 31)
441 return Fail;
442
443 Register = GPR64DecoderTable[RegNo];
444 if (Register == AArch64_XZR)
445 Register = AArch64_SP;
446
447 MCOperand_CreateReg0(Inst, Register);
448
449 return Success;
450 }
451
452 static const unsigned GPR32DecoderTable[] = {
453 AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4,
454 AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9,
455 AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14,
456 AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19,
457 AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24,
458 AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29,
459 AArch64_W30, AArch64_WZR
460 };
461
DecodeGPR32RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)462 static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
463 uint64_t Addr, const void *Decoder)
464 {
465 unsigned Register;
466
467 if (RegNo > 31)
468 return Fail;
469
470 Register = GPR32DecoderTable[RegNo];
471 MCOperand_CreateReg0(Inst, Register);
472
473 return Success;
474 }
475
DecodeGPR32spRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)476 static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo,
477 uint64_t Addr, const void *Decoder)
478 {
479 unsigned Register;
480
481 if (RegNo > 31)
482 return Fail;
483
484 Register = GPR32DecoderTable[RegNo];
485 if (Register == AArch64_WZR)
486 Register = AArch64_WSP;
487
488 MCOperand_CreateReg0(Inst, Register);
489
490 return Success;
491 }
492
493 static const unsigned ZPRDecoderTable[] = {
494 AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3,
495 AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7,
496 AArch64_Z8, AArch64_Z9, AArch64_Z10, AArch64_Z11,
497 AArch64_Z12, AArch64_Z13, AArch64_Z14, AArch64_Z15,
498 AArch64_Z16, AArch64_Z17, AArch64_Z18, AArch64_Z19,
499 AArch64_Z20, AArch64_Z21, AArch64_Z22, AArch64_Z23,
500 AArch64_Z24, AArch64_Z25, AArch64_Z26, AArch64_Z27,
501 AArch64_Z28, AArch64_Z29, AArch64_Z30, AArch64_Z31
502 };
503
DecodeZPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)504 static DecodeStatus DecodeZPRRegisterClass(MCInst *Inst, unsigned RegNo,
505 uint64_t Address, const void *Decoder)
506 {
507 unsigned Register;
508
509 if (RegNo > 31)
510 return Fail;
511
512 Register = ZPRDecoderTable[RegNo];
513 MCOperand_CreateReg0(Inst, Register);
514
515 return Success;
516 }
517
DecodeZPR_4bRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)518 static DecodeStatus DecodeZPR_4bRegisterClass(MCInst *Inst, unsigned RegNo,
519 uint64_t Address, const void *Decoder)
520 {
521 if (RegNo > 15)
522 return Fail;
523
524 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
525 }
526
DecodeZPR_3bRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)527 static DecodeStatus DecodeZPR_3bRegisterClass(MCInst *Inst, unsigned RegNo,
528 uint64_t Address, const void *Decoder)
529 {
530 if (RegNo > 7)
531 return Fail;
532
533 return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
534 }
535
536 static const unsigned ZZDecoderTable[] = {
537 AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4,
538 AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8,
539 AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12,
540 AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16,
541 AArch64_Z16_Z17, AArch64_Z17_Z18, AArch64_Z18_Z19, AArch64_Z19_Z20,
542 AArch64_Z20_Z21, AArch64_Z21_Z22, AArch64_Z22_Z23, AArch64_Z23_Z24,
543 AArch64_Z24_Z25, AArch64_Z25_Z26, AArch64_Z26_Z27, AArch64_Z27_Z28,
544 AArch64_Z28_Z29, AArch64_Z29_Z30, AArch64_Z30_Z31, AArch64_Z31_Z0
545 };
546
DecodeZPR2RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)547 static DecodeStatus DecodeZPR2RegisterClass(MCInst *Inst, unsigned RegNo,
548 uint64_t Address, const void *Decoder)
549 {
550 unsigned Register;
551
552 if (RegNo > 31)
553 return Fail;
554
555 Register = ZZDecoderTable[RegNo];
556 MCOperand_CreateReg0(Inst, Register);
557
558 return Success;
559 }
560
561 static const unsigned ZZZDecoderTable[] = {
562 AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4,
563 AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7,
564 AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10,
565 AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13,
566 AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16,
567 AArch64_Z15_Z16_Z17, AArch64_Z16_Z17_Z18, AArch64_Z17_Z18_Z19,
568 AArch64_Z18_Z19_Z20, AArch64_Z19_Z20_Z21, AArch64_Z20_Z21_Z22,
569 AArch64_Z21_Z22_Z23, AArch64_Z22_Z23_Z24, AArch64_Z23_Z24_Z25,
570 AArch64_Z24_Z25_Z26, AArch64_Z25_Z26_Z27, AArch64_Z26_Z27_Z28,
571 AArch64_Z27_Z28_Z29, AArch64_Z28_Z29_Z30, AArch64_Z29_Z30_Z31,
572 AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1
573 };
574
DecodeZPR3RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)575 static DecodeStatus DecodeZPR3RegisterClass(MCInst *Inst, unsigned RegNo,
576 uint64_t Address, const void *Decoder)
577 {
578 unsigned Register;
579
580 if (RegNo > 31)
581 return Fail;
582
583 Register = ZZZDecoderTable[RegNo];
584 MCOperand_CreateReg0(Inst, Register);
585
586 return Success;
587 }
588
589 static const unsigned ZZZZDecoderTable[] = {
590 AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5,
591 AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8,
592 AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11,
593 AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14,
594 AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17,
595 AArch64_Z15_Z16_Z17_Z18, AArch64_Z16_Z17_Z18_Z19, AArch64_Z17_Z18_Z19_Z20,
596 AArch64_Z18_Z19_Z20_Z21, AArch64_Z19_Z20_Z21_Z22, AArch64_Z20_Z21_Z22_Z23,
597 AArch64_Z21_Z22_Z23_Z24, AArch64_Z22_Z23_Z24_Z25, AArch64_Z23_Z24_Z25_Z26,
598 AArch64_Z24_Z25_Z26_Z27, AArch64_Z25_Z26_Z27_Z28, AArch64_Z26_Z27_Z28_Z29,
599 AArch64_Z27_Z28_Z29_Z30, AArch64_Z28_Z29_Z30_Z31, AArch64_Z29_Z30_Z31_Z0,
600 AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2
601 };
602
DecodeZPR4RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,const void * Decoder)603 static DecodeStatus DecodeZPR4RegisterClass(MCInst *Inst, unsigned RegNo,
604 uint64_t Address, const void *Decoder)
605 {
606 unsigned Register;
607
608 if (RegNo > 31)
609 return Fail;
610
611 Register = ZZZZDecoderTable[RegNo];
612 MCOperand_CreateReg0(Inst, Register);
613
614 return Success;
615 }
616
617 static const unsigned PPRDecoderTable[] = {
618 AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3,
619 AArch64_P4, AArch64_P5, AArch64_P6, AArch64_P7,
620 AArch64_P8, AArch64_P9, AArch64_P10, AArch64_P11,
621 AArch64_P12, AArch64_P13, AArch64_P14, AArch64_P15
622 };
623
DecodePPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)624 static DecodeStatus DecodePPRRegisterClass(MCInst *Inst, unsigned RegNo,
625 uint64_t Addr, const void *Decoder)
626 {
627 unsigned Register;
628
629 if (RegNo > 15)
630 return Fail;
631
632 Register = PPRDecoderTable[RegNo];
633 MCOperand_CreateReg0(Inst, Register);
634
635 return Success;
636 }
637
DecodePPR_3bRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)638 static DecodeStatus DecodePPR_3bRegisterClass(MCInst *Inst, unsigned RegNo,
639 uint64_t Addr, const void *Decoder)
640 {
641 if (RegNo > 7)
642 return Fail;
643
644 // Just reuse the PPR decode table
645 return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
646 }
647
648 static const unsigned VectorDecoderTable[] = {
649 AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4,
650 AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9,
651 AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14,
652 AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19,
653 AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24,
654 AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29,
655 AArch64_Q30, AArch64_Q31
656 };
657
DecodeVectorRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)658 static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo,
659 uint64_t Addr, const void *Decoder)
660 {
661 unsigned Register;
662
663 if (RegNo > 31)
664 return Fail;
665
666 Register = VectorDecoderTable[RegNo];
667 MCOperand_CreateReg0(Inst, Register);
668
669 return Success;
670 }
671
672 static const unsigned QQDecoderTable[] = {
673 AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4,
674 AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8,
675 AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12,
676 AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16,
677 AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20,
678 AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24,
679 AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28,
680 AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0
681 };
682
DecodeQQRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)683 static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo,
684 uint64_t Addr, const void *Decoder)
685 {
686 unsigned Register;
687
688 if (RegNo > 31)
689 return Fail;
690
691 Register = QQDecoderTable[RegNo];
692 MCOperand_CreateReg0(Inst, Register);
693
694 return Success;
695 }
696
697 static const unsigned QQQDecoderTable[] = {
698 AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4,
699 AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7,
700 AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10,
701 AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13,
702 AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16,
703 AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19,
704 AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22,
705 AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25,
706 AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28,
707 AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31,
708 AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1
709 };
710
DecodeQQQRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)711 static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo,
712 uint64_t Addr, const void *Decoder)
713 {
714 unsigned Register;
715
716 if (RegNo > 31)
717 return Fail;
718
719 Register = QQQDecoderTable[RegNo];
720 MCOperand_CreateReg0(Inst, Register);
721
722 return Success;
723 }
724
725 static const unsigned QQQQDecoderTable[] = {
726 AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5,
727 AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8,
728 AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11,
729 AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14,
730 AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17,
731 AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20,
732 AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23,
733 AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26,
734 AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29,
735 AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0,
736 AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2
737 };
738
DecodeQQQQRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)739 static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo,
740 uint64_t Addr, const void *Decoder)
741 {
742 unsigned Register;
743
744 if (RegNo > 31)
745 return Fail;
746
747 Register = QQQQDecoderTable[RegNo];
748 MCOperand_CreateReg0(Inst, Register);
749
750 return Success;
751 }
752
753 static const unsigned DDDecoderTable[] = {
754 AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4,
755 AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8,
756 AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12,
757 AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16,
758 AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20,
759 AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24,
760 AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28,
761 AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0
762 };
763
DecodeDDRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)764 static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo,
765 uint64_t Addr, const void *Decoder)
766 {
767 unsigned Register;
768
769 if (RegNo > 31)
770 return Fail;
771
772 Register = DDDecoderTable[RegNo];
773 MCOperand_CreateReg0(Inst, Register);
774
775 return Success;
776 }
777
778 static const unsigned DDDDecoderTable[] = {
779 AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4,
780 AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7,
781 AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10,
782 AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13,
783 AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16,
784 AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19,
785 AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22,
786 AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25,
787 AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28,
788 AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31,
789 AArch64_D30_D31_D0, AArch64_D31_D0_D1
790 };
791
DecodeDDDRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)792 static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo,
793 uint64_t Addr, const void *Decoder)
794 {
795 unsigned Register;
796
797 if (RegNo > 31)
798 return Fail;
799
800 Register = DDDDecoderTable[RegNo];
801 MCOperand_CreateReg0(Inst, Register);
802
803 return Success;
804 }
805
806 static const unsigned DDDDDecoderTable[] = {
807 AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5,
808 AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8,
809 AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11,
810 AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14,
811 AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17,
812 AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20,
813 AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23,
814 AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26,
815 AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29,
816 AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0,
817 AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2
818 };
819
DecodeDDDDRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)820 static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
821 uint64_t Addr, const void *Decoder)
822 {
823 unsigned Register;
824
825 if (RegNo > 31)
826 return Fail;
827
828 Register = DDDDDecoderTable[RegNo];
829 MCOperand_CreateReg0(Inst, Register);
830
831 return Success;
832 }
833
DecodeFixedPointScaleImm32(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)834 static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
835 uint64_t Addr, const void *Decoder)
836 {
837 // scale{5} is asserted as 1 in tblgen.
838 Imm |= 0x20;
839 MCOperand_CreateImm0(Inst, 64 - Imm);
840
841 return Success;
842 }
843
DecodeFixedPointScaleImm64(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)844 static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm,
845 uint64_t Addr, const void *Decoder)
846 {
847 MCOperand_CreateImm0(Inst, 64 - Imm);
848
849 return Success;
850 }
851
DecodePCRelLabel19(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)852 static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
853 uint64_t Addr, const void *Decoder)
854 {
855 int64_t ImmVal = Imm;
856
857 // Sign-extend 19-bit immediate.
858 if (ImmVal & (1 << (19 - 1)))
859 ImmVal |= ~((1LL << 19) - 1);
860
861 MCOperand_CreateImm0(Inst, ImmVal);
862
863 return Success;
864 }
865
DecodeMemExtend(MCInst * Inst,unsigned Imm,uint64_t Address,const void * Decoder)866 static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
867 uint64_t Address, const void *Decoder)
868 {
869 MCOperand_CreateImm0(Inst, (Imm >> 1) & 1);
870 MCOperand_CreateImm0(Inst, Imm & 1);
871
872 return Success;
873 }
874
DecodeMRSSystemRegister(MCInst * Inst,unsigned Imm,uint64_t Address,const void * Decoder)875 static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
876 uint64_t Address, const void *Decoder)
877 {
878 MCOperand_CreateImm0(Inst, Imm);
879
880 // Every system register in the encoding space is valid with the syntax
881 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
882 return Success;
883 }
884
DecodeMSRSystemRegister(MCInst * Inst,unsigned Imm,uint64_t Address,const void * Decoder)885 static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
886 uint64_t Address, const void *Decoder)
887 {
888 MCOperand_CreateImm0(Inst, Imm);
889
890 return Success;
891 }
892
DecodeFMOVLaneInstruction(MCInst * Inst,unsigned Insn,uint64_t Address,const void * Decoder)893 static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
894 uint64_t Address, const void *Decoder)
895 {
896 // This decoder exists to add the dummy Lane operand to the MCInst, which must
897 // be 1 in assembly but has no other real manifestation.
898 unsigned Rd = fieldFromInstruction_4(Insn, 0, 5);
899 unsigned Rn = fieldFromInstruction_4(Insn, 5, 5);
900 unsigned IsToVec = fieldFromInstruction_4(Insn, 16, 1);
901
902 if (IsToVec) {
903 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
904 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
905 } else {
906 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
907 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
908 }
909
910 // Add the lane
911 MCOperand_CreateImm0(Inst, 1);
912
913 return Success;
914 }
915
DecodeVecShiftRImm(MCInst * Inst,unsigned Imm,unsigned Add)916 static DecodeStatus DecodeVecShiftRImm(MCInst *Inst, unsigned Imm,
917 unsigned Add)
918 {
919 MCOperand_CreateImm0(Inst, Add - Imm);
920
921 return Success;
922 }
923
DecodeVecShiftLImm(MCInst * Inst,unsigned Imm,unsigned Add)924 static DecodeStatus DecodeVecShiftLImm(MCInst *Inst, unsigned Imm,
925 unsigned Add)
926 {
927 MCOperand_CreateImm0(Inst, (Imm + Add) & (Add - 1));
928
929 return Success;
930 }
931
DecodeVecShiftR64Imm(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)932 static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm,
933 uint64_t Addr, const void *Decoder)
934 {
935 return DecodeVecShiftRImm(Inst, Imm, 64);
936 }
937
DecodeVecShiftR64ImmNarrow(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)938 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm,
939 uint64_t Addr, const void *Decoder)
940 {
941 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
942 }
943
DecodeVecShiftR32Imm(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)944 static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm,
945 uint64_t Addr, const void *Decoder)
946 {
947 return DecodeVecShiftRImm(Inst, Imm, 32);
948 }
949
DecodeVecShiftR32ImmNarrow(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)950 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm,
951 uint64_t Addr, const void *Decoder)
952 {
953 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
954 }
955
DecodeVecShiftR16Imm(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)956 static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm,
957 uint64_t Addr, const void *Decoder)
958 {
959 return DecodeVecShiftRImm(Inst, Imm, 16);
960 }
961
DecodeVecShiftR16ImmNarrow(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)962 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm,
963 uint64_t Addr, const void *Decoder)
964 {
965 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
966 }
967
DecodeVecShiftR8Imm(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)968 static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm,
969 uint64_t Addr, const void *Decoder)
970 {
971 return DecodeVecShiftRImm(Inst, Imm, 8);
972 }
973
DecodeVecShiftL64Imm(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)974 static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm,
975 uint64_t Addr, const void *Decoder)
976 {
977 return DecodeVecShiftLImm(Inst, Imm, 64);
978 }
979
DecodeVecShiftL32Imm(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)980 static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm,
981 uint64_t Addr, const void *Decoder)
982 {
983 return DecodeVecShiftLImm(Inst, Imm, 32);
984 }
985
DecodeVecShiftL16Imm(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)986 static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
987 uint64_t Addr, const void *Decoder)
988 {
989 return DecodeVecShiftLImm(Inst, Imm, 16);
990 }
991
DecodeVecShiftL8Imm(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)992 static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
993 uint64_t Addr, const void *Decoder)
994 {
995 return DecodeVecShiftLImm(Inst, Imm, 8);
996 }
997
DecodeThreeAddrSRegInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)998 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
999 uint32_t insn, uint64_t Addr, const void *Decoder)
1000 {
1001 unsigned Rd = fieldFromInstruction_4(insn, 0, 5);
1002 unsigned Rn = fieldFromInstruction_4(insn, 5, 5);
1003 unsigned Rm = fieldFromInstruction_4(insn, 16, 5);
1004 unsigned shiftHi = fieldFromInstruction_4(insn, 22, 2);
1005 unsigned shiftLo = fieldFromInstruction_4(insn, 10, 6);
1006 unsigned shift = (shiftHi << 6) | shiftLo;
1007
1008 switch (MCInst_getOpcode(Inst)) {
1009 default:
1010 return Fail;
1011
1012 case AArch64_ADDWrs:
1013 case AArch64_ADDSWrs:
1014 case AArch64_SUBWrs:
1015 case AArch64_SUBSWrs:
1016 // if shift == '11' then ReservedValue()
1017 if (shiftHi == 0x3)
1018 return Fail;
1019 // Deliberate fallthrough
1020
1021 case AArch64_ANDWrs:
1022 case AArch64_ANDSWrs:
1023 case AArch64_BICWrs:
1024 case AArch64_BICSWrs:
1025 case AArch64_ORRWrs:
1026 case AArch64_ORNWrs:
1027 case AArch64_EORWrs:
1028 case AArch64_EONWrs: {
1029 // if sf == '0' and imm6<5> == '1' then ReservedValue()
1030 if (shiftLo >> 5 == 1)
1031 return Fail;
1032
1033 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1034 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1035 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1036 break;
1037 }
1038
1039 case AArch64_ADDXrs:
1040 case AArch64_ADDSXrs:
1041 case AArch64_SUBXrs:
1042 case AArch64_SUBSXrs:
1043 // if shift == '11' then ReservedValue()
1044 if (shiftHi == 0x3)
1045 return Fail;
1046 // Deliberate fallthrough
1047
1048 case AArch64_ANDXrs:
1049 case AArch64_ANDSXrs:
1050 case AArch64_BICXrs:
1051 case AArch64_BICSXrs:
1052 case AArch64_ORRXrs:
1053 case AArch64_ORNXrs:
1054 case AArch64_EORXrs:
1055 case AArch64_EONXrs:
1056 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1057 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1058 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1059 break;
1060 }
1061
1062 MCOperand_CreateImm0(Inst, shift);
1063
1064 return Success;
1065 }
1066
DecodeMoveImmInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1067 static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
1068 uint64_t Addr, const void *Decoder)
1069 {
1070 unsigned Rd = fieldFromInstruction_4(insn, 0, 5);
1071 unsigned imm = fieldFromInstruction_4(insn, 5, 16);
1072 unsigned shift = fieldFromInstruction_4(insn, 21, 2);
1073
1074 shift <<= 4;
1075
1076 switch (MCInst_getOpcode(Inst)) {
1077 default:
1078 return Fail;
1079
1080 case AArch64_MOVZWi:
1081 case AArch64_MOVNWi:
1082 case AArch64_MOVKWi:
1083 if (shift & (1U << 5))
1084 return Fail;
1085 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1086 break;
1087
1088 case AArch64_MOVZXi:
1089 case AArch64_MOVNXi:
1090 case AArch64_MOVKXi:
1091 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1092 break;
1093 }
1094
1095 if (MCInst_getOpcode(Inst) == AArch64_MOVKWi ||
1096 MCInst_getOpcode(Inst) == AArch64_MOVKXi)
1097 MCInst_addOperand2(Inst, MCInst_getOperand(Inst, 0));
1098
1099 MCOperand_CreateImm0(Inst, imm);
1100 MCOperand_CreateImm0(Inst, shift);
1101
1102 return Success;
1103 }
1104
DecodeUnsignedLdStInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1105 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
1106 uint32_t insn, uint64_t Addr, const void *Decoder)
1107 {
1108 unsigned Rt = fieldFromInstruction_4(insn, 0, 5);
1109 unsigned Rn = fieldFromInstruction_4(insn, 5, 5);
1110 unsigned offset = fieldFromInstruction_4(insn, 10, 12);
1111
1112 switch (MCInst_getOpcode(Inst)) {
1113 default:
1114 return Fail;
1115
1116 case AArch64_PRFMui:
1117 // Rt is an immediate in prefetch.
1118 MCOperand_CreateImm0(Inst, Rt);
1119 break;
1120
1121 case AArch64_STRBBui:
1122 case AArch64_LDRBBui:
1123 case AArch64_LDRSBWui:
1124 case AArch64_STRHHui:
1125 case AArch64_LDRHHui:
1126 case AArch64_LDRSHWui:
1127 case AArch64_STRWui:
1128 case AArch64_LDRWui:
1129 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1130 break;
1131
1132 case AArch64_LDRSBXui:
1133 case AArch64_LDRSHXui:
1134 case AArch64_LDRSWui:
1135 case AArch64_STRXui:
1136 case AArch64_LDRXui:
1137 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1138 break;
1139
1140 case AArch64_LDRQui:
1141 case AArch64_STRQui:
1142 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1143 break;
1144
1145 case AArch64_LDRDui:
1146 case AArch64_STRDui:
1147 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1148 break;
1149
1150 case AArch64_LDRSui:
1151 case AArch64_STRSui:
1152 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1153 break;
1154
1155 case AArch64_LDRHui:
1156 case AArch64_STRHui:
1157 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1158 break;
1159
1160 case AArch64_LDRBui:
1161 case AArch64_STRBui:
1162 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1163 break;
1164 }
1165
1166 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1167
1168 //if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
1169 MCOperand_CreateImm0(Inst, offset);
1170
1171 return Success;
1172 }
1173
DecodeSignedLdStInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1174 static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
1175 uint32_t insn, uint64_t Addr, const void *Decoder)
1176 {
1177 bool IsLoad, IsIndexed, IsFP;
1178 unsigned Rt = fieldFromInstruction_4(insn, 0, 5);
1179 unsigned Rn = fieldFromInstruction_4(insn, 5, 5);
1180 int64_t offset = fieldFromInstruction_4(insn, 12, 9);
1181
1182 // offset is a 9-bit signed immediate, so sign extend it to
1183 // fill the unsigned.
1184 if (offset & (1 << (9 - 1)))
1185 offset |= ~((1LL << 9) - 1);
1186
1187 // First operand is always the writeback to the address register, if needed.
1188 switch (MCInst_getOpcode(Inst)) {
1189 default:
1190 break;
1191
1192 case AArch64_LDRSBWpre:
1193 case AArch64_LDRSHWpre:
1194 case AArch64_STRBBpre:
1195 case AArch64_LDRBBpre:
1196 case AArch64_STRHHpre:
1197 case AArch64_LDRHHpre:
1198 case AArch64_STRWpre:
1199 case AArch64_LDRWpre:
1200 case AArch64_LDRSBWpost:
1201 case AArch64_LDRSHWpost:
1202 case AArch64_STRBBpost:
1203 case AArch64_LDRBBpost:
1204 case AArch64_STRHHpost:
1205 case AArch64_LDRHHpost:
1206 case AArch64_STRWpost:
1207 case AArch64_LDRWpost:
1208 case AArch64_LDRSBXpre:
1209 case AArch64_LDRSHXpre:
1210 case AArch64_STRXpre:
1211 case AArch64_LDRSWpre:
1212 case AArch64_LDRXpre:
1213 case AArch64_LDRSBXpost:
1214 case AArch64_LDRSHXpost:
1215 case AArch64_STRXpost:
1216 case AArch64_LDRSWpost:
1217 case AArch64_LDRXpost:
1218 case AArch64_LDRQpre:
1219 case AArch64_STRQpre:
1220 case AArch64_LDRQpost:
1221 case AArch64_STRQpost:
1222 case AArch64_LDRDpre:
1223 case AArch64_STRDpre:
1224 case AArch64_LDRDpost:
1225 case AArch64_STRDpost:
1226 case AArch64_LDRSpre:
1227 case AArch64_STRSpre:
1228 case AArch64_LDRSpost:
1229 case AArch64_STRSpost:
1230 case AArch64_LDRHpre:
1231 case AArch64_STRHpre:
1232 case AArch64_LDRHpost:
1233 case AArch64_STRHpost:
1234 case AArch64_LDRBpre:
1235 case AArch64_STRBpre:
1236 case AArch64_LDRBpost:
1237 case AArch64_STRBpost:
1238 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1239 break;
1240 }
1241
1242 switch (MCInst_getOpcode(Inst)) {
1243 default:
1244 return Fail;
1245
1246 case AArch64_PRFUMi:
1247 // Rt is an immediate in prefetch.
1248 MCOperand_CreateImm0(Inst, Rt);
1249 break;
1250
1251 case AArch64_STURBBi:
1252 case AArch64_LDURBBi:
1253 case AArch64_LDURSBWi:
1254 case AArch64_STURHHi:
1255 case AArch64_LDURHHi:
1256 case AArch64_LDURSHWi:
1257 case AArch64_STURWi:
1258 case AArch64_LDURWi:
1259 case AArch64_LDTRSBWi:
1260 case AArch64_LDTRSHWi:
1261 case AArch64_STTRWi:
1262 case AArch64_LDTRWi:
1263 case AArch64_STTRHi:
1264 case AArch64_LDTRHi:
1265 case AArch64_LDTRBi:
1266 case AArch64_STTRBi:
1267 case AArch64_LDRSBWpre:
1268 case AArch64_LDRSHWpre:
1269 case AArch64_STRBBpre:
1270 case AArch64_LDRBBpre:
1271 case AArch64_STRHHpre:
1272 case AArch64_LDRHHpre:
1273 case AArch64_STRWpre:
1274 case AArch64_LDRWpre:
1275 case AArch64_LDRSBWpost:
1276 case AArch64_LDRSHWpost:
1277 case AArch64_STRBBpost:
1278 case AArch64_LDRBBpost:
1279 case AArch64_STRHHpost:
1280 case AArch64_LDRHHpost:
1281 case AArch64_STRWpost:
1282 case AArch64_LDRWpost:
1283 case AArch64_STLURBi:
1284 case AArch64_STLURHi:
1285 case AArch64_STLURWi:
1286 case AArch64_LDAPURBi:
1287 case AArch64_LDAPURSBWi:
1288 case AArch64_LDAPURHi:
1289 case AArch64_LDAPURSHWi:
1290 case AArch64_LDAPURi:
1291 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1292 break;
1293
1294 case AArch64_LDURSBXi:
1295 case AArch64_LDURSHXi:
1296 case AArch64_LDURSWi:
1297 case AArch64_STURXi:
1298 case AArch64_LDURXi:
1299 case AArch64_LDTRSBXi:
1300 case AArch64_LDTRSHXi:
1301 case AArch64_LDTRSWi:
1302 case AArch64_STTRXi:
1303 case AArch64_LDTRXi:
1304 case AArch64_LDRSBXpre:
1305 case AArch64_LDRSHXpre:
1306 case AArch64_STRXpre:
1307 case AArch64_LDRSWpre:
1308 case AArch64_LDRXpre:
1309 case AArch64_LDRSBXpost:
1310 case AArch64_LDRSHXpost:
1311 case AArch64_STRXpost:
1312 case AArch64_LDRSWpost:
1313 case AArch64_LDRXpost:
1314 case AArch64_LDAPURSWi:
1315 case AArch64_LDAPURSHXi:
1316 case AArch64_LDAPURSBXi:
1317 case AArch64_STLURXi:
1318 case AArch64_LDAPURXi:
1319 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1320 break;
1321
1322 case AArch64_LDURQi:
1323 case AArch64_STURQi:
1324 case AArch64_LDRQpre:
1325 case AArch64_STRQpre:
1326 case AArch64_LDRQpost:
1327 case AArch64_STRQpost:
1328 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1329 break;
1330
1331 case AArch64_LDURDi:
1332 case AArch64_STURDi:
1333 case AArch64_LDRDpre:
1334 case AArch64_STRDpre:
1335 case AArch64_LDRDpost:
1336 case AArch64_STRDpost:
1337 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1338 break;
1339
1340 case AArch64_LDURSi:
1341 case AArch64_STURSi:
1342 case AArch64_LDRSpre:
1343 case AArch64_STRSpre:
1344 case AArch64_LDRSpost:
1345 case AArch64_STRSpost:
1346 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1347 break;
1348
1349 case AArch64_LDURHi:
1350 case AArch64_STURHi:
1351 case AArch64_LDRHpre:
1352 case AArch64_STRHpre:
1353 case AArch64_LDRHpost:
1354 case AArch64_STRHpost:
1355 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1356 break;
1357
1358 case AArch64_LDURBi:
1359 case AArch64_STURBi:
1360 case AArch64_LDRBpre:
1361 case AArch64_STRBpre:
1362 case AArch64_LDRBpost:
1363 case AArch64_STRBpost:
1364 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1365 break;
1366 }
1367
1368 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1369 MCOperand_CreateImm0(Inst, offset);
1370
1371 IsLoad = fieldFromInstruction_4(insn, 22, 1) != 0;
1372 IsIndexed = fieldFromInstruction_4(insn, 10, 2) != 0;
1373 IsFP = fieldFromInstruction_4(insn, 26, 1) != 0;
1374
1375 // Cannot write back to a transfer register (but xzr != sp).
1376 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1377 return SoftFail;
1378
1379 return Success;
1380 }
1381
DecodeExclusiveLdStInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1382 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
1383 uint32_t insn, uint64_t Addr, const void *Decoder)
1384 {
1385 unsigned Rt = fieldFromInstruction_4(insn, 0, 5);
1386 unsigned Rn = fieldFromInstruction_4(insn, 5, 5);
1387 unsigned Rt2 = fieldFromInstruction_4(insn, 10, 5);
1388 unsigned Rs = fieldFromInstruction_4(insn, 16, 5);
1389 unsigned Opcode = MCInst_getOpcode(Inst);
1390
1391 switch (Opcode) {
1392 default:
1393 return Fail;
1394
1395 case AArch64_STLXRW:
1396 case AArch64_STLXRB:
1397 case AArch64_STLXRH:
1398 case AArch64_STXRW:
1399 case AArch64_STXRB:
1400 case AArch64_STXRH:
1401 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1402 // FALLTHROUGH
1403 case AArch64_LDARW:
1404 case AArch64_LDARB:
1405 case AArch64_LDARH:
1406 case AArch64_LDAXRW:
1407 case AArch64_LDAXRB:
1408 case AArch64_LDAXRH:
1409 case AArch64_LDXRW:
1410 case AArch64_LDXRB:
1411 case AArch64_LDXRH:
1412 case AArch64_STLRW:
1413 case AArch64_STLRB:
1414 case AArch64_STLRH:
1415 case AArch64_STLLRW:
1416 case AArch64_STLLRB:
1417 case AArch64_STLLRH:
1418 case AArch64_LDLARW:
1419 case AArch64_LDLARB:
1420 case AArch64_LDLARH:
1421 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1422 break;
1423
1424 case AArch64_STLXRX:
1425 case AArch64_STXRX:
1426 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1427 // FALLTHROUGH
1428 case AArch64_LDARX:
1429 case AArch64_LDAXRX:
1430 case AArch64_LDXRX:
1431 case AArch64_STLRX:
1432 case AArch64_LDLARX:
1433 case AArch64_STLLRX:
1434 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1435 break;
1436
1437 case AArch64_STLXPW:
1438 case AArch64_STXPW:
1439 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1440 // FALLTHROUGH
1441 case AArch64_LDAXPW:
1442 case AArch64_LDXPW:
1443 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1444 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1445 break;
1446
1447 case AArch64_STLXPX:
1448 case AArch64_STXPX:
1449 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1450 // FALLTHROUGH
1451 case AArch64_LDAXPX:
1452 case AArch64_LDXPX:
1453 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1454 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1455 break;
1456 }
1457
1458 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1459
1460 // You shouldn't load to the same register twice in an instruction...
1461 if ((Opcode == AArch64_LDAXPW || Opcode == AArch64_LDXPW ||
1462 Opcode == AArch64_LDAXPX || Opcode == AArch64_LDXPX) &&
1463 Rt == Rt2)
1464 return SoftFail;
1465
1466 return Success;
1467 }
1468
DecodePairLdStInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1469 static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
1470 uint64_t Addr, const void *Decoder)
1471 {
1472 unsigned Rt = fieldFromInstruction_4(insn, 0, 5);
1473 unsigned Rn = fieldFromInstruction_4(insn, 5, 5);
1474 unsigned Rt2 = fieldFromInstruction_4(insn, 10, 5);
1475 int32_t offset = fieldFromInstruction_4(insn, 15, 7);
1476 bool IsLoad = fieldFromInstruction_4(insn, 22, 1) != 0;
1477 unsigned Opcode = MCInst_getOpcode(Inst);
1478 bool NeedsDisjointWritebackTransfer = false;
1479
1480 // offset is a 7-bit signed immediate, so sign extend it to
1481 // fill the unsigned.
1482 if (offset & (1 << (7 - 1)))
1483 offset |= ~((1LL << 7) - 1);
1484
1485 // First operand is always writeback of base register.
1486 switch (Opcode) {
1487 default:
1488 break;
1489
1490 case AArch64_LDPXpost:
1491 case AArch64_STPXpost:
1492 case AArch64_LDPSWpost:
1493 case AArch64_LDPXpre:
1494 case AArch64_STPXpre:
1495 case AArch64_LDPSWpre:
1496 case AArch64_LDPWpost:
1497 case AArch64_STPWpost:
1498 case AArch64_LDPWpre:
1499 case AArch64_STPWpre:
1500 case AArch64_LDPQpost:
1501 case AArch64_STPQpost:
1502 case AArch64_LDPQpre:
1503 case AArch64_STPQpre:
1504 case AArch64_LDPDpost:
1505 case AArch64_STPDpost:
1506 case AArch64_LDPDpre:
1507 case AArch64_STPDpre:
1508 case AArch64_LDPSpost:
1509 case AArch64_STPSpost:
1510 case AArch64_LDPSpre:
1511 case AArch64_STPSpre:
1512 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1513 break;
1514 }
1515
1516 switch (Opcode) {
1517 default:
1518 return Fail;
1519
1520 case AArch64_LDPXpost:
1521 case AArch64_STPXpost:
1522 case AArch64_LDPSWpost:
1523 case AArch64_LDPXpre:
1524 case AArch64_STPXpre:
1525 case AArch64_LDPSWpre:
1526 NeedsDisjointWritebackTransfer = true;
1527 // Fallthrough
1528 case AArch64_LDNPXi:
1529 case AArch64_STNPXi:
1530 case AArch64_LDPXi:
1531 case AArch64_STPXi:
1532 case AArch64_LDPSWi:
1533 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1534 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1535 break;
1536
1537 case AArch64_LDPWpost:
1538 case AArch64_STPWpost:
1539 case AArch64_LDPWpre:
1540 case AArch64_STPWpre:
1541 NeedsDisjointWritebackTransfer = true;
1542 // Fallthrough
1543 case AArch64_LDNPWi:
1544 case AArch64_STNPWi:
1545 case AArch64_LDPWi:
1546 case AArch64_STPWi:
1547 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1548 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1549 break;
1550
1551 case AArch64_LDNPQi:
1552 case AArch64_STNPQi:
1553 case AArch64_LDPQpost:
1554 case AArch64_STPQpost:
1555 case AArch64_LDPQi:
1556 case AArch64_STPQi:
1557 case AArch64_LDPQpre:
1558 case AArch64_STPQpre:
1559 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1560 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1561 break;
1562
1563 case AArch64_LDNPDi:
1564 case AArch64_STNPDi:
1565 case AArch64_LDPDpost:
1566 case AArch64_STPDpost:
1567 case AArch64_LDPDi:
1568 case AArch64_STPDi:
1569 case AArch64_LDPDpre:
1570 case AArch64_STPDpre:
1571 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1572 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1573 break;
1574
1575 case AArch64_LDNPSi:
1576 case AArch64_STNPSi:
1577 case AArch64_LDPSpost:
1578 case AArch64_STPSpost:
1579 case AArch64_LDPSi:
1580 case AArch64_STPSi:
1581 case AArch64_LDPSpre:
1582 case AArch64_STPSpre:
1583 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1584 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1585 break;
1586 }
1587
1588 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1589 MCOperand_CreateImm0(Inst, offset);
1590
1591 // You shouldn't load to the same register twice in an instruction...
1592 if (IsLoad && Rt == Rt2)
1593 return SoftFail;
1594
1595 // ... or do any operation that writes-back to a transfer register. But note
1596 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1597 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1598 return SoftFail;
1599
1600 return Success;
1601 }
1602
DecodeAddSubERegInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1603 static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
1604 uint32_t insn, uint64_t Addr, const void *Decoder)
1605 {
1606 unsigned Rd, Rn, Rm;
1607 unsigned extend = fieldFromInstruction_4(insn, 10, 6);
1608 unsigned shift = extend & 0x7;
1609
1610 if (shift > 4)
1611 return Fail;
1612
1613 Rd = fieldFromInstruction_4(insn, 0, 5);
1614 Rn = fieldFromInstruction_4(insn, 5, 5);
1615 Rm = fieldFromInstruction_4(insn, 16, 5);
1616
1617 switch (MCInst_getOpcode(Inst)) {
1618 default:
1619 return Fail;
1620
1621 case AArch64_ADDWrx:
1622 case AArch64_SUBWrx:
1623 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1624 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1625 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1626 break;
1627
1628 case AArch64_ADDSWrx:
1629 case AArch64_SUBSWrx:
1630 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1631 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1632 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1633 break;
1634
1635 case AArch64_ADDXrx:
1636 case AArch64_SUBXrx:
1637 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1638 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1639 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1640 break;
1641
1642 case AArch64_ADDSXrx:
1643 case AArch64_SUBSXrx:
1644 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1645 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1646 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1647 break;
1648
1649 case AArch64_ADDXrx64:
1650 case AArch64_SUBXrx64:
1651 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1652 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1653 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1654 break;
1655
1656 case AArch64_SUBSXrx64:
1657 case AArch64_ADDSXrx64:
1658 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1659 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1660 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1661 break;
1662 }
1663
1664 MCOperand_CreateImm0(Inst, extend);
1665
1666 return Success;
1667 }
1668
DecodeLogicalImmInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1669 static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
1670 uint32_t insn, uint64_t Addr, const void *Decoder)
1671 {
1672 unsigned Rd = fieldFromInstruction_4(insn, 0, 5);
1673 unsigned Rn = fieldFromInstruction_4(insn, 5, 5);
1674 unsigned Datasize = fieldFromInstruction_4(insn, 31, 1);
1675 unsigned imm;
1676
1677 if (Datasize) {
1678 if (MCInst_getOpcode(Inst) == AArch64_ANDSXri)
1679 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1680 else
1681 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1682
1683 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1684
1685 imm = fieldFromInstruction_4(insn, 10, 13);
1686 if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64))
1687 return Fail;
1688 } else {
1689 if (MCInst_getOpcode(Inst) == AArch64_ANDSWri)
1690 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1691 else
1692 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1693
1694 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1695
1696 imm = fieldFromInstruction_4(insn, 10, 12);
1697 if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 32))
1698 return Fail;
1699 }
1700
1701 MCOperand_CreateImm0(Inst, imm);
1702
1703 return Success;
1704 }
1705
DecodeModImmInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1706 static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
1707 uint64_t Addr, const void *Decoder)
1708 {
1709 unsigned Rd = fieldFromInstruction_4(insn, 0, 5);
1710 unsigned cmode = fieldFromInstruction_4(insn, 12, 4);
1711 unsigned imm = fieldFromInstruction_4(insn, 16, 3) << 5;
1712 imm |= fieldFromInstruction_4(insn, 5, 5);
1713
1714 if (MCInst_getOpcode(Inst) == AArch64_MOVID)
1715 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1716 else
1717 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1718
1719 MCOperand_CreateImm0(Inst, imm);
1720
1721 switch (MCInst_getOpcode(Inst)) {
1722 default:
1723 break;
1724
1725 case AArch64_MOVIv4i16:
1726 case AArch64_MOVIv8i16:
1727 case AArch64_MVNIv4i16:
1728 case AArch64_MVNIv8i16:
1729 case AArch64_MOVIv2i32:
1730 case AArch64_MOVIv4i32:
1731 case AArch64_MVNIv2i32:
1732 case AArch64_MVNIv4i32:
1733 MCOperand_CreateImm0(Inst, (cmode & 6) << 2);
1734 break;
1735
1736 case AArch64_MOVIv2s_msl:
1737 case AArch64_MOVIv4s_msl:
1738 case AArch64_MVNIv2s_msl:
1739 case AArch64_MVNIv4s_msl:
1740 MCOperand_CreateImm0(Inst, cmode & 1 ? 0x110 : 0x108);
1741 break;
1742 }
1743
1744 return Success;
1745 }
1746
DecodeModImmTiedInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1747 static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
1748 uint32_t insn, uint64_t Addr, const void *Decoder)
1749 {
1750 unsigned Rd = fieldFromInstruction_4(insn, 0, 5);
1751 unsigned cmode = fieldFromInstruction_4(insn, 12, 4);
1752 unsigned imm = fieldFromInstruction_4(insn, 16, 3) << 5;
1753 imm |= fieldFromInstruction_4(insn, 5, 5);
1754
1755 // Tied operands added twice.
1756 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1757 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1758
1759 MCOperand_CreateImm0(Inst, imm);
1760 MCOperand_CreateImm0(Inst, (cmode & 6) << 2);
1761
1762 return Success;
1763 }
1764
DecodeAdrInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1765 static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
1766 uint64_t Addr, const void *Decoder)
1767 {
1768 unsigned Rd = fieldFromInstruction_4(insn, 0, 5);
1769 int64_t imm = fieldFromInstruction_4(insn, 5, 19) << 2;
1770 imm |= fieldFromInstruction_4(insn, 29, 2);
1771
1772 // Sign-extend the 21-bit immediate.
1773 if (imm & (1 << (21 - 1)))
1774 imm |= ~((1LL << 21) - 1);
1775
1776 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1777 //if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1778 MCOperand_CreateImm0(Inst, imm);
1779
1780 return Success;
1781 }
1782
DecodeBaseAddSubImm(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1783 static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
1784 uint64_t Addr, const void *Decoder)
1785 {
1786 unsigned Rd = fieldFromInstruction_4(insn, 0, 5);
1787 unsigned Rn = fieldFromInstruction_4(insn, 5, 5);
1788 unsigned Imm = fieldFromInstruction_4(insn, 10, 14);
1789 unsigned S = fieldFromInstruction_4(insn, 29, 1);
1790 unsigned Datasize = fieldFromInstruction_4(insn, 31, 1);
1791
1792 unsigned ShifterVal = (Imm >> 12) & 3;
1793 unsigned ImmVal = Imm & 0xFFF;
1794
1795 if (ShifterVal != 0 && ShifterVal != 1)
1796 return Fail;
1797
1798 if (Datasize) {
1799 if (Rd == 31 && !S)
1800 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1801 else
1802 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1803
1804 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1805 } else {
1806 if (Rd == 31 && !S)
1807 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1808 else
1809 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1810
1811 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1812 }
1813
1814 //if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1815 MCOperand_CreateImm0(Inst, ImmVal);
1816 MCOperand_CreateImm0(Inst, 12 * ShifterVal);
1817
1818 return Success;
1819 }
1820
DecodeUnconditionalBranch(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1821 static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
1822 uint64_t Addr, const void *Decoder)
1823 {
1824 int64_t imm = fieldFromInstruction_4(insn, 0, 26);
1825
1826 // Sign-extend the 26-bit immediate.
1827 if (imm & (1 << (26 - 1)))
1828 imm |= ~((1LL << 26) - 1);
1829
1830 // if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4))
1831 MCOperand_CreateImm0(Inst, imm);
1832
1833 return Success;
1834 }
1835
DecodeSystemPStateInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1836 static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
1837 uint32_t insn, uint64_t Addr, const void *Decoder)
1838 {
1839 uint32_t op1 = fieldFromInstruction_4(insn, 16, 3);
1840 uint32_t op2 = fieldFromInstruction_4(insn, 5, 3);
1841 uint32_t crm = fieldFromInstruction_4(insn, 8, 4);
1842 uint32_t pstate_field = (op1 << 3) | op2;
1843
1844 if ((pstate_field == AArch64PState_PAN ||
1845 pstate_field == AArch64PState_UAO) && crm > 1)
1846 return Fail;
1847
1848 MCOperand_CreateImm0(Inst, pstate_field);
1849 MCOperand_CreateImm0(Inst, crm);
1850
1851 if (lookupPStateByEncoding(pstate_field))
1852 return Success;
1853
1854 return Fail;
1855 }
1856
DecodeTestAndBranch(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1857 static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
1858 uint64_t Addr, const void *Decoder)
1859 {
1860 uint32_t Rt = fieldFromInstruction_4(insn, 0, 5);
1861 uint32_t bit = fieldFromInstruction_4(insn, 31, 1) << 5;
1862 uint64_t dst = fieldFromInstruction_4(insn, 5, 14);
1863
1864 bit |= fieldFromInstruction_4(insn, 19, 5);
1865
1866 // Sign-extend 14-bit immediate.
1867 if (dst & (1 << (14 - 1)))
1868 dst |= ~((1LL << 14) - 1);
1869
1870 if (fieldFromInstruction_4(insn, 31, 1) == 0)
1871 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1872 else
1873 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1874
1875 MCOperand_CreateImm0(Inst, bit);
1876
1877 //if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4))
1878 MCOperand_CreateImm0(Inst, dst);
1879
1880 return Success;
1881 }
1882
DecodeGPRSeqPairsClassRegisterClass(MCInst * Inst,unsigned RegClassID,unsigned RegNo,uint64_t Addr,const void * Decoder)1883 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst *Inst,
1884 unsigned RegClassID, unsigned RegNo, uint64_t Addr, const void *Decoder)
1885 {
1886 unsigned Register;
1887
1888 // Register number must be even (see CASP instruction)
1889 if (RegNo & 0x1)
1890 return Fail;
1891
1892 Register = AArch64MCRegisterClasses[RegClassID].RegsBegin[RegNo];
1893 MCOperand_CreateReg0(Inst, Register);
1894
1895 return Success;
1896 }
1897
DecodeWSeqPairsClassRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)1898 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst *Inst,
1899 unsigned RegNo, uint64_t Addr, const void *Decoder)
1900 {
1901 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1902 AArch64_WSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1903 }
1904
DecodeXSeqPairsClassRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Addr,const void * Decoder)1905 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst *Inst,
1906 unsigned RegNo, uint64_t Addr, const void *Decoder)
1907 {
1908 return DecodeGPRSeqPairsClassRegisterClass(Inst,
1909 AArch64_XSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1910 }
1911
DecodeSVELogicalImmInstruction(MCInst * Inst,uint32_t insn,uint64_t Addr,const void * Decoder)1912 static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn,
1913 uint64_t Addr, const void *Decoder)
1914 {
1915 unsigned Zdn = fieldFromInstruction_4(insn, 0, 5);
1916 unsigned imm = fieldFromInstruction_4(insn, 5, 13);
1917
1918 if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64))
1919 return Fail;
1920
1921 // The same (tied) operand is added twice to the instruction.
1922 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1923 if (MCInst_getOpcode(Inst) != AArch64_DUPM_ZI)
1924 DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1925
1926 MCOperand_CreateImm0(Inst, imm);
1927
1928 return Success;
1929 }
1930
DecodeSImm(MCInst * Inst,uint64_t Imm,uint64_t Address,const void * Decoder,int Bits)1931 static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address,
1932 const void *Decoder, int Bits)
1933 {
1934 if (Imm & ~((1LL << Bits) - 1))
1935 return Fail;
1936
1937 // Imm is a signed immediate, so sign extend it.
1938 if (Imm & (1 << (Bits - 1)))
1939 Imm |= ~((1LL << Bits) - 1);
1940
1941 MCOperand_CreateImm0(Inst, Imm);
1942
1943 return Success;
1944 }
1945
1946 // Decode 8-bit signed/unsigned immediate for a given element width.
DecodeImm8OptLsl(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder,int ElementWidth)1947 static DecodeStatus DecodeImm8OptLsl(MCInst *Inst, unsigned Imm, uint64_t Addr,
1948 const void *Decoder, int ElementWidth)
1949 {
1950 unsigned Val = (uint8_t)Imm;
1951 unsigned Shift = (Imm & 0x100) ? 8 : 0;
1952
1953 if (ElementWidth == 8 && Shift)
1954 return Fail;
1955
1956 MCOperand_CreateImm0(Inst, Val);
1957 MCOperand_CreateImm0(Inst, Shift);
1958
1959 return Success;
1960 }
1961
1962 // Decode uimm4 ranged from 1-16.
DecodeSVEIncDecImm(MCInst * Inst,unsigned Imm,uint64_t Addr,const void * Decoder)1963 static DecodeStatus DecodeSVEIncDecImm(MCInst *Inst, unsigned Imm,
1964 uint64_t Addr, const void *Decoder)
1965 {
1966 MCOperand_CreateImm0(Inst, Imm + 1);
1967
1968 return Success;
1969 }
1970
AArch64_init(MCRegisterInfo * MRI)1971 void AArch64_init(MCRegisterInfo *MRI)
1972 {
1973 /*
1974 InitMCRegisterInfo(AArch64RegDesc, 661,
1975 RA, PC,
1976 AArch64MCRegisterClasses, 100,
1977 AArch64RegUnitRoots, 115, AArch64RegDiffLists,
1978 AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings,
1979 AArch64SubRegIdxLists, 100,
1980 AArch64SubRegIdxRanges, AArch64RegEncodingTable);
1981 */
1982
1983 MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 661,
1984 0, 0,
1985 AArch64MCRegisterClasses, 100,
1986 0, 0, AArch64RegDiffLists,
1987 0,
1988 AArch64SubRegIdxLists, 100,
1989 0);
1990 }
1991
1992 #endif
1993