1
2/* Capstone Disassembly Engine, http://www.capstone-engine.org */
3/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
4
5/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
6|*                                                                            *|
7|* Target Register Enum Values                                                *|
8|*                                                                            *|
9|* Automatically generated file, do not edit!                                 *|
10|*                                                                            *|
11\*===----------------------------------------------------------------------===*/
12
13#ifdef GET_REGINFO_ENUM
14#undef GET_REGINFO_ENUM
15
16enum {
17  AArch64_NoRegister,
18  AArch64_FFR = 1,
19  AArch64_FP = 2,
20  AArch64_LR = 3,
21  AArch64_NZCV = 4,
22  AArch64_SP = 5,
23  AArch64_WSP = 6,
24  AArch64_WZR = 7,
25  AArch64_XZR = 8,
26  AArch64_B0 = 9,
27  AArch64_B1 = 10,
28  AArch64_B2 = 11,
29  AArch64_B3 = 12,
30  AArch64_B4 = 13,
31  AArch64_B5 = 14,
32  AArch64_B6 = 15,
33  AArch64_B7 = 16,
34  AArch64_B8 = 17,
35  AArch64_B9 = 18,
36  AArch64_B10 = 19,
37  AArch64_B11 = 20,
38  AArch64_B12 = 21,
39  AArch64_B13 = 22,
40  AArch64_B14 = 23,
41  AArch64_B15 = 24,
42  AArch64_B16 = 25,
43  AArch64_B17 = 26,
44  AArch64_B18 = 27,
45  AArch64_B19 = 28,
46  AArch64_B20 = 29,
47  AArch64_B21 = 30,
48  AArch64_B22 = 31,
49  AArch64_B23 = 32,
50  AArch64_B24 = 33,
51  AArch64_B25 = 34,
52  AArch64_B26 = 35,
53  AArch64_B27 = 36,
54  AArch64_B28 = 37,
55  AArch64_B29 = 38,
56  AArch64_B30 = 39,
57  AArch64_B31 = 40,
58  AArch64_D0 = 41,
59  AArch64_D1 = 42,
60  AArch64_D2 = 43,
61  AArch64_D3 = 44,
62  AArch64_D4 = 45,
63  AArch64_D5 = 46,
64  AArch64_D6 = 47,
65  AArch64_D7 = 48,
66  AArch64_D8 = 49,
67  AArch64_D9 = 50,
68  AArch64_D10 = 51,
69  AArch64_D11 = 52,
70  AArch64_D12 = 53,
71  AArch64_D13 = 54,
72  AArch64_D14 = 55,
73  AArch64_D15 = 56,
74  AArch64_D16 = 57,
75  AArch64_D17 = 58,
76  AArch64_D18 = 59,
77  AArch64_D19 = 60,
78  AArch64_D20 = 61,
79  AArch64_D21 = 62,
80  AArch64_D22 = 63,
81  AArch64_D23 = 64,
82  AArch64_D24 = 65,
83  AArch64_D25 = 66,
84  AArch64_D26 = 67,
85  AArch64_D27 = 68,
86  AArch64_D28 = 69,
87  AArch64_D29 = 70,
88  AArch64_D30 = 71,
89  AArch64_D31 = 72,
90  AArch64_H0 = 73,
91  AArch64_H1 = 74,
92  AArch64_H2 = 75,
93  AArch64_H3 = 76,
94  AArch64_H4 = 77,
95  AArch64_H5 = 78,
96  AArch64_H6 = 79,
97  AArch64_H7 = 80,
98  AArch64_H8 = 81,
99  AArch64_H9 = 82,
100  AArch64_H10 = 83,
101  AArch64_H11 = 84,
102  AArch64_H12 = 85,
103  AArch64_H13 = 86,
104  AArch64_H14 = 87,
105  AArch64_H15 = 88,
106  AArch64_H16 = 89,
107  AArch64_H17 = 90,
108  AArch64_H18 = 91,
109  AArch64_H19 = 92,
110  AArch64_H20 = 93,
111  AArch64_H21 = 94,
112  AArch64_H22 = 95,
113  AArch64_H23 = 96,
114  AArch64_H24 = 97,
115  AArch64_H25 = 98,
116  AArch64_H26 = 99,
117  AArch64_H27 = 100,
118  AArch64_H28 = 101,
119  AArch64_H29 = 102,
120  AArch64_H30 = 103,
121  AArch64_H31 = 104,
122  AArch64_P0 = 105,
123  AArch64_P1 = 106,
124  AArch64_P2 = 107,
125  AArch64_P3 = 108,
126  AArch64_P4 = 109,
127  AArch64_P5 = 110,
128  AArch64_P6 = 111,
129  AArch64_P7 = 112,
130  AArch64_P8 = 113,
131  AArch64_P9 = 114,
132  AArch64_P10 = 115,
133  AArch64_P11 = 116,
134  AArch64_P12 = 117,
135  AArch64_P13 = 118,
136  AArch64_P14 = 119,
137  AArch64_P15 = 120,
138  AArch64_Q0 = 121,
139  AArch64_Q1 = 122,
140  AArch64_Q2 = 123,
141  AArch64_Q3 = 124,
142  AArch64_Q4 = 125,
143  AArch64_Q5 = 126,
144  AArch64_Q6 = 127,
145  AArch64_Q7 = 128,
146  AArch64_Q8 = 129,
147  AArch64_Q9 = 130,
148  AArch64_Q10 = 131,
149  AArch64_Q11 = 132,
150  AArch64_Q12 = 133,
151  AArch64_Q13 = 134,
152  AArch64_Q14 = 135,
153  AArch64_Q15 = 136,
154  AArch64_Q16 = 137,
155  AArch64_Q17 = 138,
156  AArch64_Q18 = 139,
157  AArch64_Q19 = 140,
158  AArch64_Q20 = 141,
159  AArch64_Q21 = 142,
160  AArch64_Q22 = 143,
161  AArch64_Q23 = 144,
162  AArch64_Q24 = 145,
163  AArch64_Q25 = 146,
164  AArch64_Q26 = 147,
165  AArch64_Q27 = 148,
166  AArch64_Q28 = 149,
167  AArch64_Q29 = 150,
168  AArch64_Q30 = 151,
169  AArch64_Q31 = 152,
170  AArch64_S0 = 153,
171  AArch64_S1 = 154,
172  AArch64_S2 = 155,
173  AArch64_S3 = 156,
174  AArch64_S4 = 157,
175  AArch64_S5 = 158,
176  AArch64_S6 = 159,
177  AArch64_S7 = 160,
178  AArch64_S8 = 161,
179  AArch64_S9 = 162,
180  AArch64_S10 = 163,
181  AArch64_S11 = 164,
182  AArch64_S12 = 165,
183  AArch64_S13 = 166,
184  AArch64_S14 = 167,
185  AArch64_S15 = 168,
186  AArch64_S16 = 169,
187  AArch64_S17 = 170,
188  AArch64_S18 = 171,
189  AArch64_S19 = 172,
190  AArch64_S20 = 173,
191  AArch64_S21 = 174,
192  AArch64_S22 = 175,
193  AArch64_S23 = 176,
194  AArch64_S24 = 177,
195  AArch64_S25 = 178,
196  AArch64_S26 = 179,
197  AArch64_S27 = 180,
198  AArch64_S28 = 181,
199  AArch64_S29 = 182,
200  AArch64_S30 = 183,
201  AArch64_S31 = 184,
202  AArch64_W0 = 185,
203  AArch64_W1 = 186,
204  AArch64_W2 = 187,
205  AArch64_W3 = 188,
206  AArch64_W4 = 189,
207  AArch64_W5 = 190,
208  AArch64_W6 = 191,
209  AArch64_W7 = 192,
210  AArch64_W8 = 193,
211  AArch64_W9 = 194,
212  AArch64_W10 = 195,
213  AArch64_W11 = 196,
214  AArch64_W12 = 197,
215  AArch64_W13 = 198,
216  AArch64_W14 = 199,
217  AArch64_W15 = 200,
218  AArch64_W16 = 201,
219  AArch64_W17 = 202,
220  AArch64_W18 = 203,
221  AArch64_W19 = 204,
222  AArch64_W20 = 205,
223  AArch64_W21 = 206,
224  AArch64_W22 = 207,
225  AArch64_W23 = 208,
226  AArch64_W24 = 209,
227  AArch64_W25 = 210,
228  AArch64_W26 = 211,
229  AArch64_W27 = 212,
230  AArch64_W28 = 213,
231  AArch64_W29 = 214,
232  AArch64_W30 = 215,
233  AArch64_X0 = 216,
234  AArch64_X1 = 217,
235  AArch64_X2 = 218,
236  AArch64_X3 = 219,
237  AArch64_X4 = 220,
238  AArch64_X5 = 221,
239  AArch64_X6 = 222,
240  AArch64_X7 = 223,
241  AArch64_X8 = 224,
242  AArch64_X9 = 225,
243  AArch64_X10 = 226,
244  AArch64_X11 = 227,
245  AArch64_X12 = 228,
246  AArch64_X13 = 229,
247  AArch64_X14 = 230,
248  AArch64_X15 = 231,
249  AArch64_X16 = 232,
250  AArch64_X17 = 233,
251  AArch64_X18 = 234,
252  AArch64_X19 = 235,
253  AArch64_X20 = 236,
254  AArch64_X21 = 237,
255  AArch64_X22 = 238,
256  AArch64_X23 = 239,
257  AArch64_X24 = 240,
258  AArch64_X25 = 241,
259  AArch64_X26 = 242,
260  AArch64_X27 = 243,
261  AArch64_X28 = 244,
262  AArch64_Z0 = 245,
263  AArch64_Z1 = 246,
264  AArch64_Z2 = 247,
265  AArch64_Z3 = 248,
266  AArch64_Z4 = 249,
267  AArch64_Z5 = 250,
268  AArch64_Z6 = 251,
269  AArch64_Z7 = 252,
270  AArch64_Z8 = 253,
271  AArch64_Z9 = 254,
272  AArch64_Z10 = 255,
273  AArch64_Z11 = 256,
274  AArch64_Z12 = 257,
275  AArch64_Z13 = 258,
276  AArch64_Z14 = 259,
277  AArch64_Z15 = 260,
278  AArch64_Z16 = 261,
279  AArch64_Z17 = 262,
280  AArch64_Z18 = 263,
281  AArch64_Z19 = 264,
282  AArch64_Z20 = 265,
283  AArch64_Z21 = 266,
284  AArch64_Z22 = 267,
285  AArch64_Z23 = 268,
286  AArch64_Z24 = 269,
287  AArch64_Z25 = 270,
288  AArch64_Z26 = 271,
289  AArch64_Z27 = 272,
290  AArch64_Z28 = 273,
291  AArch64_Z29 = 274,
292  AArch64_Z30 = 275,
293  AArch64_Z31 = 276,
294  AArch64_Z0_HI = 277,
295  AArch64_Z1_HI = 278,
296  AArch64_Z2_HI = 279,
297  AArch64_Z3_HI = 280,
298  AArch64_Z4_HI = 281,
299  AArch64_Z5_HI = 282,
300  AArch64_Z6_HI = 283,
301  AArch64_Z7_HI = 284,
302  AArch64_Z8_HI = 285,
303  AArch64_Z9_HI = 286,
304  AArch64_Z10_HI = 287,
305  AArch64_Z11_HI = 288,
306  AArch64_Z12_HI = 289,
307  AArch64_Z13_HI = 290,
308  AArch64_Z14_HI = 291,
309  AArch64_Z15_HI = 292,
310  AArch64_Z16_HI = 293,
311  AArch64_Z17_HI = 294,
312  AArch64_Z18_HI = 295,
313  AArch64_Z19_HI = 296,
314  AArch64_Z20_HI = 297,
315  AArch64_Z21_HI = 298,
316  AArch64_Z22_HI = 299,
317  AArch64_Z23_HI = 300,
318  AArch64_Z24_HI = 301,
319  AArch64_Z25_HI = 302,
320  AArch64_Z26_HI = 303,
321  AArch64_Z27_HI = 304,
322  AArch64_Z28_HI = 305,
323  AArch64_Z29_HI = 306,
324  AArch64_Z30_HI = 307,
325  AArch64_Z31_HI = 308,
326  AArch64_D0_D1 = 309,
327  AArch64_D1_D2 = 310,
328  AArch64_D2_D3 = 311,
329  AArch64_D3_D4 = 312,
330  AArch64_D4_D5 = 313,
331  AArch64_D5_D6 = 314,
332  AArch64_D6_D7 = 315,
333  AArch64_D7_D8 = 316,
334  AArch64_D8_D9 = 317,
335  AArch64_D9_D10 = 318,
336  AArch64_D10_D11 = 319,
337  AArch64_D11_D12 = 320,
338  AArch64_D12_D13 = 321,
339  AArch64_D13_D14 = 322,
340  AArch64_D14_D15 = 323,
341  AArch64_D15_D16 = 324,
342  AArch64_D16_D17 = 325,
343  AArch64_D17_D18 = 326,
344  AArch64_D18_D19 = 327,
345  AArch64_D19_D20 = 328,
346  AArch64_D20_D21 = 329,
347  AArch64_D21_D22 = 330,
348  AArch64_D22_D23 = 331,
349  AArch64_D23_D24 = 332,
350  AArch64_D24_D25 = 333,
351  AArch64_D25_D26 = 334,
352  AArch64_D26_D27 = 335,
353  AArch64_D27_D28 = 336,
354  AArch64_D28_D29 = 337,
355  AArch64_D29_D30 = 338,
356  AArch64_D30_D31 = 339,
357  AArch64_D31_D0 = 340,
358  AArch64_D0_D1_D2_D3 = 341,
359  AArch64_D1_D2_D3_D4 = 342,
360  AArch64_D2_D3_D4_D5 = 343,
361  AArch64_D3_D4_D5_D6 = 344,
362  AArch64_D4_D5_D6_D7 = 345,
363  AArch64_D5_D6_D7_D8 = 346,
364  AArch64_D6_D7_D8_D9 = 347,
365  AArch64_D7_D8_D9_D10 = 348,
366  AArch64_D8_D9_D10_D11 = 349,
367  AArch64_D9_D10_D11_D12 = 350,
368  AArch64_D10_D11_D12_D13 = 351,
369  AArch64_D11_D12_D13_D14 = 352,
370  AArch64_D12_D13_D14_D15 = 353,
371  AArch64_D13_D14_D15_D16 = 354,
372  AArch64_D14_D15_D16_D17 = 355,
373  AArch64_D15_D16_D17_D18 = 356,
374  AArch64_D16_D17_D18_D19 = 357,
375  AArch64_D17_D18_D19_D20 = 358,
376  AArch64_D18_D19_D20_D21 = 359,
377  AArch64_D19_D20_D21_D22 = 360,
378  AArch64_D20_D21_D22_D23 = 361,
379  AArch64_D21_D22_D23_D24 = 362,
380  AArch64_D22_D23_D24_D25 = 363,
381  AArch64_D23_D24_D25_D26 = 364,
382  AArch64_D24_D25_D26_D27 = 365,
383  AArch64_D25_D26_D27_D28 = 366,
384  AArch64_D26_D27_D28_D29 = 367,
385  AArch64_D27_D28_D29_D30 = 368,
386  AArch64_D28_D29_D30_D31 = 369,
387  AArch64_D29_D30_D31_D0 = 370,
388  AArch64_D30_D31_D0_D1 = 371,
389  AArch64_D31_D0_D1_D2 = 372,
390  AArch64_D0_D1_D2 = 373,
391  AArch64_D1_D2_D3 = 374,
392  AArch64_D2_D3_D4 = 375,
393  AArch64_D3_D4_D5 = 376,
394  AArch64_D4_D5_D6 = 377,
395  AArch64_D5_D6_D7 = 378,
396  AArch64_D6_D7_D8 = 379,
397  AArch64_D7_D8_D9 = 380,
398  AArch64_D8_D9_D10 = 381,
399  AArch64_D9_D10_D11 = 382,
400  AArch64_D10_D11_D12 = 383,
401  AArch64_D11_D12_D13 = 384,
402  AArch64_D12_D13_D14 = 385,
403  AArch64_D13_D14_D15 = 386,
404  AArch64_D14_D15_D16 = 387,
405  AArch64_D15_D16_D17 = 388,
406  AArch64_D16_D17_D18 = 389,
407  AArch64_D17_D18_D19 = 390,
408  AArch64_D18_D19_D20 = 391,
409  AArch64_D19_D20_D21 = 392,
410  AArch64_D20_D21_D22 = 393,
411  AArch64_D21_D22_D23 = 394,
412  AArch64_D22_D23_D24 = 395,
413  AArch64_D23_D24_D25 = 396,
414  AArch64_D24_D25_D26 = 397,
415  AArch64_D25_D26_D27 = 398,
416  AArch64_D26_D27_D28 = 399,
417  AArch64_D27_D28_D29 = 400,
418  AArch64_D28_D29_D30 = 401,
419  AArch64_D29_D30_D31 = 402,
420  AArch64_D30_D31_D0 = 403,
421  AArch64_D31_D0_D1 = 404,
422  AArch64_Q0_Q1 = 405,
423  AArch64_Q1_Q2 = 406,
424  AArch64_Q2_Q3 = 407,
425  AArch64_Q3_Q4 = 408,
426  AArch64_Q4_Q5 = 409,
427  AArch64_Q5_Q6 = 410,
428  AArch64_Q6_Q7 = 411,
429  AArch64_Q7_Q8 = 412,
430  AArch64_Q8_Q9 = 413,
431  AArch64_Q9_Q10 = 414,
432  AArch64_Q10_Q11 = 415,
433  AArch64_Q11_Q12 = 416,
434  AArch64_Q12_Q13 = 417,
435  AArch64_Q13_Q14 = 418,
436  AArch64_Q14_Q15 = 419,
437  AArch64_Q15_Q16 = 420,
438  AArch64_Q16_Q17 = 421,
439  AArch64_Q17_Q18 = 422,
440  AArch64_Q18_Q19 = 423,
441  AArch64_Q19_Q20 = 424,
442  AArch64_Q20_Q21 = 425,
443  AArch64_Q21_Q22 = 426,
444  AArch64_Q22_Q23 = 427,
445  AArch64_Q23_Q24 = 428,
446  AArch64_Q24_Q25 = 429,
447  AArch64_Q25_Q26 = 430,
448  AArch64_Q26_Q27 = 431,
449  AArch64_Q27_Q28 = 432,
450  AArch64_Q28_Q29 = 433,
451  AArch64_Q29_Q30 = 434,
452  AArch64_Q30_Q31 = 435,
453  AArch64_Q31_Q0 = 436,
454  AArch64_Q0_Q1_Q2_Q3 = 437,
455  AArch64_Q1_Q2_Q3_Q4 = 438,
456  AArch64_Q2_Q3_Q4_Q5 = 439,
457  AArch64_Q3_Q4_Q5_Q6 = 440,
458  AArch64_Q4_Q5_Q6_Q7 = 441,
459  AArch64_Q5_Q6_Q7_Q8 = 442,
460  AArch64_Q6_Q7_Q8_Q9 = 443,
461  AArch64_Q7_Q8_Q9_Q10 = 444,
462  AArch64_Q8_Q9_Q10_Q11 = 445,
463  AArch64_Q9_Q10_Q11_Q12 = 446,
464  AArch64_Q10_Q11_Q12_Q13 = 447,
465  AArch64_Q11_Q12_Q13_Q14 = 448,
466  AArch64_Q12_Q13_Q14_Q15 = 449,
467  AArch64_Q13_Q14_Q15_Q16 = 450,
468  AArch64_Q14_Q15_Q16_Q17 = 451,
469  AArch64_Q15_Q16_Q17_Q18 = 452,
470  AArch64_Q16_Q17_Q18_Q19 = 453,
471  AArch64_Q17_Q18_Q19_Q20 = 454,
472  AArch64_Q18_Q19_Q20_Q21 = 455,
473  AArch64_Q19_Q20_Q21_Q22 = 456,
474  AArch64_Q20_Q21_Q22_Q23 = 457,
475  AArch64_Q21_Q22_Q23_Q24 = 458,
476  AArch64_Q22_Q23_Q24_Q25 = 459,
477  AArch64_Q23_Q24_Q25_Q26 = 460,
478  AArch64_Q24_Q25_Q26_Q27 = 461,
479  AArch64_Q25_Q26_Q27_Q28 = 462,
480  AArch64_Q26_Q27_Q28_Q29 = 463,
481  AArch64_Q27_Q28_Q29_Q30 = 464,
482  AArch64_Q28_Q29_Q30_Q31 = 465,
483  AArch64_Q29_Q30_Q31_Q0 = 466,
484  AArch64_Q30_Q31_Q0_Q1 = 467,
485  AArch64_Q31_Q0_Q1_Q2 = 468,
486  AArch64_Q0_Q1_Q2 = 469,
487  AArch64_Q1_Q2_Q3 = 470,
488  AArch64_Q2_Q3_Q4 = 471,
489  AArch64_Q3_Q4_Q5 = 472,
490  AArch64_Q4_Q5_Q6 = 473,
491  AArch64_Q5_Q6_Q7 = 474,
492  AArch64_Q6_Q7_Q8 = 475,
493  AArch64_Q7_Q8_Q9 = 476,
494  AArch64_Q8_Q9_Q10 = 477,
495  AArch64_Q9_Q10_Q11 = 478,
496  AArch64_Q10_Q11_Q12 = 479,
497  AArch64_Q11_Q12_Q13 = 480,
498  AArch64_Q12_Q13_Q14 = 481,
499  AArch64_Q13_Q14_Q15 = 482,
500  AArch64_Q14_Q15_Q16 = 483,
501  AArch64_Q15_Q16_Q17 = 484,
502  AArch64_Q16_Q17_Q18 = 485,
503  AArch64_Q17_Q18_Q19 = 486,
504  AArch64_Q18_Q19_Q20 = 487,
505  AArch64_Q19_Q20_Q21 = 488,
506  AArch64_Q20_Q21_Q22 = 489,
507  AArch64_Q21_Q22_Q23 = 490,
508  AArch64_Q22_Q23_Q24 = 491,
509  AArch64_Q23_Q24_Q25 = 492,
510  AArch64_Q24_Q25_Q26 = 493,
511  AArch64_Q25_Q26_Q27 = 494,
512  AArch64_Q26_Q27_Q28 = 495,
513  AArch64_Q27_Q28_Q29 = 496,
514  AArch64_Q28_Q29_Q30 = 497,
515  AArch64_Q29_Q30_Q31 = 498,
516  AArch64_Q30_Q31_Q0 = 499,
517  AArch64_Q31_Q0_Q1 = 500,
518  AArch64_WZR_W0 = 501,
519  AArch64_W30_WZR = 502,
520  AArch64_W0_W1 = 503,
521  AArch64_W1_W2 = 504,
522  AArch64_W2_W3 = 505,
523  AArch64_W3_W4 = 506,
524  AArch64_W4_W5 = 507,
525  AArch64_W5_W6 = 508,
526  AArch64_W6_W7 = 509,
527  AArch64_W7_W8 = 510,
528  AArch64_W8_W9 = 511,
529  AArch64_W9_W10 = 512,
530  AArch64_W10_W11 = 513,
531  AArch64_W11_W12 = 514,
532  AArch64_W12_W13 = 515,
533  AArch64_W13_W14 = 516,
534  AArch64_W14_W15 = 517,
535  AArch64_W15_W16 = 518,
536  AArch64_W16_W17 = 519,
537  AArch64_W17_W18 = 520,
538  AArch64_W18_W19 = 521,
539  AArch64_W19_W20 = 522,
540  AArch64_W20_W21 = 523,
541  AArch64_W21_W22 = 524,
542  AArch64_W22_W23 = 525,
543  AArch64_W23_W24 = 526,
544  AArch64_W24_W25 = 527,
545  AArch64_W25_W26 = 528,
546  AArch64_W26_W27 = 529,
547  AArch64_W27_W28 = 530,
548  AArch64_W28_W29 = 531,
549  AArch64_W29_W30 = 532,
550  AArch64_FP_LR = 533,
551  AArch64_LR_XZR = 534,
552  AArch64_XZR_X0 = 535,
553  AArch64_X28_FP = 536,
554  AArch64_X0_X1 = 537,
555  AArch64_X1_X2 = 538,
556  AArch64_X2_X3 = 539,
557  AArch64_X3_X4 = 540,
558  AArch64_X4_X5 = 541,
559  AArch64_X5_X6 = 542,
560  AArch64_X6_X7 = 543,
561  AArch64_X7_X8 = 544,
562  AArch64_X8_X9 = 545,
563  AArch64_X9_X10 = 546,
564  AArch64_X10_X11 = 547,
565  AArch64_X11_X12 = 548,
566  AArch64_X12_X13 = 549,
567  AArch64_X13_X14 = 550,
568  AArch64_X14_X15 = 551,
569  AArch64_X15_X16 = 552,
570  AArch64_X16_X17 = 553,
571  AArch64_X17_X18 = 554,
572  AArch64_X18_X19 = 555,
573  AArch64_X19_X20 = 556,
574  AArch64_X20_X21 = 557,
575  AArch64_X21_X22 = 558,
576  AArch64_X22_X23 = 559,
577  AArch64_X23_X24 = 560,
578  AArch64_X24_X25 = 561,
579  AArch64_X25_X26 = 562,
580  AArch64_X26_X27 = 563,
581  AArch64_X27_X28 = 564,
582  AArch64_Z0_Z1 = 565,
583  AArch64_Z1_Z2 = 566,
584  AArch64_Z2_Z3 = 567,
585  AArch64_Z3_Z4 = 568,
586  AArch64_Z4_Z5 = 569,
587  AArch64_Z5_Z6 = 570,
588  AArch64_Z6_Z7 = 571,
589  AArch64_Z7_Z8 = 572,
590  AArch64_Z8_Z9 = 573,
591  AArch64_Z9_Z10 = 574,
592  AArch64_Z10_Z11 = 575,
593  AArch64_Z11_Z12 = 576,
594  AArch64_Z12_Z13 = 577,
595  AArch64_Z13_Z14 = 578,
596  AArch64_Z14_Z15 = 579,
597  AArch64_Z15_Z16 = 580,
598  AArch64_Z16_Z17 = 581,
599  AArch64_Z17_Z18 = 582,
600  AArch64_Z18_Z19 = 583,
601  AArch64_Z19_Z20 = 584,
602  AArch64_Z20_Z21 = 585,
603  AArch64_Z21_Z22 = 586,
604  AArch64_Z22_Z23 = 587,
605  AArch64_Z23_Z24 = 588,
606  AArch64_Z24_Z25 = 589,
607  AArch64_Z25_Z26 = 590,
608  AArch64_Z26_Z27 = 591,
609  AArch64_Z27_Z28 = 592,
610  AArch64_Z28_Z29 = 593,
611  AArch64_Z29_Z30 = 594,
612  AArch64_Z30_Z31 = 595,
613  AArch64_Z31_Z0 = 596,
614  AArch64_Z0_Z1_Z2_Z3 = 597,
615  AArch64_Z1_Z2_Z3_Z4 = 598,
616  AArch64_Z2_Z3_Z4_Z5 = 599,
617  AArch64_Z3_Z4_Z5_Z6 = 600,
618  AArch64_Z4_Z5_Z6_Z7 = 601,
619  AArch64_Z5_Z6_Z7_Z8 = 602,
620  AArch64_Z6_Z7_Z8_Z9 = 603,
621  AArch64_Z7_Z8_Z9_Z10 = 604,
622  AArch64_Z8_Z9_Z10_Z11 = 605,
623  AArch64_Z9_Z10_Z11_Z12 = 606,
624  AArch64_Z10_Z11_Z12_Z13 = 607,
625  AArch64_Z11_Z12_Z13_Z14 = 608,
626  AArch64_Z12_Z13_Z14_Z15 = 609,
627  AArch64_Z13_Z14_Z15_Z16 = 610,
628  AArch64_Z14_Z15_Z16_Z17 = 611,
629  AArch64_Z15_Z16_Z17_Z18 = 612,
630  AArch64_Z16_Z17_Z18_Z19 = 613,
631  AArch64_Z17_Z18_Z19_Z20 = 614,
632  AArch64_Z18_Z19_Z20_Z21 = 615,
633  AArch64_Z19_Z20_Z21_Z22 = 616,
634  AArch64_Z20_Z21_Z22_Z23 = 617,
635  AArch64_Z21_Z22_Z23_Z24 = 618,
636  AArch64_Z22_Z23_Z24_Z25 = 619,
637  AArch64_Z23_Z24_Z25_Z26 = 620,
638  AArch64_Z24_Z25_Z26_Z27 = 621,
639  AArch64_Z25_Z26_Z27_Z28 = 622,
640  AArch64_Z26_Z27_Z28_Z29 = 623,
641  AArch64_Z27_Z28_Z29_Z30 = 624,
642  AArch64_Z28_Z29_Z30_Z31 = 625,
643  AArch64_Z29_Z30_Z31_Z0 = 626,
644  AArch64_Z30_Z31_Z0_Z1 = 627,
645  AArch64_Z31_Z0_Z1_Z2 = 628,
646  AArch64_Z0_Z1_Z2 = 629,
647  AArch64_Z1_Z2_Z3 = 630,
648  AArch64_Z2_Z3_Z4 = 631,
649  AArch64_Z3_Z4_Z5 = 632,
650  AArch64_Z4_Z5_Z6 = 633,
651  AArch64_Z5_Z6_Z7 = 634,
652  AArch64_Z6_Z7_Z8 = 635,
653  AArch64_Z7_Z8_Z9 = 636,
654  AArch64_Z8_Z9_Z10 = 637,
655  AArch64_Z9_Z10_Z11 = 638,
656  AArch64_Z10_Z11_Z12 = 639,
657  AArch64_Z11_Z12_Z13 = 640,
658  AArch64_Z12_Z13_Z14 = 641,
659  AArch64_Z13_Z14_Z15 = 642,
660  AArch64_Z14_Z15_Z16 = 643,
661  AArch64_Z15_Z16_Z17 = 644,
662  AArch64_Z16_Z17_Z18 = 645,
663  AArch64_Z17_Z18_Z19 = 646,
664  AArch64_Z18_Z19_Z20 = 647,
665  AArch64_Z19_Z20_Z21 = 648,
666  AArch64_Z20_Z21_Z22 = 649,
667  AArch64_Z21_Z22_Z23 = 650,
668  AArch64_Z22_Z23_Z24 = 651,
669  AArch64_Z23_Z24_Z25 = 652,
670  AArch64_Z24_Z25_Z26 = 653,
671  AArch64_Z25_Z26_Z27 = 654,
672  AArch64_Z26_Z27_Z28 = 655,
673  AArch64_Z27_Z28_Z29 = 656,
674  AArch64_Z28_Z29_Z30 = 657,
675  AArch64_Z29_Z30_Z31 = 658,
676  AArch64_Z30_Z31_Z0 = 659,
677  AArch64_Z31_Z0_Z1 = 660,
678  AArch64_NUM_TARGET_REGS 	// 661
679};
680
681// Register classes
682enum {
683  AArch64_FPR8RegClassID = 0,
684  AArch64_FPR16RegClassID = 1,
685  AArch64_PPRRegClassID = 2,
686  AArch64_PPR_3bRegClassID = 3,
687  AArch64_GPR32allRegClassID = 4,
688  AArch64_FPR32RegClassID = 5,
689  AArch64_GPR32RegClassID = 6,
690  AArch64_GPR32spRegClassID = 7,
691  AArch64_GPR32commonRegClassID = 8,
692  AArch64_CCRRegClassID = 9,
693  AArch64_GPR32sponlyRegClassID = 10,
694  AArch64_WSeqPairsClassRegClassID = 11,
695  AArch64_WSeqPairsClass_with_sube32_in_GPR32commonRegClassID = 12,
696  AArch64_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 13,
697  AArch64_WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 14,
698  AArch64_GPR64allRegClassID = 15,
699  AArch64_FPR64RegClassID = 16,
700  AArch64_GPR64RegClassID = 17,
701  AArch64_GPR64spRegClassID = 18,
702  AArch64_GPR64commonRegClassID = 19,
703  AArch64_tcGPR64RegClassID = 20,
704  AArch64_GPR64sponlyRegClassID = 21,
705  AArch64_DDRegClassID = 22,
706  AArch64_XSeqPairsClassRegClassID = 23,
707  AArch64_XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID = 24,
708  AArch64_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 25,
709  AArch64_XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 26,
710  AArch64_XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 27,
711  AArch64_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 28,
712  AArch64_XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 29,
713  AArch64_FPR128RegClassID = 30,
714  AArch64_ZPRRegClassID = 31,
715  AArch64_FPR128_loRegClassID = 32,
716  AArch64_ZPR_4bRegClassID = 33,
717  AArch64_ZPR_3bRegClassID = 34,
718  AArch64_DDDRegClassID = 35,
719  AArch64_DDDDRegClassID = 36,
720  AArch64_QQRegClassID = 37,
721  AArch64_ZPR2RegClassID = 38,
722  AArch64_QQ_with_qsub0_in_FPR128_loRegClassID = 39,
723  AArch64_QQ_with_qsub1_in_FPR128_loRegClassID = 40,
724  AArch64_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 41,
725  AArch64_ZPR2_with_zsub_in_FPR128_loRegClassID = 42,
726  AArch64_QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 43,
727  AArch64_ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 44,
728  AArch64_ZPR2_with_zsub0_in_ZPR_3bRegClassID = 45,
729  AArch64_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 46,
730  AArch64_ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 47,
731  AArch64_QQQRegClassID = 48,
732  AArch64_ZPR3RegClassID = 49,
733  AArch64_QQQ_with_qsub0_in_FPR128_loRegClassID = 50,
734  AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID = 51,
735  AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID = 52,
736  AArch64_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 53,
737  AArch64_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 54,
738  AArch64_ZPR3_with_zsub_in_FPR128_loRegClassID = 55,
739  AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 56,
740  AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 57,
741  AArch64_ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 58,
742  AArch64_ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 59,
743  AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 60,
744  AArch64_ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 61,
745  AArch64_ZPR3_with_zsub0_in_ZPR_3bRegClassID = 62,
746  AArch64_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 63,
747  AArch64_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 64,
748  AArch64_ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 65,
749  AArch64_ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 66,
750  AArch64_ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 67,
751  AArch64_QQQQRegClassID = 68,
752  AArch64_ZPR4RegClassID = 69,
753  AArch64_QQQQ_with_qsub0_in_FPR128_loRegClassID = 70,
754  AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID = 71,
755  AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID = 72,
756  AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID = 73,
757  AArch64_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 74,
758  AArch64_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 75,
759  AArch64_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 76,
760  AArch64_ZPR4_with_zsub_in_FPR128_loRegClassID = 77,
761  AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 78,
762  AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 79,
763  AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 80,
764  AArch64_ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 81,
765  AArch64_ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 82,
766  AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 83,
767  AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 84,
768  AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 85,
769  AArch64_ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 86,
770  AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 87,
771  AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 88,
772  AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 89,
773  AArch64_ZPR4_with_zsub0_in_ZPR_3bRegClassID = 90,
774  AArch64_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 91,
775  AArch64_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 92,
776  AArch64_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 93,
777  AArch64_ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 94,
778  AArch64_ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 95,
779  AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 96,
780  AArch64_ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 97,
781  AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 98,
782  AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 99,
783};
784
785// Register alternate name indices
786enum {
787  AArch64_NoRegAltName,	// 0
788  AArch64_vlist1,	// 1
789  AArch64_vreg,	// 2
790  AArch64_NUM_TARGET_REG_ALT_NAMES = 3
791};
792
793// Subregister indices
794enum {
795  AArch64_NoSubRegister,
796  AArch64_bsub,	// 1
797  AArch64_dsub,	// 2
798  AArch64_dsub0,	// 3
799  AArch64_dsub1,	// 4
800  AArch64_dsub2,	// 5
801  AArch64_dsub3,	// 6
802  AArch64_hsub,	// 7
803  AArch64_qhisub,	// 8
804  AArch64_qsub,	// 9
805  AArch64_qsub0,	// 10
806  AArch64_qsub1,	// 11
807  AArch64_qsub2,	// 12
808  AArch64_qsub3,	// 13
809  AArch64_ssub,	// 14
810  AArch64_sub_32,	// 15
811  AArch64_sube32,	// 16
812  AArch64_sube64,	// 17
813  AArch64_subo32,	// 18
814  AArch64_subo64,	// 19
815  AArch64_zsub,	// 20
816  AArch64_zsub0,	// 21
817  AArch64_zsub1,	// 22
818  AArch64_zsub2,	// 23
819  AArch64_zsub3,	// 24
820  AArch64_zsub_hi,	// 25
821  AArch64_dsub1_then_bsub,	// 26
822  AArch64_dsub1_then_hsub,	// 27
823  AArch64_dsub1_then_ssub,	// 28
824  AArch64_dsub3_then_bsub,	// 29
825  AArch64_dsub3_then_hsub,	// 30
826  AArch64_dsub3_then_ssub,	// 31
827  AArch64_dsub2_then_bsub,	// 32
828  AArch64_dsub2_then_hsub,	// 33
829  AArch64_dsub2_then_ssub,	// 34
830  AArch64_qsub1_then_bsub,	// 35
831  AArch64_qsub1_then_dsub,	// 36
832  AArch64_qsub1_then_hsub,	// 37
833  AArch64_qsub1_then_ssub,	// 38
834  AArch64_qsub3_then_bsub,	// 39
835  AArch64_qsub3_then_dsub,	// 40
836  AArch64_qsub3_then_hsub,	// 41
837  AArch64_qsub3_then_ssub,	// 42
838  AArch64_qsub2_then_bsub,	// 43
839  AArch64_qsub2_then_dsub,	// 44
840  AArch64_qsub2_then_hsub,	// 45
841  AArch64_qsub2_then_ssub,	// 46
842  AArch64_subo64_then_sub_32,	// 47
843  AArch64_zsub1_then_bsub,	// 48
844  AArch64_zsub1_then_dsub,	// 49
845  AArch64_zsub1_then_hsub,	// 50
846  AArch64_zsub1_then_ssub,	// 51
847  AArch64_zsub1_then_zsub,	// 52
848  AArch64_zsub1_then_zsub_hi,	// 53
849  AArch64_zsub3_then_bsub,	// 54
850  AArch64_zsub3_then_dsub,	// 55
851  AArch64_zsub3_then_hsub,	// 56
852  AArch64_zsub3_then_ssub,	// 57
853  AArch64_zsub3_then_zsub,	// 58
854  AArch64_zsub3_then_zsub_hi,	// 59
855  AArch64_zsub2_then_bsub,	// 60
856  AArch64_zsub2_then_dsub,	// 61
857  AArch64_zsub2_then_hsub,	// 62
858  AArch64_zsub2_then_ssub,	// 63
859  AArch64_zsub2_then_zsub,	// 64
860  AArch64_zsub2_then_zsub_hi,	// 65
861  AArch64_dsub0_dsub1,	// 66
862  AArch64_dsub0_dsub1_dsub2,	// 67
863  AArch64_dsub1_dsub2,	// 68
864  AArch64_dsub1_dsub2_dsub3,	// 69
865  AArch64_dsub2_dsub3,	// 70
866  AArch64_dsub_qsub1_then_dsub,	// 71
867  AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub,	// 72
868  AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub,	// 73
869  AArch64_qsub0_qsub1,	// 74
870  AArch64_qsub0_qsub1_qsub2,	// 75
871  AArch64_qsub1_qsub2,	// 76
872  AArch64_qsub1_qsub2_qsub3,	// 77
873  AArch64_qsub2_qsub3,	// 78
874  AArch64_qsub1_then_dsub_qsub2_then_dsub,	// 79
875  AArch64_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub,	// 80
876  AArch64_qsub2_then_dsub_qsub3_then_dsub,	// 81
877  AArch64_sub_32_subo64_then_sub_32,	// 82
878  AArch64_dsub_zsub1_then_dsub,	// 83
879  AArch64_zsub_zsub1_then_zsub,	// 84
880  AArch64_dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub,	// 85
881  AArch64_dsub_zsub1_then_dsub_zsub2_then_dsub,	// 86
882  AArch64_zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub,	// 87
883  AArch64_zsub_zsub1_then_zsub_zsub2_then_zsub,	// 88
884  AArch64_zsub0_zsub1,	// 89
885  AArch64_zsub0_zsub1_zsub2,	// 90
886  AArch64_zsub1_zsub2,	// 91
887  AArch64_zsub1_zsub2_zsub3,	// 92
888  AArch64_zsub2_zsub3,	// 93
889  AArch64_zsub1_then_dsub_zsub2_then_dsub,	// 94
890  AArch64_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub,	// 95
891  AArch64_zsub1_then_zsub_zsub2_then_zsub,	// 96
892  AArch64_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub,	// 97
893  AArch64_zsub2_then_dsub_zsub3_then_dsub,	// 98
894  AArch64_zsub2_then_zsub_zsub3_then_zsub,	// 99
895  AArch64_NUM_TARGET_SUBREGS
896};
897
898#endif // GET_REGINFO_ENUM
899
900#ifdef GET_REGINFO_MC_DESC
901#undef GET_REGINFO_MC_DESC
902
903
904static const MCPhysReg AArch64RegDiffLists[] = {
905  /* 0 */ 64945, 1, 1, 1, 74, 1, 1, 1, 0,
906  /* 9 */ 65105, 1, 1, 1, 0,
907  /* 14 */ 65201, 1, 1, 1, 0,
908  /* 19 */ 6, 29, 1, 1, 0,
909  /* 24 */ 6, 29, 1, 1, 46, 29, 1, 1, 0,
910  /* 33 */ 65324, 499, 30, 1, 1, 0,
911  /* 39 */ 64913, 1, 1, 75, 1, 1, 0,
912  /* 46 */ 65073, 1, 1, 0,
913  /* 50 */ 65169, 1, 1, 0,
914  /* 54 */ 6, 1, 29, 1, 0,
915  /* 59 */ 6, 1, 29, 1, 46, 1, 29, 1, 0,
916  /* 68 */ 6, 30, 1, 0,
917  /* 72 */ 6, 30, 1, 46, 30, 1, 0,
918  /* 79 */ 1, 493, 1, 32, 1, 0,
919  /* 85 */ 31, 286, 1, 33, 1, 0,
920  /* 91 */ 64977, 1, 76, 1, 0,
921  /* 96 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 298, 1, 0,
922  /* 111 */ 320, 1, 0,
923  /* 114 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 330, 1, 0,
924  /* 129 */ 526, 1, 0,
925  /* 132 */ 530, 1, 0,
926  /* 135 */ 65053, 1, 0,
927  /* 138 */ 65087, 1, 0,
928  /* 141 */ 65137, 1, 0,
929  /* 144 */ 65218, 1, 0,
930  /* 147 */ 65233, 1, 0,
931  /* 150 */ 64, 80, 65424, 80, 124, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
932  /* 183 */ 124, 159, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
933  /* 203 */ 65504, 319, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
934  /* 214 */ 64, 80, 65424, 80, 124, 64, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
935  /* 247 */ 124, 160, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
936  /* 267 */ 65504, 320, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
937  /* 278 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 128, 63, 65503, 34, 65503, 1, 0,
938  /* 296 */ 64, 80, 65424, 80, 124, 63, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
939  /* 329 */ 124, 159, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
940  /* 349 */ 65504, 319, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
941  /* 360 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 97, 64, 65504, 63, 65503, 1, 0,
942  /* 378 */ 65503, 1, 128, 65503, 1, 192, 65503, 1, 0,
943  /* 387 */ 31, 285, 2, 32, 2, 0,
944  /* 393 */ 319, 2, 0,
945  /* 396 */ 65324, 529, 1, 1, 3, 0,
946  /* 402 */ 2, 3, 0,
947  /* 405 */ 531, 3, 0,
948  /* 408 */ 65004, 3, 0,
949  /* 411 */ 4, 0,
950  /* 413 */ 5, 0,
951  /* 415 */ 31, 286, 1, 5, 28, 0,
952  /* 421 */ 292, 28, 0,
953  /* 424 */ 6, 1, 1, 29, 0,
954  /* 429 */ 6, 1, 1, 29, 46, 1, 1, 29, 0,
955  /* 438 */ 64, 80, 65424, 80, 124, 63, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
956  /* 471 */ 124, 159, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
957  /* 491 */ 65504, 319, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
958  /* 502 */ 6, 1, 30, 0,
959  /* 506 */ 6, 1, 30, 46, 1, 30, 0,
960  /* 513 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 98, 63, 1, 65503, 1, 30, 0,
961  /* 531 */ 6, 31, 0,
962  /* 534 */ 6, 31, 46, 31, 0,
963  /* 539 */ 65504, 31, 97, 65504, 31, 161, 65504, 31, 0,
964  /* 548 */ 32, 0,
965  /* 550 */ 34, 0,
966  /* 552 */ 5, 49, 0,
967  /* 555 */ 63936, 49, 0,
968  /* 558 */ 65297, 77, 0,
969  /* 561 */ 1, 81, 0,
970  /* 564 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 31, 96, 0,
971  /* 581 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 63, 96, 0,
972  /* 598 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 30, 96, 65504, 96, 96, 1, 65280, 96, 0,
973  /* 628 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 1, 65280, 96, 0,
974  /* 658 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 65505, 65280, 96, 0,
975  /* 688 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65441, 65311, 64, 32, 64, 65345, 96, 0,
976  /* 734 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65441, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
977  /* 780 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 29, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
978  /* 826 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0,
979  /* 872 */ 96, 160, 0,
980  /* 875 */ 65042, 178, 0,
981  /* 878 */ 212, 0,
982  /* 880 */ 65412, 65456, 112, 65456, 65472, 268, 0,
983  /* 887 */ 65252, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 299, 0,
984  /* 899 */ 65009, 65535, 209, 65505, 316, 0,
985  /* 905 */ 65005, 212, 65325, 212, 317, 0,
986  /* 911 */ 65244, 65505, 65325, 212, 317, 0,
987  /* 917 */ 65215, 65505, 32, 65505, 317, 0,
988  /* 923 */ 65252, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 331, 0,
989  /* 935 */ 65005, 212, 65329, 65535, 495, 0,
990  /* 941 */ 65323, 0,
991  /* 943 */ 65249, 65328, 0,
992  /* 946 */ 65342, 0,
993  /* 948 */ 65374, 0,
994  /* 950 */ 65389, 0,
995  /* 952 */ 65405, 0,
996  /* 954 */ 65421, 0,
997  /* 956 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 298, 64, 32, 1, 65440, 0,
998  /* 977 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 330, 64, 32, 1, 65440, 0,
999  /* 998 */ 65188, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 330, 64, 32, 65505, 65440, 0,
1000  /* 1019 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0,
1001  /* 1051 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65473, 64, 65441, 0,
1002  /* 1073 */ 65469, 0,
1003  /* 1075 */ 65268, 112, 65456, 65472, 1, 112, 65456, 65472, 0,
1004  /* 1084 */ 65268, 112, 65456, 65472, 33, 112, 65456, 65472, 0,
1005  /* 1093 */ 65456, 112, 65456, 65472, 0,
1006  /* 1098 */ 65220, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0,
1007  /* 1130 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 297, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
1008  /* 1162 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
1009  /* 1194 */ 65236, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65441, 64, 65473, 0,
1010  /* 1216 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 297, 64, 65473, 64, 65473, 0,
1011  /* 1238 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 329, 64, 65473, 64, 65473, 0,
1012  /* 1260 */ 65501, 0,
1013  /* 1262 */ 65204, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 330, 65505, 0,
1014  /* 1277 */ 65533, 0,
1015  /* 1279 */ 65535, 0,
1016};
1017
1018static const uint16_t AArch64SubRegIdxLists[] = {
1019  /* 0 */ 2, 14, 7, 1, 0,
1020  /* 5 */ 15, 0,
1021  /* 7 */ 16, 18, 0,
1022  /* 10 */ 20, 2, 14, 7, 1, 25, 0,
1023  /* 17 */ 3, 14, 7, 1, 4, 28, 27, 26, 0,
1024  /* 26 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 66, 68, 0,
1025  /* 41 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 6, 31, 30, 29, 66, 67, 68, 69, 70, 0,
1026  /* 63 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 71, 0,
1027  /* 75 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 71, 73, 74, 76, 79, 0,
1028  /* 96 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 13, 40, 42, 41, 39, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 0,
1029  /* 128 */ 17, 15, 19, 47, 82, 0,
1030  /* 134 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 83, 84, 0,
1031  /* 151 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 83, 84, 86, 88, 89, 91, 94, 96, 0,
1032  /* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0,
1033};
1034
1035static const MCRegisterDesc AArch64RegDesc[] = {
1036  { 3, 0, 0, 0, 0, 0 },
1037  { 2489, 8, 8, 4, 20465, 0 },
1038  { 2482, 878, 405, 5, 20465, 27 },
1039  { 2496, 878, 132, 5, 20465, 27 },
1040  { 2514, 8, 8, 4, 20465, 0 },
1041  { 2486, 7, 8, 5, 6576, 27 },
1042  { 2485, 8, 1279, 4, 6576, 0 },
1043  { 2503, 8, 79, 4, 6608, 0 },
1044  { 2510, 1279, 129, 5, 6608, 27 },
1045  { 213, 8, 214, 4, 20433, 0 },
1046  { 494, 8, 296, 4, 20433, 0 },
1047  { 713, 8, 438, 4, 20433, 0 },
1048  { 932, 8, 150, 4, 20433, 0 },
1049  { 1148, 8, 150, 4, 20433, 0 },
1050  { 1364, 8, 150, 4, 20433, 0 },
1051  { 1576, 8, 150, 4, 20433, 0 },
1052  { 1788, 8, 150, 4, 20433, 0 },
1053  { 2000, 8, 150, 4, 20433, 0 },
1054  { 2204, 8, 150, 4, 20433, 0 },
1055  { 0, 8, 150, 4, 20433, 0 },
1056  { 284, 8, 150, 4, 20433, 0 },
1057  { 560, 8, 150, 4, 20433, 0 },
1058  { 776, 8, 150, 4, 20433, 0 },
1059  { 992, 8, 150, 4, 20433, 0 },
1060  { 1208, 8, 150, 4, 20433, 0 },
1061  { 1424, 8, 150, 4, 20433, 0 },
1062  { 1636, 8, 150, 4, 20433, 0 },
1063  { 1848, 8, 150, 4, 20433, 0 },
1064  { 2060, 8, 150, 4, 20433, 0 },
1065  { 69, 8, 150, 4, 20433, 0 },
1066  { 358, 8, 150, 4, 20433, 0 },
1067  { 637, 8, 150, 4, 20433, 0 },
1068  { 856, 8, 150, 4, 20433, 0 },
1069  { 1072, 8, 150, 4, 20433, 0 },
1070  { 1288, 8, 150, 4, 20433, 0 },
1071  { 1500, 8, 150, 4, 20433, 0 },
1072  { 1712, 8, 150, 4, 20433, 0 },
1073  { 1924, 8, 150, 4, 20433, 0 },
1074  { 2136, 8, 150, 4, 20433, 0 },
1075  { 145, 8, 150, 4, 20433, 0 },
1076  { 434, 8, 150, 4, 20433, 0 },
1077  { 228, 1080, 217, 1, 20161, 3 },
1078  { 508, 1080, 299, 1, 20161, 3 },
1079  { 726, 1080, 441, 1, 20161, 3 },
1080  { 944, 1080, 153, 1, 20161, 3 },
1081  { 1160, 1080, 153, 1, 20161, 3 },
1082  { 1376, 1080, 153, 1, 20161, 3 },
1083  { 1588, 1080, 153, 1, 20161, 3 },
1084  { 1800, 1080, 153, 1, 20161, 3 },
1085  { 2012, 1080, 153, 1, 20161, 3 },
1086  { 2216, 1080, 153, 1, 20161, 3 },
1087  { 13, 1080, 153, 1, 20161, 3 },
1088  { 298, 1080, 153, 1, 20161, 3 },
1089  { 575, 1080, 153, 1, 20161, 3 },
1090  { 792, 1080, 153, 1, 20161, 3 },
1091  { 1008, 1080, 153, 1, 20161, 3 },
1092  { 1224, 1080, 153, 1, 20161, 3 },
1093  { 1440, 1080, 153, 1, 20161, 3 },
1094  { 1652, 1080, 153, 1, 20161, 3 },
1095  { 1864, 1080, 153, 1, 20161, 3 },
1096  { 2076, 1080, 153, 1, 20161, 3 },
1097  { 85, 1080, 153, 1, 20161, 3 },
1098  { 374, 1080, 153, 1, 20161, 3 },
1099  { 653, 1080, 153, 1, 20161, 3 },
1100  { 872, 1080, 153, 1, 20161, 3 },
1101  { 1088, 1080, 153, 1, 20161, 3 },
1102  { 1304, 1080, 153, 1, 20161, 3 },
1103  { 1516, 1080, 153, 1, 20161, 3 },
1104  { 1728, 1080, 153, 1, 20161, 3 },
1105  { 1940, 1080, 153, 1, 20161, 3 },
1106  { 2152, 1080, 153, 1, 20161, 3 },
1107  { 161, 1080, 153, 1, 20161, 3 },
1108  { 450, 1080, 153, 1, 20161, 3 },
1109  { 231, 1082, 215, 3, 17169, 3 },
1110  { 511, 1082, 297, 3, 17169, 3 },
1111  { 729, 1082, 439, 3, 17169, 3 },
1112  { 947, 1082, 151, 3, 17169, 3 },
1113  { 1163, 1082, 151, 3, 17169, 3 },
1114  { 1379, 1082, 151, 3, 17169, 3 },
1115  { 1591, 1082, 151, 3, 17169, 3 },
1116  { 1803, 1082, 151, 3, 17169, 3 },
1117  { 2015, 1082, 151, 3, 17169, 3 },
1118  { 2219, 1082, 151, 3, 17169, 3 },
1119  { 17, 1082, 151, 3, 17169, 3 },
1120  { 302, 1082, 151, 3, 17169, 3 },
1121  { 579, 1082, 151, 3, 17169, 3 },
1122  { 796, 1082, 151, 3, 17169, 3 },
1123  { 1012, 1082, 151, 3, 17169, 3 },
1124  { 1228, 1082, 151, 3, 17169, 3 },
1125  { 1444, 1082, 151, 3, 17169, 3 },
1126  { 1656, 1082, 151, 3, 17169, 3 },
1127  { 1868, 1082, 151, 3, 17169, 3 },
1128  { 2080, 1082, 151, 3, 17169, 3 },
1129  { 89, 1082, 151, 3, 17169, 3 },
1130  { 378, 1082, 151, 3, 17169, 3 },
1131  { 657, 1082, 151, 3, 17169, 3 },
1132  { 876, 1082, 151, 3, 17169, 3 },
1133  { 1092, 1082, 151, 3, 17169, 3 },
1134  { 1308, 1082, 151, 3, 17169, 3 },
1135  { 1520, 1082, 151, 3, 17169, 3 },
1136  { 1732, 1082, 151, 3, 17169, 3 },
1137  { 1944, 1082, 151, 3, 17169, 3 },
1138  { 2156, 1082, 151, 3, 17169, 3 },
1139  { 165, 1082, 151, 3, 17169, 3 },
1140  { 454, 1082, 151, 3, 17169, 3 },
1141  { 234, 8, 8, 4, 17169, 0 },
1142  { 514, 8, 8, 4, 17169, 0 },
1143  { 732, 8, 8, 4, 17169, 0 },
1144  { 950, 8, 8, 4, 17169, 0 },
1145  { 1166, 8, 8, 4, 17169, 0 },
1146  { 1382, 8, 8, 4, 17169, 0 },
1147  { 1594, 8, 8, 4, 17169, 0 },
1148  { 1806, 8, 8, 4, 17169, 0 },
1149  { 2018, 8, 8, 4, 17169, 0 },
1150  { 2222, 8, 8, 4, 17169, 0 },
1151  { 21, 8, 8, 4, 17169, 0 },
1152  { 306, 8, 8, 4, 17169, 0 },
1153  { 583, 8, 8, 4, 17169, 0 },
1154  { 800, 8, 8, 4, 17169, 0 },
1155  { 1016, 8, 8, 4, 17169, 0 },
1156  { 1232, 8, 8, 4, 17169, 0 },
1157  { 249, 1093, 247, 0, 15265, 3 },
1158  { 528, 1093, 329, 0, 15265, 3 },
1159  { 745, 1093, 471, 0, 15265, 3 },
1160  { 962, 1093, 183, 0, 15265, 3 },
1161  { 1178, 1093, 183, 0, 15265, 3 },
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1563  { 1332, 144, 550, 7, 2209, 32 },
1564  { 1544, 144, 550, 7, 2209, 32 },
1565  { 1756, 144, 550, 7, 2209, 32 },
1566  { 1968, 144, 550, 7, 2209, 32 },
1567  { 2180, 144, 413, 7, 8976, 29 },
1568  { 189, 144, 7, 7, 96, 32 },
1569  { 2493, 905, 8, 128, 96, 97 },
1570  { 2507, 935, 8, 128, 6529, 97 },
1571  { 262, 899, 8, 128, 8883, 97 },
1572  { 2478, 911, 8, 128, 8976, 26 },
1573  { 540, 917, 8, 128, 2161, 97 },
1574  { 757, 917, 8, 128, 2161, 97 },
1575  { 974, 917, 8, 128, 2161, 97 },
1576  { 1190, 917, 8, 128, 2161, 97 },
1577  { 1406, 917, 8, 128, 2161, 97 },
1578  { 1618, 917, 8, 128, 2161, 97 },
1579  { 1830, 917, 8, 128, 2161, 97 },
1580  { 2042, 917, 8, 128, 2161, 97 },
1581  { 2246, 917, 8, 128, 2161, 97 },
1582  { 49, 917, 8, 128, 2161, 97 },
1583  { 336, 917, 8, 128, 2161, 97 },
1584  { 614, 917, 8, 128, 2161, 97 },
1585  { 832, 917, 8, 128, 2161, 97 },
1586  { 1048, 917, 8, 128, 2161, 97 },
1587  { 1264, 917, 8, 128, 2161, 97 },
1588  { 1476, 917, 8, 128, 2161, 97 },
1589  { 1688, 917, 8, 128, 2161, 97 },
1590  { 1900, 917, 8, 128, 2161, 97 },
1591  { 2112, 917, 8, 128, 2161, 97 },
1592  { 121, 917, 8, 128, 2161, 97 },
1593  { 410, 917, 8, 128, 2161, 97 },
1594  { 689, 917, 8, 128, 2161, 97 },
1595  { 908, 917, 8, 128, 2161, 97 },
1596  { 1124, 917, 8, 128, 2161, 97 },
1597  { 1340, 917, 8, 128, 2161, 97 },
1598  { 1552, 917, 8, 128, 2161, 97 },
1599  { 1764, 917, 8, 128, 2161, 97 },
1600  { 1976, 917, 8, 128, 2161, 97 },
1601  { 554, 564, 372, 134, 1457, 100 },
1602  { 770, 564, 525, 134, 1457, 100 },
1603  { 986, 564, 290, 134, 1457, 100 },
1604  { 1202, 564, 290, 134, 1457, 100 },
1605  { 1418, 564, 290, 134, 1457, 100 },
1606  { 1630, 564, 290, 134, 1457, 100 },
1607  { 1842, 564, 290, 134, 1457, 100 },
1608  { 2054, 564, 290, 134, 1457, 100 },
1609  { 2258, 564, 290, 134, 1457, 100 },
1610  { 62, 564, 290, 134, 1457, 100 },
1611  { 350, 564, 290, 134, 1457, 100 },
1612  { 629, 564, 290, 134, 1457, 100 },
1613  { 848, 564, 290, 134, 1457, 100 },
1614  { 1064, 564, 290, 134, 1457, 100 },
1615  { 1280, 564, 290, 134, 1457, 100 },
1616  { 1492, 564, 290, 134, 1457, 100 },
1617  { 1704, 564, 290, 134, 1457, 100 },
1618  { 1916, 564, 290, 134, 1457, 100 },
1619  { 2128, 564, 290, 134, 1457, 100 },
1620  { 137, 564, 290, 134, 1457, 100 },
1621  { 426, 564, 290, 134, 1457, 100 },
1622  { 705, 564, 290, 134, 1457, 100 },
1623  { 924, 564, 290, 134, 1457, 100 },
1624  { 1140, 564, 290, 134, 1457, 100 },
1625  { 1356, 564, 290, 134, 1457, 100 },
1626  { 1568, 564, 290, 134, 1457, 100 },
1627  { 1780, 564, 290, 134, 1457, 100 },
1628  { 1992, 564, 290, 134, 1457, 100 },
1629  { 2196, 564, 290, 134, 1457, 100 },
1630  { 205, 564, 290, 134, 1457, 100 },
1631  { 486, 564, 290, 134, 1457, 100 },
1632  { 277, 581, 290, 134, 8544, 38 },
1633  { 980, 780, 8, 181, 1, 121 },
1634  { 1196, 780, 8, 181, 1, 121 },
1635  { 1412, 780, 8, 181, 1, 121 },
1636  { 1624, 780, 8, 181, 1, 121 },
1637  { 1836, 780, 8, 181, 1, 121 },
1638  { 2048, 780, 8, 181, 1, 121 },
1639  { 2252, 780, 8, 181, 1, 121 },
1640  { 56, 780, 8, 181, 1, 121 },
1641  { 344, 780, 8, 181, 1, 121 },
1642  { 622, 780, 8, 181, 1, 121 },
1643  { 840, 780, 8, 181, 1, 121 },
1644  { 1056, 780, 8, 181, 1, 121 },
1645  { 1272, 780, 8, 181, 1, 121 },
1646  { 1484, 780, 8, 181, 1, 121 },
1647  { 1696, 780, 8, 181, 1, 121 },
1648  { 1908, 780, 8, 181, 1, 121 },
1649  { 2120, 780, 8, 181, 1, 121 },
1650  { 129, 780, 8, 181, 1, 121 },
1651  { 418, 780, 8, 181, 1, 121 },
1652  { 697, 780, 8, 181, 1, 121 },
1653  { 916, 780, 8, 181, 1, 121 },
1654  { 1132, 780, 8, 181, 1, 121 },
1655  { 1348, 780, 8, 181, 1, 121 },
1656  { 1560, 780, 8, 181, 1, 121 },
1657  { 1772, 780, 8, 181, 1, 121 },
1658  { 1984, 780, 8, 181, 1, 121 },
1659  { 2188, 780, 8, 181, 1, 121 },
1660  { 197, 780, 8, 181, 1, 121 },
1661  { 478, 780, 8, 181, 1, 121 },
1662  { 269, 826, 8, 181, 384, 130 },
1663  { 546, 688, 8, 181, 944, 105 },
1664  { 763, 734, 8, 181, 6864, 43 },
1665  { 767, 598, 545, 151, 625, 139 },
1666  { 983, 598, 180, 151, 625, 139 },
1667  { 1199, 598, 180, 151, 625, 139 },
1668  { 1415, 598, 180, 151, 625, 139 },
1669  { 1627, 598, 180, 151, 625, 139 },
1670  { 1839, 598, 180, 151, 625, 139 },
1671  { 2051, 598, 180, 151, 625, 139 },
1672  { 2255, 598, 180, 151, 625, 139 },
1673  { 59, 598, 180, 151, 625, 139 },
1674  { 347, 598, 180, 151, 625, 139 },
1675  { 625, 598, 180, 151, 625, 139 },
1676  { 844, 598, 180, 151, 625, 139 },
1677  { 1060, 598, 180, 151, 625, 139 },
1678  { 1276, 598, 180, 151, 625, 139 },
1679  { 1488, 598, 180, 151, 625, 139 },
1680  { 1700, 598, 180, 151, 625, 139 },
1681  { 1912, 598, 180, 151, 625, 139 },
1682  { 2124, 598, 180, 151, 625, 139 },
1683  { 133, 598, 180, 151, 625, 139 },
1684  { 422, 598, 180, 151, 625, 139 },
1685  { 701, 598, 180, 151, 625, 139 },
1686  { 920, 598, 180, 151, 625, 139 },
1687  { 1136, 598, 180, 151, 625, 139 },
1688  { 1352, 598, 180, 151, 625, 139 },
1689  { 1564, 598, 180, 151, 625, 139 },
1690  { 1776, 598, 180, 151, 625, 139 },
1691  { 1988, 598, 180, 151, 625, 139 },
1692  { 2192, 598, 180, 151, 625, 139 },
1693  { 201, 598, 180, 151, 625, 139 },
1694  { 482, 598, 180, 151, 625, 139 },
1695  { 273, 628, 180, 151, 1152, 114 },
1696  { 550, 658, 180, 151, 8096, 52 },
1697};
1698
1699  // FPR8 Register Class...
1700  static const MCPhysReg FPR8[] = {
1701    AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, AArch64_B30, AArch64_B31,
1702  };
1703  // FPR8 Bit set.
1704  static const uint8_t FPR8Bits[] = {
1705    0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
1706  };
1707  // FPR16 Register Class...
1708  static const MCPhysReg FPR16[] = {
1709    AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, AArch64_H30, AArch64_H31,
1710  };
1711  // FPR16 Bit set.
1712  static const uint8_t FPR16Bits[] = {
1713    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
1714  };
1715  // PPR Register Class...
1716  static const MCPhysReg PPR[] = {
1717    AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, AArch64_P4, AArch64_P5, AArch64_P6, AArch64_P7, AArch64_P8, AArch64_P9, AArch64_P10, AArch64_P11, AArch64_P12, AArch64_P13, AArch64_P14, AArch64_P15,
1718  };
1719  // PPR Bit set.
1720  static const uint8_t PPRBits[] = {
1721    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
1722  };
1723  // PPR_3b Register Class...
1724  static const MCPhysReg PPR_3b[] = {
1725    AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, AArch64_P4, AArch64_P5, AArch64_P6, AArch64_P7,
1726  };
1727  // PPR_3b Bit set.
1728  static const uint8_t PPR_3bBits[] = {
1729    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
1730  };
1731  // GPR32all Register Class...
1732  static const MCPhysReg GPR32all[] = {
1733    AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR, AArch64_WSP,
1734  };
1735  // GPR32all Bit set.
1736  static const uint8_t GPR32allBits[] = {
1737    0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff,
1738  };
1739  // FPR32 Register Class...
1740  static const MCPhysReg FPR32[] = {
1741    AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, AArch64_S30, AArch64_S31,
1742  };
1743  // FPR32 Bit set.
1744  static const uint8_t FPR32Bits[] = {
1745    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
1746  };
1747  // GPR32 Register Class...
1748  static const MCPhysReg GPR32[] = {
1749    AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR,
1750  };
1751  // GPR32 Bit set.
1752  static const uint8_t GPR32Bits[] = {
1753    0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff,
1754  };
1755  // GPR32sp Register Class...
1756  static const MCPhysReg GPR32sp[] = {
1757    AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WSP,
1758  };
1759  // GPR32sp Bit set.
1760  static const uint8_t GPR32spBits[] = {
1761    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff,
1762  };
1763  // GPR32common Register Class...
1764  static const MCPhysReg GPR32common[] = {
1765    AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30,
1766  };
1767  // GPR32common Bit set.
1768  static const uint8_t GPR32commonBits[] = {
1769    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff,
1770  };
1771  // CCR Register Class...
1772  static const MCPhysReg CCR[] = {
1773    AArch64_NZCV,
1774  };
1775  // CCR Bit set.
1776  static const uint8_t CCRBits[] = {
1777    0x10,
1778  };
1779  // GPR32sponly Register Class...
1780  static const MCPhysReg GPR32sponly[] = {
1781    AArch64_WSP,
1782  };
1783  // GPR32sponly Bit set.
1784  static const uint8_t GPR32sponlyBits[] = {
1785    0x40,
1786  };
1787  // WSeqPairsClass Register Class...
1788  static const MCPhysReg WSeqPairsClass[] = {
1789    AArch64_W0_W1, AArch64_W1_W2, AArch64_W2_W3, AArch64_W3_W4, AArch64_W4_W5, AArch64_W5_W6, AArch64_W6_W7, AArch64_W7_W8, AArch64_W8_W9, AArch64_W9_W10, AArch64_W10_W11, AArch64_W11_W12, AArch64_W12_W13, AArch64_W13_W14, AArch64_W14_W15, AArch64_W15_W16, AArch64_W16_W17, AArch64_W17_W18, AArch64_W18_W19, AArch64_W19_W20, AArch64_W20_W21, AArch64_W21_W22, AArch64_W22_W23, AArch64_W23_W24, AArch64_W24_W25, AArch64_W25_W26, AArch64_W26_W27, AArch64_W27_W28, AArch64_W28_W29, AArch64_W29_W30, AArch64_W30_WZR, AArch64_WZR_W0,
1790  };
1791  // WSeqPairsClass Bit set.
1792  static const uint8_t WSeqPairsClassBits[] = {
1793    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
1794  };
1795  // WSeqPairsClass_with_sube32_in_GPR32common Register Class...
1796  static const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common[] = {
1797    AArch64_W0_W1, AArch64_W1_W2, AArch64_W2_W3, AArch64_W3_W4, AArch64_W4_W5, AArch64_W5_W6, AArch64_W6_W7, AArch64_W7_W8, AArch64_W8_W9, AArch64_W9_W10, AArch64_W10_W11, AArch64_W11_W12, AArch64_W12_W13, AArch64_W13_W14, AArch64_W14_W15, AArch64_W15_W16, AArch64_W16_W17, AArch64_W17_W18, AArch64_W18_W19, AArch64_W19_W20, AArch64_W20_W21, AArch64_W21_W22, AArch64_W22_W23, AArch64_W23_W24, AArch64_W24_W25, AArch64_W25_W26, AArch64_W26_W27, AArch64_W27_W28, AArch64_W28_W29, AArch64_W29_W30, AArch64_W30_WZR,
1798  };
1799  // WSeqPairsClass_with_sube32_in_GPR32common Bit set.
1800  static const uint8_t WSeqPairsClass_with_sube32_in_GPR32commonBits[] = {
1801    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f,
1802  };
1803  // WSeqPairsClass_with_subo32_in_GPR32common Register Class...
1804  static const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
1805    AArch64_W0_W1, AArch64_W1_W2, AArch64_W2_W3, AArch64_W3_W4, AArch64_W4_W5, AArch64_W5_W6, AArch64_W6_W7, AArch64_W7_W8, AArch64_W8_W9, AArch64_W9_W10, AArch64_W10_W11, AArch64_W11_W12, AArch64_W12_W13, AArch64_W13_W14, AArch64_W14_W15, AArch64_W15_W16, AArch64_W16_W17, AArch64_W17_W18, AArch64_W18_W19, AArch64_W19_W20, AArch64_W20_W21, AArch64_W21_W22, AArch64_W22_W23, AArch64_W23_W24, AArch64_W24_W25, AArch64_W25_W26, AArch64_W26_W27, AArch64_W27_W28, AArch64_W28_W29, AArch64_W29_W30, AArch64_WZR_W0,
1806  };
1807  // WSeqPairsClass_with_subo32_in_GPR32common Bit set.
1808  static const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
1809    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f,
1810  };
1811  // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Register Class...
1812  static const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common[] = {
1813    AArch64_W0_W1, AArch64_W1_W2, AArch64_W2_W3, AArch64_W3_W4, AArch64_W4_W5, AArch64_W5_W6, AArch64_W6_W7, AArch64_W7_W8, AArch64_W8_W9, AArch64_W9_W10, AArch64_W10_W11, AArch64_W11_W12, AArch64_W12_W13, AArch64_W13_W14, AArch64_W14_W15, AArch64_W15_W16, AArch64_W16_W17, AArch64_W17_W18, AArch64_W18_W19, AArch64_W19_W20, AArch64_W20_W21, AArch64_W21_W22, AArch64_W22_W23, AArch64_W23_W24, AArch64_W24_W25, AArch64_W25_W26, AArch64_W26_W27, AArch64_W27_W28, AArch64_W28_W29, AArch64_W29_W30,
1814  };
1815  // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Bit set.
1816  static const uint8_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
1817    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f,
1818  };
1819  // GPR64all Register Class...
1820  static const MCPhysReg GPR64all[] = {
1821    AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR, AArch64_SP,
1822  };
1823  // GPR64all Bit set.
1824  static const uint8_t GPR64allBits[] = {
1825    0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f,
1826  };
1827  // FPR64 Register Class...
1828  static const MCPhysReg FPR64[] = {
1829    AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, AArch64_D30, AArch64_D31,
1830  };
1831  // FPR64 Bit set.
1832  static const uint8_t FPR64Bits[] = {
1833    0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
1834  };
1835  // GPR64 Register Class...
1836  static const MCPhysReg GPR64[] = {
1837    AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR,
1838  };
1839  // GPR64 Bit set.
1840  static const uint8_t GPR64Bits[] = {
1841    0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f,
1842  };
1843  // GPR64sp Register Class...
1844  static const MCPhysReg GPR64sp[] = {
1845    AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_SP,
1846  };
1847  // GPR64sp Bit set.
1848  static const uint8_t GPR64spBits[] = {
1849    0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f,
1850  };
1851  // GPR64common Register Class...
1852  static const MCPhysReg GPR64common[] = {
1853    AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR,
1854  };
1855  // GPR64common Bit set.
1856  static const uint8_t GPR64commonBits[] = {
1857    0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f,
1858  };
1859  // tcGPR64 Register Class...
1860  static const MCPhysReg tcGPR64[] = {
1861    AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18,
1862  };
1863  // tcGPR64 Bit set.
1864  static const uint8_t tcGPR64Bits[] = {
1865    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07,
1866  };
1867  // GPR64sponly Register Class...
1868  static const MCPhysReg GPR64sponly[] = {
1869    AArch64_SP,
1870  };
1871  // GPR64sponly Bit set.
1872  static const uint8_t GPR64sponlyBits[] = {
1873    0x20,
1874  };
1875  // DD Register Class...
1876  static const MCPhysReg DD[] = {
1877    AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0,
1878  };
1879  // DD Bit set.
1880  static const uint8_t DDBits[] = {
1881    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
1882  };
1883  // XSeqPairsClass Register Class...
1884  static const MCPhysReg XSeqPairsClass[] = {
1885    AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, AArch64_X19_X20, AArch64_X20_X21, AArch64_X21_X22, AArch64_X22_X23, AArch64_X23_X24, AArch64_X24_X25, AArch64_X25_X26, AArch64_X26_X27, AArch64_X27_X28, AArch64_X28_FP, AArch64_FP_LR, AArch64_LR_XZR, AArch64_XZR_X0,
1886  };
1887  // XSeqPairsClass Bit set.
1888  static const uint8_t XSeqPairsClassBits[] = {
1889    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
1890  };
1891  // XSeqPairsClass_with_sub_32_in_GPR32common Register Class...
1892  static const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common[] = {
1893    AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, AArch64_X19_X20, AArch64_X20_X21, AArch64_X21_X22, AArch64_X22_X23, AArch64_X23_X24, AArch64_X24_X25, AArch64_X25_X26, AArch64_X26_X27, AArch64_X27_X28, AArch64_X28_FP, AArch64_FP_LR, AArch64_LR_XZR,
1894  };
1895  // XSeqPairsClass_with_sub_32_in_GPR32common Bit set.
1896  static const uint8_t XSeqPairsClass_with_sub_32_in_GPR32commonBits[] = {
1897    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xff, 0xff, 0xff, 0x1f,
1898  };
1899  // XSeqPairsClass_with_subo64_in_GPR64common Register Class...
1900  static const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
1901    AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, AArch64_X19_X20, AArch64_X20_X21, AArch64_X21_X22, AArch64_X22_X23, AArch64_X23_X24, AArch64_X24_X25, AArch64_X25_X26, AArch64_X26_X27, AArch64_X27_X28, AArch64_X28_FP, AArch64_FP_LR, AArch64_XZR_X0,
1902  };
1903  // XSeqPairsClass_with_subo64_in_GPR64common Bit set.
1904  static const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
1905    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f,
1906  };
1907  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Register Class...
1908  static const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common[] = {
1909    AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, AArch64_X19_X20, AArch64_X20_X21, AArch64_X21_X22, AArch64_X22_X23, AArch64_X23_X24, AArch64_X24_X25, AArch64_X25_X26, AArch64_X26_X27, AArch64_X27_X28, AArch64_X28_FP, AArch64_FP_LR,
1910  };
1911  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Bit set.
1912  static const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
1913    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0xff, 0xff, 0xff, 0x1f,
1914  };
1915  // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class...
1916  static const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
1917    AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19,
1918  };
1919  // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set.
1920  static const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = {
1921    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x0f,
1922  };
1923  // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
1924  static const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
1925    AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_XZR_X0,
1926  };
1927  // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
1928  static const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
1929    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xfe, 0xff, 0x07,
1930  };
1931  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
1932  static const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64[] = {
1933    AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18,
1934  };
1935  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
1936  static const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
1937    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x07,
1938  };
1939  // FPR128 Register Class...
1940  static const MCPhysReg FPR128[] = {
1941    AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, AArch64_Q30, AArch64_Q31,
1942  };
1943  // FPR128 Bit set.
1944  static const uint8_t FPR128Bits[] = {
1945    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
1946  };
1947  // ZPR Register Class...
1948  static const MCPhysReg ZPR[] = {
1949    AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, AArch64_Z8, AArch64_Z9, AArch64_Z10, AArch64_Z11, AArch64_Z12, AArch64_Z13, AArch64_Z14, AArch64_Z15, AArch64_Z16, AArch64_Z17, AArch64_Z18, AArch64_Z19, AArch64_Z20, AArch64_Z21, AArch64_Z22, AArch64_Z23, AArch64_Z24, AArch64_Z25, AArch64_Z26, AArch64_Z27, AArch64_Z28, AArch64_Z29, AArch64_Z30, AArch64_Z31,
1950  };
1951  // ZPR Bit set.
1952  static const uint8_t ZPRBits[] = {
1953    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
1954  };
1955  // FPR128_lo Register Class...
1956  static const MCPhysReg FPR128_lo[] = {
1957    AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15,
1958  };
1959  // FPR128_lo Bit set.
1960  static const uint8_t FPR128_loBits[] = {
1961    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
1962  };
1963  // ZPR_4b Register Class...
1964  static const MCPhysReg ZPR_4b[] = {
1965    AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, AArch64_Z8, AArch64_Z9, AArch64_Z10, AArch64_Z11, AArch64_Z12, AArch64_Z13, AArch64_Z14, AArch64_Z15,
1966  };
1967  // ZPR_4b Bit set.
1968  static const uint8_t ZPR_4bBits[] = {
1969    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
1970  };
1971  // ZPR_3b Register Class...
1972  static const MCPhysReg ZPR_3b[] = {
1973    AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7,
1974  };
1975  // ZPR_3b Bit set.
1976  static const uint8_t ZPR_3bBits[] = {
1977    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1978  };
1979  // DDD Register Class...
1980  static const MCPhysReg DDD[] = {
1981    AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, AArch64_D30_D31_D0, AArch64_D31_D0_D1,
1982  };
1983  // DDD Bit set.
1984  static const uint8_t DDDBits[] = {
1985    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
1986  };
1987  // DDDD Register Class...
1988  static const MCPhysReg DDDD[] = {
1989    AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2,
1990  };
1991  // DDDD Bit set.
1992  static const uint8_t DDDDBits[] = {
1993    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
1994  };
1995  // QQ Register Class...
1996  static const MCPhysReg QQ[] = {
1997    AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0,
1998  };
1999  // QQ Bit set.
2000  static const uint8_t QQBits[] = {
2001    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2002  };
2003  // ZPR2 Register Class...
2004  static const MCPhysReg ZPR2[] = {
2005    AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16, AArch64_Z16_Z17, AArch64_Z17_Z18, AArch64_Z18_Z19, AArch64_Z19_Z20, AArch64_Z20_Z21, AArch64_Z21_Z22, AArch64_Z22_Z23, AArch64_Z23_Z24, AArch64_Z24_Z25, AArch64_Z25_Z26, AArch64_Z26_Z27, AArch64_Z27_Z28, AArch64_Z28_Z29, AArch64_Z29_Z30, AArch64_Z30_Z31, AArch64_Z31_Z0,
2006  };
2007  // ZPR2 Bit set.
2008  static const uint8_t ZPR2Bits[] = {
2009    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2010  };
2011  // QQ_with_qsub0_in_FPR128_lo Register Class...
2012  static const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
2013    AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16,
2014  };
2015  // QQ_with_qsub0_in_FPR128_lo Bit set.
2016  static const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
2017    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2018  };
2019  // QQ_with_qsub1_in_FPR128_lo Register Class...
2020  static const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
2021    AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q31_Q0,
2022  };
2023  // QQ_with_qsub1_in_FPR128_lo Bit set.
2024  static const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
2025    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2026  };
2027  // ZPR2_with_zsub1_in_ZPR_4b Register Class...
2028  static const MCPhysReg ZPR2_with_zsub1_in_ZPR_4b[] = {
2029    AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z31_Z0,
2030  };
2031  // ZPR2_with_zsub1_in_ZPR_4b Bit set.
2032  static const uint8_t ZPR2_with_zsub1_in_ZPR_4bBits[] = {
2033    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2034  };
2035  // ZPR2_with_zsub_in_FPR128_lo Register Class...
2036  static const MCPhysReg ZPR2_with_zsub_in_FPR128_lo[] = {
2037    AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16,
2038  };
2039  // ZPR2_with_zsub_in_FPR128_lo Bit set.
2040  static const uint8_t ZPR2_with_zsub_in_FPR128_loBits[] = {
2041    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2042  };
2043  // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
2044  static const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
2045    AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15,
2046  };
2047  // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
2048  static const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
2049    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2050  };
2051  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Register Class...
2052  static const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b[] = {
2053    AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15,
2054  };
2055  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Bit set.
2056  static const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits[] = {
2057    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2058  };
2059  // ZPR2_with_zsub0_in_ZPR_3b Register Class...
2060  static const MCPhysReg ZPR2_with_zsub0_in_ZPR_3b[] = {
2061    AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8,
2062  };
2063  // ZPR2_with_zsub0_in_ZPR_3b Bit set.
2064  static const uint8_t ZPR2_with_zsub0_in_ZPR_3bBits[] = {
2065    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
2066  };
2067  // ZPR2_with_zsub1_in_ZPR_3b Register Class...
2068  static const MCPhysReg ZPR2_with_zsub1_in_ZPR_3b[] = {
2069    AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z31_Z0,
2070  };
2071  // ZPR2_with_zsub1_in_ZPR_3b Bit set.
2072  static const uint8_t ZPR2_with_zsub1_in_ZPR_3bBits[] = {
2073    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10,
2074  };
2075  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Register Class...
2076  static const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b[] = {
2077    AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7,
2078  };
2079  // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Bit set.
2080  static const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits[] = {
2081    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
2082  };
2083  // QQQ Register Class...
2084  static const MCPhysReg QQQ[] = {
2085    AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1,
2086  };
2087  // QQQ Bit set.
2088  static const uint8_t QQQBits[] = {
2089    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2090  };
2091  // ZPR3 Register Class...
2092  static const MCPhysReg ZPR3[] = {
2093    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, AArch64_Z15_Z16_Z17, AArch64_Z16_Z17_Z18, AArch64_Z17_Z18_Z19, AArch64_Z18_Z19_Z20, AArch64_Z19_Z20_Z21, AArch64_Z20_Z21_Z22, AArch64_Z21_Z22_Z23, AArch64_Z22_Z23_Z24, AArch64_Z23_Z24_Z25, AArch64_Z24_Z25_Z26, AArch64_Z25_Z26_Z27, AArch64_Z26_Z27_Z28, AArch64_Z27_Z28_Z29, AArch64_Z28_Z29_Z30, AArch64_Z29_Z30_Z31, AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1,
2094  };
2095  // ZPR3 Bit set.
2096  static const uint8_t ZPR3Bits[] = {
2097    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2098  };
2099  // QQQ_with_qsub0_in_FPR128_lo Register Class...
2100  static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
2101    AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17,
2102  };
2103  // QQQ_with_qsub0_in_FPR128_lo Bit set.
2104  static const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
2105    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2106  };
2107  // QQQ_with_qsub1_in_FPR128_lo Register Class...
2108  static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
2109    AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q31_Q0_Q1,
2110  };
2111  // QQQ_with_qsub1_in_FPR128_lo Bit set.
2112  static const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
2113    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2114  };
2115  // QQQ_with_qsub2_in_FPR128_lo Register Class...
2116  static const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
2117    AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1,
2118  };
2119  // QQQ_with_qsub2_in_FPR128_lo Bit set.
2120  static const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
2121    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18,
2122  };
2123  // ZPR3_with_zsub1_in_ZPR_4b Register Class...
2124  static const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b[] = {
2125    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, AArch64_Z31_Z0_Z1,
2126  };
2127  // ZPR3_with_zsub1_in_ZPR_4b Bit set.
2128  static const uint8_t ZPR3_with_zsub1_in_ZPR_4bBits[] = {
2129    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2130  };
2131  // ZPR3_with_zsub2_in_ZPR_4b Register Class...
2132  static const MCPhysReg ZPR3_with_zsub2_in_ZPR_4b[] = {
2133    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1,
2134  };
2135  // ZPR3_with_zsub2_in_ZPR_4b Bit set.
2136  static const uint8_t ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2137    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18,
2138  };
2139  // ZPR3_with_zsub_in_FPR128_lo Register Class...
2140  static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo[] = {
2141    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, AArch64_Z15_Z16_Z17,
2142  };
2143  // ZPR3_with_zsub_in_FPR128_lo Bit set.
2144  static const uint8_t ZPR3_with_zsub_in_FPR128_loBits[] = {
2145    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2146  };
2147  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
2148  static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
2149    AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16,
2150  };
2151  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
2152  static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
2153    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2154  };
2155  // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
2156  static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2157    AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q31_Q0_Q1,
2158  };
2159  // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
2160  static const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
2161    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10,
2162  };
2163  // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
2164  static const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2165    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z31_Z0_Z1,
2166  };
2167  // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
2168  static const uint8_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2169    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10,
2170  };
2171  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Register Class...
2172  static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b[] = {
2173    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16,
2174  };
2175  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Bit set.
2176  static const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits[] = {
2177    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2178  };
2179  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
2180  static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
2181    AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15,
2182  };
2183  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
2184  static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
2185    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
2186  };
2187  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Register Class...
2188  static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b[] = {
2189    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15,
2190  };
2191  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Bit set.
2192  static const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = {
2193    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
2194  };
2195  // ZPR3_with_zsub0_in_ZPR_3b Register Class...
2196  static const MCPhysReg ZPR3_with_zsub0_in_ZPR_3b[] = {
2197    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9,
2198  };
2199  // ZPR3_with_zsub0_in_ZPR_3b Bit set.
2200  static const uint8_t ZPR3_with_zsub0_in_ZPR_3bBits[] = {
2201    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
2202  };
2203  // ZPR3_with_zsub1_in_ZPR_3b Register Class...
2204  static const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b[] = {
2205    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z31_Z0_Z1,
2206  };
2207  // ZPR3_with_zsub1_in_ZPR_3b Bit set.
2208  static const uint8_t ZPR3_with_zsub1_in_ZPR_3bBits[] = {
2209    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10,
2210  };
2211  // ZPR3_with_zsub2_in_ZPR_3b Register Class...
2212  static const MCPhysReg ZPR3_with_zsub2_in_ZPR_3b[] = {
2213    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1,
2214  };
2215  // ZPR3_with_zsub2_in_ZPR_3b Bit set.
2216  static const uint8_t ZPR3_with_zsub2_in_ZPR_3bBits[] = {
2217    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18,
2218  };
2219  // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
2220  static const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
2221    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z31_Z0_Z1,
2222  };
2223  // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
2224  static const uint8_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
2225    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10,
2226  };
2227  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Register Class...
2228  static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b[] = {
2229    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8,
2230  };
2231  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Bit set.
2232  static const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits[] = {
2233    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
2234  };
2235  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Register Class...
2236  static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b[] = {
2237    AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7,
2238  };
2239  // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Bit set.
2240  static const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = {
2241    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07,
2242  };
2243  // QQQQ Register Class...
2244  static const MCPhysReg QQQQ[] = {
2245    AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
2246  };
2247  // QQQQ Bit set.
2248  static const uint8_t QQQQBits[] = {
2249    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2250  };
2251  // ZPR4 Register Class...
2252  static const MCPhysReg ZPR4[] = {
2253    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, AArch64_Z15_Z16_Z17_Z18, AArch64_Z16_Z17_Z18_Z19, AArch64_Z17_Z18_Z19_Z20, AArch64_Z18_Z19_Z20_Z21, AArch64_Z19_Z20_Z21_Z22, AArch64_Z20_Z21_Z22_Z23, AArch64_Z21_Z22_Z23_Z24, AArch64_Z22_Z23_Z24_Z25, AArch64_Z23_Z24_Z25_Z26, AArch64_Z24_Z25_Z26_Z27, AArch64_Z25_Z26_Z27_Z28, AArch64_Z26_Z27_Z28_Z29, AArch64_Z27_Z28_Z29_Z30, AArch64_Z28_Z29_Z30_Z31, AArch64_Z29_Z30_Z31_Z0, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2,
2254  };
2255  // ZPR4 Bit set.
2256  static const uint8_t ZPR4Bits[] = {
2257    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
2258  };
2259  // QQQQ_with_qsub0_in_FPR128_lo Register Class...
2260  static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
2261    AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18,
2262  };
2263  // QQQQ_with_qsub0_in_FPR128_lo Bit set.
2264  static const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
2265    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2266  };
2267  // QQQQ_with_qsub1_in_FPR128_lo Register Class...
2268  static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
2269    AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q31_Q0_Q1_Q2,
2270  };
2271  // QQQQ_with_qsub1_in_FPR128_lo Bit set.
2272  static const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
2273    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2274  };
2275  // QQQQ_with_qsub2_in_FPR128_lo Register Class...
2276  static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
2277    AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
2278  };
2279  // QQQQ_with_qsub2_in_FPR128_lo Bit set.
2280  static const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
2281    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18,
2282  };
2283  // QQQQ_with_qsub3_in_FPR128_lo Register Class...
2284  static const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
2285    AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
2286  };
2287  // QQQQ_with_qsub3_in_FPR128_lo Bit set.
2288  static const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
2289    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c,
2290  };
2291  // ZPR4_with_zsub1_in_ZPR_4b Register Class...
2292  static const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b[] = {
2293    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, AArch64_Z31_Z0_Z1_Z2,
2294  };
2295  // ZPR4_with_zsub1_in_ZPR_4b Bit set.
2296  static const uint8_t ZPR4_with_zsub1_in_ZPR_4bBits[] = {
2297    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10,
2298  };
2299  // ZPR4_with_zsub2_in_ZPR_4b Register Class...
2300  static const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b[] = {
2301    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2,
2302  };
2303  // ZPR4_with_zsub2_in_ZPR_4b Bit set.
2304  static const uint8_t ZPR4_with_zsub2_in_ZPR_4bBits[] = {
2305    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18,
2306  };
2307  // ZPR4_with_zsub3_in_ZPR_4b Register Class...
2308  static const MCPhysReg ZPR4_with_zsub3_in_ZPR_4b[] = {
2309    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z29_Z30_Z31_Z0, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2,
2310  };
2311  // ZPR4_with_zsub3_in_ZPR_4b Bit set.
2312  static const uint8_t ZPR4_with_zsub3_in_ZPR_4bBits[] = {
2313    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c,
2314  };
2315  // ZPR4_with_zsub_in_FPR128_lo Register Class...
2316  static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo[] = {
2317    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, AArch64_Z15_Z16_Z17_Z18,
2318  };
2319  // ZPR4_with_zsub_in_FPR128_lo Bit set.
2320  static const uint8_t ZPR4_with_zsub_in_FPR128_loBits[] = {
2321    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
2322  };
2323  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
2324  static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
2325    AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17,
2326  };
2327  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
2328  static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
2329    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2330  };
2331  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
2332  static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
2333    AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q31_Q0_Q1_Q2,
2334  };
2335  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
2336  static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
2337    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10,
2338  };
2339  // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
2340  static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
2341    AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
2342  };
2343  // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
2344  static const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
2345    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18,
2346  };
2347  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
2348  static const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
2349    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z31_Z0_Z1_Z2,
2350  };
2351  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
2352  static const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
2353    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10,
2354  };
2355  // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
2356  static const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
2357    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2,
2358  };
2359  // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
2360  static const uint8_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
2361    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18,
2362  };
2363  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Register Class...
2364  static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b[] = {
2365    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17,
2366  };
2367  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Bit set.
2368  static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits[] = {
2369    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
2370  };
2371  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
2372  static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
2373    AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16,
2374  };
2375  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
2376  static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
2377    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
2378  };
2379  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
2380  static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
2381    AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q31_Q0_Q1_Q2,
2382  };
2383  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
2384  static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
2385    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10,
2386  };
2387  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
2388  static const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
2389    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z31_Z0_Z1_Z2,
2390  };
2391  // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
2392  static const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
2393    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10,
2394  };
2395  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Register Class...
2396  static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b[] = {
2397    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16,
2398  };
2399  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Bit set.
2400  static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = {
2401    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
2402  };
2403  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
2404  static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
2405    AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15,
2406  };
2407  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
2408  static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
2409    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03,
2410  };
2411  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Register Class...
2412  static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b[] = {
2413    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15,
2414  };
2415  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Bit set.
2416  static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = {
2417    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03,
2418  };
2419  // ZPR4_with_zsub0_in_ZPR_3b Register Class...
2420  static const MCPhysReg ZPR4_with_zsub0_in_ZPR_3b[] = {
2421    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10,
2422  };
2423  // ZPR4_with_zsub0_in_ZPR_3b Bit set.
2424  static const uint8_t ZPR4_with_zsub0_in_ZPR_3bBits[] = {
2425    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
2426  };
2427  // ZPR4_with_zsub1_in_ZPR_3b Register Class...
2428  static const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b[] = {
2429    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z31_Z0_Z1_Z2,
2430  };
2431  // ZPR4_with_zsub1_in_ZPR_3b Bit set.
2432  static const uint8_t ZPR4_with_zsub1_in_ZPR_3bBits[] = {
2433    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10,
2434  };
2435  // ZPR4_with_zsub2_in_ZPR_3b Register Class...
2436  static const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b[] = {
2437    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2,
2438  };
2439  // ZPR4_with_zsub2_in_ZPR_3b Bit set.
2440  static const uint8_t ZPR4_with_zsub2_in_ZPR_3bBits[] = {
2441    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18,
2442  };
2443  // ZPR4_with_zsub3_in_ZPR_3b Register Class...
2444  static const MCPhysReg ZPR4_with_zsub3_in_ZPR_3b[] = {
2445    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z29_Z30_Z31_Z0, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2,
2446  };
2447  // ZPR4_with_zsub3_in_ZPR_3b Bit set.
2448  static const uint8_t ZPR4_with_zsub3_in_ZPR_3bBits[] = {
2449    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x1c,
2450  };
2451  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
2452  static const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
2453    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z31_Z0_Z1_Z2,
2454  };
2455  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
2456  static const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
2457    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10,
2458  };
2459  // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
2460  static const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
2461    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2,
2462  };
2463  // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
2464  static const uint8_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
2465    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x18,
2466  };
2467  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Register Class...
2468  static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b[] = {
2469    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9,
2470  };
2471  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Bit set.
2472  static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits[] = {
2473    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
2474  };
2475  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
2476  static const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
2477    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z31_Z0_Z1_Z2,
2478  };
2479  // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
2480  static const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
2481    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x10,
2482  };
2483  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Register Class...
2484  static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b[] = {
2485    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8,
2486  };
2487  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Bit set.
2488  static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = {
2489    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07,
2490  };
2491  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Register Class...
2492  static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b[] = {
2493    AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7,
2494  };
2495  // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Bit set.
2496  static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = {
2497    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03,
2498  };
2499
2500
2501static const MCRegisterClass AArch64MCRegisterClasses[] = {
2502  { FPR8, FPR8Bits, sizeof(FPR8Bits) },
2503  { FPR16, FPR16Bits, sizeof(FPR16Bits) },
2504  { PPR, PPRBits, sizeof(PPRBits) },
2505  { PPR_3b, PPR_3bBits, sizeof(PPR_3bBits) },
2506  { GPR32all, GPR32allBits, sizeof(GPR32allBits) },
2507  { FPR32, FPR32Bits, sizeof(FPR32Bits) },
2508  { GPR32, GPR32Bits, sizeof(GPR32Bits) },
2509  { GPR32sp, GPR32spBits, sizeof(GPR32spBits) },
2510  { GPR32common, GPR32commonBits, sizeof(GPR32commonBits) },
2511  { CCR, CCRBits, sizeof(CCRBits) },
2512  { GPR32sponly, GPR32sponlyBits, sizeof(GPR32sponlyBits) },
2513  { WSeqPairsClass, WSeqPairsClassBits, sizeof(WSeqPairsClassBits) },
2514  { WSeqPairsClass_with_sube32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32commonBits, sizeof(WSeqPairsClass_with_sube32_in_GPR32commonBits) },
2515  { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits) },
2516  { WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits, sizeof(WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits) },
2517  { GPR64all, GPR64allBits, sizeof(GPR64allBits) },
2518  { FPR64, FPR64Bits, sizeof(FPR64Bits) },
2519  { GPR64, GPR64Bits, sizeof(GPR64Bits) },
2520  { GPR64sp, GPR64spBits, sizeof(GPR64spBits) },
2521  { GPR64common, GPR64commonBits, sizeof(GPR64commonBits) },
2522  { tcGPR64, tcGPR64Bits, sizeof(tcGPR64Bits) },
2523  { GPR64sponly, GPR64sponlyBits, sizeof(GPR64sponlyBits) },
2524  { DD, DDBits, sizeof(DDBits) },
2525  { XSeqPairsClass, XSeqPairsClassBits, sizeof(XSeqPairsClassBits) },
2526  { XSeqPairsClass_with_sub_32_in_GPR32common, XSeqPairsClass_with_sub_32_in_GPR32commonBits, sizeof(XSeqPairsClass_with_sub_32_in_GPR32commonBits) },
2527  { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits) },
2528  { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits) },
2529  { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits) },
2530  { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits) },
2531  { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits) },
2532  { FPR128, FPR128Bits, sizeof(FPR128Bits) },
2533  { ZPR, ZPRBits, sizeof(ZPRBits) },
2534  { FPR128_lo, FPR128_loBits, sizeof(FPR128_loBits) },
2535  { ZPR_4b, ZPR_4bBits, sizeof(ZPR_4bBits) },
2536  { ZPR_3b, ZPR_3bBits, sizeof(ZPR_3bBits) },
2537  { DDD, DDDBits, sizeof(DDDBits) },
2538  { DDDD, DDDDBits, sizeof(DDDDBits) },
2539  { QQ, QQBits, sizeof(QQBits) },
2540  { ZPR2, ZPR2Bits, sizeof(ZPR2Bits) },
2541  { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, sizeof(QQ_with_qsub0_in_FPR128_loBits) },
2542  { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, sizeof(QQ_with_qsub1_in_FPR128_loBits) },
2543  { ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub1_in_ZPR_4bBits, sizeof(ZPR2_with_zsub1_in_ZPR_4bBits) },
2544  { ZPR2_with_zsub_in_FPR128_lo, ZPR2_with_zsub_in_FPR128_loBits, sizeof(ZPR2_with_zsub_in_FPR128_loBits) },
2545  { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits) },
2546  { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits) },
2547  { ZPR2_with_zsub0_in_ZPR_3b, ZPR2_with_zsub0_in_ZPR_3bBits, sizeof(ZPR2_with_zsub0_in_ZPR_3bBits) },
2548  { ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub1_in_ZPR_3bBits, sizeof(ZPR2_with_zsub1_in_ZPR_3bBits) },
2549  { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits) },
2550  { QQQ, QQQBits, sizeof(QQQBits) },
2551  { ZPR3, ZPR3Bits, sizeof(ZPR3Bits) },
2552  { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, sizeof(QQQ_with_qsub0_in_FPR128_loBits) },
2553  { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, sizeof(QQQ_with_qsub1_in_FPR128_loBits) },
2554  { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQ_with_qsub2_in_FPR128_loBits) },
2555  { ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4bBits, sizeof(ZPR3_with_zsub1_in_ZPR_4bBits) },
2556  { ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub2_in_ZPR_4bBits, sizeof(ZPR3_with_zsub2_in_ZPR_4bBits) },
2557  { ZPR3_with_zsub_in_FPR128_lo, ZPR3_with_zsub_in_FPR128_loBits, sizeof(ZPR3_with_zsub_in_FPR128_loBits) },
2558  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits) },
2559  { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits) },
2560  { ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits, sizeof(ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits) },
2561  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits) },
2562  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits) },
2563  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits) },
2564  { ZPR3_with_zsub0_in_ZPR_3b, ZPR3_with_zsub0_in_ZPR_3bBits, sizeof(ZPR3_with_zsub0_in_ZPR_3bBits) },
2565  { ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3bBits, sizeof(ZPR3_with_zsub1_in_ZPR_3bBits) },
2566  { ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub2_in_ZPR_3bBits, sizeof(ZPR3_with_zsub2_in_ZPR_3bBits) },
2567  { ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits, sizeof(ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits) },
2568  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits) },
2569  { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits) },
2570  { QQQQ, QQQQBits, sizeof(QQQQBits) },
2571  { ZPR4, ZPR4Bits, sizeof(ZPR4Bits) },
2572  { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, sizeof(QQQQ_with_qsub0_in_FPR128_loBits) },
2573  { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, sizeof(QQQQ_with_qsub1_in_FPR128_loBits) },
2574  { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQQ_with_qsub2_in_FPR128_loBits) },
2575  { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, sizeof(QQQQ_with_qsub3_in_FPR128_loBits) },
2576  { ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4bBits, sizeof(ZPR4_with_zsub1_in_ZPR_4bBits) },
2577  { ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4bBits, sizeof(ZPR4_with_zsub2_in_ZPR_4bBits) },
2578  { ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub3_in_ZPR_4bBits, sizeof(ZPR4_with_zsub3_in_ZPR_4bBits) },
2579  { ZPR4_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_loBits, sizeof(ZPR4_with_zsub_in_FPR128_loBits) },
2580  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits) },
2581  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits) },
2582  { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits) },
2583  { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits) },
2584  { ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, sizeof(ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits) },
2585  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits) },
2586  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits) },
2587  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits) },
2588  { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits) },
2589  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits) },
2590  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits) },
2591  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits) },
2592  { ZPR4_with_zsub0_in_ZPR_3b, ZPR4_with_zsub0_in_ZPR_3bBits, sizeof(ZPR4_with_zsub0_in_ZPR_3bBits) },
2593  { ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3bBits, sizeof(ZPR4_with_zsub1_in_ZPR_3bBits) },
2594  { ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3bBits, sizeof(ZPR4_with_zsub2_in_ZPR_3bBits) },
2595  { ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub3_in_ZPR_3bBits, sizeof(ZPR4_with_zsub3_in_ZPR_3bBits) },
2596  { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits) },
2597  { ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, sizeof(ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits) },
2598  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits) },
2599  { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits) },
2600  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits) },
2601  { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits) },
2602};
2603
2604#endif // GET_REGINFO_MC_DESC
2605