1 /* Table of opcodes for the Motorola M88k family. 2 Copyright 1989, 1990, 1991, 1993, 2001 Free Software Foundation, Inc. 3 4 This file is part of GDB and GAS. 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 2 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 19 20 /* 21 * Disassembler Instruction Table 22 * 23 * The first field of the table is the opcode field. If an opcode 24 * is specified which has any non-opcode bits on, a system error 25 * will occur when the system attempts the install it into the 26 * instruction table. The second parameter is a pointer to the 27 * instruction mnemonic. Each operand is specified by offset, width, 28 * and type. The offset is the bit number of the least significant 29 * bit of the operand with bit 0 being the least significant bit of 30 * the instruction. The width is the number of bits used to specify 31 * the operand. The type specifies the output format to be used for 32 * the operand. The valid formats are: register, register indirect, 33 * hex constant, and bit field specification. The last field is a 34 * pointer to the next instruction in the linked list. These pointers 35 * are initialized by init_disasm(). 36 * 37 * Revision History 38 * 39 * Revision 1.0 11/08/85 Creation date 40 * 1.1 02/05/86 Updated instruction mnemonic table MD 41 * 1.2 06/16/86 Updated SIM_FLAGS for floating point 42 * 1.3 09/20/86 Updated for new encoding 43 * 05/11/89 R. Trawick adapted from Motorola disassembler 44 */ 45 46 #include <stdio.h> 47 48 /* Define the number of bits in the primary opcode field of the instruction, 49 the destination field, the source 1 and source 2 fields. */ 50 51 /* Size of opcode field. */ 52 #define OP 8 53 54 /* Size of destination. */ 55 #define DEST 6 56 57 /* Size of source1. */ 58 #define SOURCE1 6 59 60 /* Size of source2. */ 61 #define SOURCE2 6 62 63 /* Number of registers. */ 64 #define REGs 32 65 66 /* Type definitions. */ 67 68 typedef unsigned int UINT; 69 #define WORD long 70 #define FLAG unsigned 71 #define STATE short 72 73 /* The next four equates define the priorities that the various classes 74 * of instructions have regarding writing results back into registers and 75 * signalling exceptions. */ 76 77 /* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */ 78 #undef PMEM 79 80 /* Integer priority. */ 81 #define PINT 0 82 83 /* Floating point priority. */ 84 #define PFLT 1 85 86 /* Memory priority. */ 87 #define PMEM 2 88 89 /* Not applicable, instruction doesn't write to regs. */ 90 #define NA 3 91 92 /* Highest of these priorities. */ 93 #define HIPRI 3 94 95 /* The instruction registers are an artificial mechanism to speed up 96 * simulator execution. In the real processor, an instruction register 97 * is 32 bits wide. In the simulator, the 32 bit instruction is kept in 98 * a structure field called rawop, and the instruction is partially decoded, 99 * and split into various fields and flags which make up the other fields 100 * of the structure. 101 * The partial decode is done when the instructions are initially loaded 102 * into simulator memory. The simulator code memory is not an array of 103 * 32 bit words, but is an array of instruction register structures. 104 * Yes this wastes memory, but it executes much quicker. 105 */ 106 107 struct IR_FIELDS 108 { 109 unsigned op:OP, 110 dest: DEST, 111 src1: SOURCE1, 112 src2: SOURCE2; 113 int ltncy, 114 extime, 115 /* Writeback priority. */ 116 wb_pri; 117 /* Immediate size. */ 118 unsigned imm_flags:2, 119 /* Register source 1 used. */ 120 rs1_used:1, 121 /* Register source 2 used. */ 122 rs2_used:1, 123 /* Register source/dest. used. */ 124 rsd_used:1, 125 /* Complement. */ 126 c_flag:1, 127 /* Upper half word. */ 128 u_flag:1, 129 /* Execute next. */ 130 n_flag:1, 131 /* Uses writeback slot. */ 132 wb_flag:1, 133 /* Dest size. */ 134 dest_64:1, 135 /* Source 1 size. */ 136 s1_64:1, 137 /* Source 2 size. */ 138 s2_64:1, 139 scale_flag:1, 140 /* Scaled register. */ 141 brk_flg:1; 142 }; 143 144 struct mem_segs 145 { 146 /* Pointer (returned by calloc) to segment. */ 147 struct mem_wrd *seg; 148 149 /* Base load address from file headers. */ 150 unsigned long baseaddr; 151 152 /* Ending address of segment. */ 153 unsigned long endaddr; 154 155 /* Segment control flags (none defined). */ 156 int flags; 157 }; 158 159 #define MAXSEGS (10) /* max number of segment allowed */ 160 #define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */ 161 162 #if 0 163 #define BRK_RD (0x01) /* break on memory read */ 164 #define BRK_WR (0x02) /* break on memory write */ 165 #define BRK_EXEC (0x04) /* break on execution */ 166 #define BRK_CNT (0x08) /* break on terminal count */ 167 #endif 168 169 struct mem_wrd 170 { 171 /* Simulator instruction break down. */ 172 struct IR_FIELDS opcode; 173 union { 174 /* Memory element break down. */ 175 unsigned long l; 176 unsigned short s[2]; 177 unsigned char c[4]; 178 } mem; 179 }; 180 181 /* Size of each 32 bit memory model. */ 182 #define MEMWRDSIZE (sizeof (struct mem_wrd)) 183 184 extern struct mem_segs memory[]; 185 extern struct PROCESSOR m78000; 186 187 struct PROCESSOR 188 { 189 unsigned WORD 190 /* Execute instruction pointer. */ 191 ip, 192 /* Vector base register. */ 193 vbr, 194 /* Processor status register. */ 195 psr; 196 197 /* Source 1. */ 198 WORD S1bus, 199 /* Source 2. */ 200 S2bus, 201 /* Destination. */ 202 Dbus, 203 /* Data address bus. */ 204 DAbus, 205 ALU, 206 /* Data registers. */ 207 Regs[REGs], 208 /* Max clocks before reg is available. */ 209 time_left[REGs], 210 /* Writeback priority of reg. */ 211 wb_pri[REGs], 212 /* Integer unit control regs. */ 213 SFU0_regs[REGs], 214 /* Floating point control regs. */ 215 SFU1_regs[REGs], 216 Scoreboard[REGs], 217 Vbr; 218 unsigned WORD scoreboard, 219 Psw, 220 Tpsw; 221 /* Waiting for a jump instruction. */ 222 FLAG jump_pending:1; 223 }; 224 225 /* Size of immediate field. */ 226 227 #define i26bit 1 228 #define i16bit 2 229 #define i10bit 3 230 231 /* Definitions for fields in psr. */ 232 233 #define mode 31 234 #define rbo 30 235 #define ser 29 236 #define carry 28 237 #define sf7m 11 238 #define sf6m 10 239 #define sf5m 9 240 #define sf4m 8 241 #define sf3m 7 242 #define sf2m 6 243 #define sf1m 5 244 #define mam 4 245 #define inm 3 246 #define exm 2 247 #define trm 1 248 #define ovfm 0 249 250 /* The 1 clock operations. */ 251 252 #define ADDU 1 253 #define ADDC 2 254 #define ADDUC 3 255 #define ADD 4 256 257 #define SUBU ADD+1 258 #define SUBB ADD+2 259 #define SUBUB ADD+3 260 #define SUB ADD+4 261 262 #define AND_ ADD+5 263 #define OR ADD+6 264 #define XOR ADD+7 265 #define CMP ADD+8 266 267 /* Loads. */ 268 269 #define LDAB CMP+1 270 #define LDAH CMP+2 271 #define LDA CMP+3 272 #define LDAD CMP+4 273 274 #define LDB LDAD+1 275 #define LDH LDAD+2 276 #define LD LDAD+3 277 #define LDD LDAD+4 278 #define LDBU LDAD+5 279 #define LDHU LDAD+6 280 281 /* Stores. */ 282 283 #define STB LDHU+1 284 #define STH LDHU+2 285 #define ST LDHU+3 286 #define STD LDHU+4 287 288 /* Exchange. */ 289 290 #define XMEMBU LDHU+5 291 #define XMEM LDHU+6 292 293 /* Branches. */ 294 295 #define JSR STD+1 296 #define BSR STD+2 297 #define BR STD+3 298 #define JMP STD+4 299 #define BB1 STD+5 300 #define BB0 STD+6 301 #define RTN STD+7 302 #define BCND STD+8 303 304 /* Traps. */ 305 306 #define TB1 BCND+1 307 #define TB0 BCND+2 308 #define TCND BCND+3 309 #define RTE BCND+4 310 #define TBND BCND+5 311 312 /* Misc. */ 313 314 #define MUL TBND + 1 315 #define DIV MUL +2 316 #define DIVU MUL +3 317 #define MASK MUL +4 318 #define FF0 MUL +5 319 #define FF1 MUL +6 320 #define CLR MUL +7 321 #define SET MUL +8 322 #define EXT MUL +9 323 #define EXTU MUL +10 324 #define MAK MUL +11 325 #define ROT MUL +12 326 327 /* Control register manipulations. */ 328 329 #define LDCR ROT +1 330 #define STCR ROT +2 331 #define XCR ROT +3 332 333 #define FLDCR ROT +4 334 #define FSTCR ROT +5 335 #define FXCR ROT +6 336 337 #define NOP XCR +1 338 339 /* Floating point instructions. */ 340 341 #define FADD NOP +1 342 #define FSUB NOP +2 343 #define FMUL NOP +3 344 #define FDIV NOP +4 345 #define FSQRT NOP +5 346 #define FCMP NOP +6 347 #define FIP NOP +7 348 #define FLT NOP +8 349 #define INT NOP +9 350 #define NINT NOP +10 351 #define TRNC NOP +11 352 #define FLDC NOP +12 353 #define FSTC NOP +13 354 #define FXC NOP +14 355 356 #define UEXT(src,off,wid) \ 357 ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1)) 358 359 #define SEXT(src,off,wid) \ 360 (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) ) 361 362 #define MAKE(src,off,wid) \ 363 ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off)) 364 365 #define opword(n) (unsigned long) (memaddr->mem.l) 366 367 /* Constants and masks. */ 368 369 #define SFU0 0x80000000 370 #define SFU1 0x84000000 371 #define SFU7 0x9c000000 372 #define RRI10 0xf0000000 373 #define RRR 0xf4000000 374 #define SFUMASK 0xfc00ffe0 375 #define RRRMASK 0xfc00ffe0 376 #define RRI10MASK 0xfc00fc00 377 #define DEFMASK 0xfc000000 378 #define CTRL 0x0000f000 379 #define CTRLMASK 0xfc00f800 380 381 /* Operands types. */ 382 383 enum operand_type 384 { 385 HEX = 1, 386 REG = 2, 387 CONT = 3, 388 IND = 3, 389 BF = 4, 390 /* Scaled register. */ 391 REGSC = 5, 392 /* Control register. */ 393 CRREG = 6, 394 /* Floating point control register. */ 395 FCRREG = 7, 396 PCREL = 8, 397 CONDMASK = 9, 398 /* Extended register. */ 399 XREG = 10, 400 /* Decimal. */ 401 DEC = 11 402 }; 403 404 /* Hashing specification. */ 405 406 #define HASHVAL 79 407 408 /* Structure templates. */ 409 410 typedef struct 411 { 412 unsigned int offset; 413 unsigned int width; 414 enum operand_type type; 415 } OPSPEC; 416 417 struct SIM_FLAGS 418 { 419 int ltncy, /* latency (max number of clocks needed to execute). */ 420 extime, /* execution time (min number of clocks needed to execute). */ 421 wb_pri; /* writeback slot priority. */ 422 unsigned op:OP, /* simulator version of opcode. */ 423 imm_flags:2, /* 10,16 or 26 bit immediate flags. */ 424 rs1_used:1, /* register source 1 used. */ 425 rs2_used:1, /* register source 2 used. */ 426 rsd_used:1, /* register source/dest used. */ 427 c_flag:1, /* complement. */ 428 u_flag:1, /* upper half word. */ 429 n_flag:1, /* execute next. */ 430 wb_flag:1, /* uses writeback slot. */ 431 dest_64:1, /* double precision dest. */ 432 s1_64:1, /* double precision source 1. */ 433 s2_64:1, /* double precision source 2. */ 434 scale_flag:1; /* register is scaled. */ 435 }; 436 437 typedef struct INSTRUCTAB { 438 unsigned int opcode; 439 char *mnemonic; 440 OPSPEC op1,op2,op3; 441 struct SIM_FLAGS flgs; 442 } INSTAB; 443 444 445 #define NO_OPERAND {0,0,0} 446 447 extern const INSTAB instructions[]; 448 449 /* 450 * Local Variables: 451 * fill-column: 131 452 * End: 453 */ 454