1;; Machine description for DEC Alpha for GNU C compiler 2;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3;; 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 5;; 6;; This file is part of GCC. 7;; 8;; GCC is free software; you can redistribute it and/or modify 9;; it under the terms of the GNU General Public License as published by 10;; the Free Software Foundation; either version 2, or (at your option) 11;; any later version. 12;; 13;; GCC is distributed in the hope that it will be useful, 14;; but WITHOUT ANY WARRANTY; without even the implied warranty of 15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16;; GNU General Public License for more details. 17;; 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING. If not, write to 20;; the Free Software Foundation, 59 Temple Place - Suite 330, 21;; Boston, MA 02111-1307, USA. 22 23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 24 25;; Uses of UNSPEC in this file: 26 27(define_constants 28 [(UNSPEC_ARG_HOME 0) 29 (UNSPEC_CTTZ 1) 30 (UNSPEC_INSXH 2) 31 (UNSPEC_MSKXH 3) 32 (UNSPEC_CVTQL 4) 33 (UNSPEC_CVTLQ 5) 34 (UNSPEC_UMK_LAUM 6) 35 (UNSPEC_UMK_LALM 7) 36 (UNSPEC_UMK_LAL 8) 37 (UNSPEC_UMK_LOAD_CIW 9) 38 (UNSPEC_LDGP2 10) 39 (UNSPEC_LITERAL 11) 40 (UNSPEC_LITUSE 12) 41 (UNSPEC_SIBCALL 13) 42 (UNSPEC_SYMBOL 14) 43 44 ;; TLS Support 45 (UNSPEC_TLSGD_CALL 15) 46 (UNSPEC_TLSLDM_CALL 16) 47 (UNSPEC_TLSGD 17) 48 (UNSPEC_TLSLDM 18) 49 (UNSPEC_DTPREL 19) 50 (UNSPEC_TPREL 20) 51 (UNSPEC_TP 21) 52 53 ;; Builtins 54 (UNSPEC_CMPBGE 22) 55 (UNSPEC_ZAP 23) 56 (UNSPEC_AMASK 24) 57 (UNSPEC_IMPLVER 25) 58 (UNSPEC_PERR 26) 59 (UNSPEC_CTLZ 27) 60 (UNSPEC_CTPOP 28) 61 ]) 62 63;; UNSPEC_VOLATILE: 64 65(define_constants 66 [(UNSPECV_IMB 0) 67 (UNSPECV_BLOCKAGE 1) 68 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver 69 (UNSPECV_LONGJMP 3) ; builtin_longjmp 70 (UNSPECV_TRAPB 4) 71 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop 72 (UNSPECV_REALIGN 6) 73 (UNSPECV_EHR 7) ; exception_receiver 74 (UNSPECV_MCOUNT 8) 75 (UNSPECV_FORCE_MOV 9) 76 (UNSPECV_LDGP1 10) 77 (UNSPECV_PLDGP2 11) ; prologue ldgp 78 (UNSPECV_SET_TP 12) 79 (UNSPECV_RPCC 13) 80 ]) 81 82;; Where necessary, the suffixes _le and _be are used to distinguish between 83;; little-endian and big-endian patterns. 84;; 85;; Note that the Unicos/Mk assembler does not support the following 86;; opcodes: mov, fmov, nop, fnop, unop. 87 88;; Processor type -- this attribute must exactly match the processor_type 89;; enumeration in alpha.h. 90 91(define_attr "cpu" "ev4,ev5,ev6" 92 (const (symbol_ref "alpha_cpu"))) 93 94;; Define an insn type attribute. This is used in function unit delay 95;; computations, among other purposes. For the most part, we use the names 96;; defined in the EV4 documentation, but add a few that we have to know about 97;; separately. 98 99(define_attr "type" 100 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov, 101 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" 102 (const_string "iadd")) 103 104;; Describe a user's asm statement. 105(define_asm_attributes 106 [(set_attr "type" "multi")]) 107 108;; Define the operand size an insn operates on. Used primarily by mul 109;; and div operations that have size dependent timings. 110 111(define_attr "opsize" "si,di,udi" 112 (const_string "di")) 113 114;; The TRAP attribute marks instructions that may generate traps 115;; (which are imprecise and may need a trapb if software completion 116;; is desired). 117 118(define_attr "trap" "no,yes" 119 (const_string "no")) 120 121;; The ROUND_SUFFIX attribute marks which instructions require a 122;; rounding-mode suffix. The value NONE indicates no suffix, 123;; the value NORMAL indicates a suffix controlled by alpha_fprm. 124 125(define_attr "round_suffix" "none,normal,c" 126 (const_string "none")) 127 128;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix: 129;; NONE no suffix 130;; SU accepts only /su (cmpt et al) 131;; SUI accepts only /sui (cvtqt and cvtqs) 132;; V_SV accepts /v and /sv (cvtql only) 133;; V_SV_SVI accepts /v, /sv and /svi (cvttq only) 134;; U_SU_SUI accepts /u, /su and /sui (most fp instructions) 135;; 136;; The actual suffix emitted is controlled by alpha_fptm. 137 138(define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui" 139 (const_string "none")) 140 141;; The length of an instruction sequence in bytes. 142 143(define_attr "length" "" 144 (const_int 4)) 145 146;; The USEGP attribute marks instructions that have relocations that use 147;; the GP. 148 149(define_attr "usegp" "no,yes" 150 (cond [(eq_attr "type" "ldsym,jsr") 151 (const_string "yes") 152 (eq_attr "type" "ild,fld,ist,fst") 153 (symbol_ref "alpha_find_lo_sum_using_gp(insn)") 154 ] 155 (const_string "no"))) 156 157;; The CANNOT_COPY attribute marks instructions with relocations that 158;; cannot easily be duplicated. This includes insns with gpdisp relocs 159;; since they have to stay in 1-1 correspondence with one another. This 160;; also includes jsr insns, since they must stay in correspondence with 161;; the immediately following gpdisp instructions. 162 163(define_attr "cannot_copy" "false,true" 164 (const_string "false")) 165 166;; Include scheduling descriptions. 167 168(include "ev4.md") 169(include "ev5.md") 170(include "ev6.md") 171 172;; First define the arithmetic insns. Note that the 32-bit forms also 173;; sign-extend. 174 175;; Handle 32-64 bit extension from memory to a floating point register 176;; specially, since this occurs frequently in int->double conversions. 177;; 178;; Note that while we must retain the =f case in the insn for reload's 179;; benefit, it should be eliminated after reload, so we should never emit 180;; code for that case. But we don't reject the possibility. 181 182(define_expand "extendsidi2" 183 [(set (match_operand:DI 0 "register_operand" "") 184 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 185 "" 186 "") 187 188(define_insn "*cvtlq" 189 [(set (match_operand:DI 0 "register_operand" "=f") 190 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")] 191 UNSPEC_CVTLQ))] 192 "" 193 "cvtlq %1,%0" 194 [(set_attr "type" "fadd")]) 195 196(define_insn "*extendsidi2_1" 197 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f") 198 (sign_extend:DI 199 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))] 200 "" 201 "@ 202 addl $31,%1,%0 203 ldl %0,%1 204 lds %0,%1\;cvtlq %0,%0" 205 [(set_attr "type" "iadd,ild,fld") 206 (set_attr "length" "*,*,8")]) 207 208(define_split 209 [(set (match_operand:DI 0 "hard_fp_register_operand" "") 210 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))] 211 "reload_completed" 212 [(set (match_dup 2) (match_dup 1)) 213 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))] 214{ 215 operands[1] = adjust_address (operands[1], SFmode, 0); 216 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0])); 217}) 218 219;; Optimize sign-extension of SImode loads. This shows up in the wake of 220;; reload when converting fp->int. 221 222(define_peephole2 223 [(set (match_operand:SI 0 "hard_int_register_operand" "") 224 (match_operand:SI 1 "memory_operand" "")) 225 (set (match_operand:DI 2 "hard_int_register_operand" "") 226 (sign_extend:DI (match_dup 0)))] 227 "true_regnum (operands[0]) == true_regnum (operands[2]) 228 || peep2_reg_dead_p (2, operands[0])" 229 [(set (match_dup 2) 230 (sign_extend:DI (match_dup 1)))] 231 "") 232 233;; Don't say we have addsi3 if optimizing. This generates better code. We 234;; have the anonymous addsi3 pattern below in case combine wants to make it. 235(define_expand "addsi3" 236 [(set (match_operand:SI 0 "register_operand" "") 237 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "") 238 (match_operand:SI 2 "add_operand" "")))] 239 "! optimize" 240 "") 241 242(define_insn "*addsi_internal" 243 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 244 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") 245 (match_operand:SI 2 "add_operand" "rI,O,K,L")))] 246 "" 247 "@ 248 addl %r1,%2,%0 249 subl %r1,%n2,%0 250 lda %0,%2(%r1) 251 ldah %0,%h2(%r1)") 252 253(define_split 254 [(set (match_operand:SI 0 "register_operand" "") 255 (plus:SI (match_operand:SI 1 "register_operand" "") 256 (match_operand:SI 2 "const_int_operand" "")))] 257 "! add_operand (operands[2], SImode)" 258 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 259 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 260{ 261 HOST_WIDE_INT val = INTVAL (operands[2]); 262 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 263 HOST_WIDE_INT rest = val - low; 264 265 operands[3] = GEN_INT (rest); 266 operands[4] = GEN_INT (low); 267}) 268 269(define_insn "*addsi_se" 270 [(set (match_operand:DI 0 "register_operand" "=r,r") 271 (sign_extend:DI 272 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 273 (match_operand:SI 2 "sext_add_operand" "rI,O"))))] 274 "" 275 "@ 276 addl %r1,%2,%0 277 subl %r1,%n2,%0") 278 279(define_insn "*addsi_se2" 280 [(set (match_operand:DI 0 "register_operand" "=r,r") 281 (sign_extend:DI 282 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 283 (match_operand:DI 2 "sext_add_operand" "rI,O")) 284 0)))] 285 "" 286 "@ 287 addl %r1,%2,%0 288 subl %r1,%n2,%0") 289 290(define_split 291 [(set (match_operand:DI 0 "register_operand" "") 292 (sign_extend:DI 293 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "") 294 (match_operand:SI 2 "const_int_operand" "")))) 295 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))] 296 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 297 && INTVAL (operands[2]) % 4 == 0" 298 [(set (match_dup 3) (match_dup 4)) 299 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3) 300 (match_dup 5)) 301 (match_dup 1))))] 302{ 303 HOST_WIDE_INT val = INTVAL (operands[2]) / 4; 304 int mult = 4; 305 306 if (val % 2 == 0) 307 val /= 2, mult = 8; 308 309 operands[4] = GEN_INT (val); 310 operands[5] = GEN_INT (mult); 311}) 312 313(define_split 314 [(set (match_operand:DI 0 "register_operand" "") 315 (sign_extend:DI 316 (plus:SI (match_operator:SI 1 "comparison_operator" 317 [(match_operand 2 "" "") 318 (match_operand 3 "" "")]) 319 (match_operand:SI 4 "add_operand" "")))) 320 (clobber (match_operand:DI 5 "register_operand" ""))] 321 "" 322 [(set (match_dup 5) (match_dup 6)) 323 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))] 324{ 325 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 326 operands[2], operands[3]); 327 operands[7] = gen_lowpart (SImode, operands[5]); 328}) 329 330(define_insn "addvsi3" 331 [(set (match_operand:SI 0 "register_operand" "=r,r") 332 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 333 (match_operand:SI 2 "sext_add_operand" "rI,O"))) 334 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1)) 335 (sign_extend:DI (match_dup 2))) 336 (sign_extend:DI (plus:SI (match_dup 1) 337 (match_dup 2)))) 338 (const_int 0))] 339 "" 340 "@ 341 addlv %r1,%2,%0 342 sublv %r1,%n2,%0") 343 344(define_expand "adddi3" 345 [(set (match_operand:DI 0 "register_operand" "") 346 (plus:DI (match_operand:DI 1 "register_operand" "") 347 (match_operand:DI 2 "add_operand" "")))] 348 "" 349 "") 350 351(define_insn "*adddi_er_lo16_dtp" 352 [(set (match_operand:DI 0 "register_operand" "=r") 353 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 354 (match_operand:DI 2 "dtp16_symbolic_operand" "")))] 355 "HAVE_AS_TLS" 356 "lda %0,%2(%1)\t\t!dtprel") 357 358(define_insn "*adddi_er_hi32_dtp" 359 [(set (match_operand:DI 0 "register_operand" "=r") 360 (plus:DI (match_operand:DI 1 "register_operand" "r") 361 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))] 362 "HAVE_AS_TLS" 363 "ldah %0,%2(%1)\t\t!dtprelhi") 364 365(define_insn "*adddi_er_lo32_dtp" 366 [(set (match_operand:DI 0 "register_operand" "=r") 367 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 368 (match_operand:DI 2 "dtp32_symbolic_operand" "")))] 369 "HAVE_AS_TLS" 370 "lda %0,%2(%1)\t\t!dtprello") 371 372(define_insn "*adddi_er_lo16_tp" 373 [(set (match_operand:DI 0 "register_operand" "=r") 374 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 375 (match_operand:DI 2 "tp16_symbolic_operand" "")))] 376 "HAVE_AS_TLS" 377 "lda %0,%2(%1)\t\t!tprel") 378 379(define_insn "*adddi_er_hi32_tp" 380 [(set (match_operand:DI 0 "register_operand" "=r") 381 (plus:DI (match_operand:DI 1 "register_operand" "r") 382 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))] 383 "HAVE_AS_TLS" 384 "ldah %0,%2(%1)\t\t!tprelhi") 385 386(define_insn "*adddi_er_lo32_tp" 387 [(set (match_operand:DI 0 "register_operand" "=r") 388 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 389 (match_operand:DI 2 "tp32_symbolic_operand" "")))] 390 "HAVE_AS_TLS" 391 "lda %0,%2(%1)\t\t!tprello") 392 393(define_insn "*adddi_er_high_l" 394 [(set (match_operand:DI 0 "register_operand" "=r") 395 (plus:DI (match_operand:DI 1 "register_operand" "r") 396 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))] 397 "TARGET_EXPLICIT_RELOCS && reload_completed" 398 "ldah %0,%2(%1)\t\t!gprelhigh" 399 [(set_attr "usegp" "yes")]) 400 401(define_split 402 [(set (match_operand:DI 0 "register_operand" "") 403 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))] 404 "TARGET_EXPLICIT_RELOCS && reload_completed" 405 [(set (match_dup 0) 406 (plus:DI (match_dup 2) (high:DI (match_dup 1))))] 407 "operands[2] = pic_offset_table_rtx;") 408 409;; We used to expend quite a lot of effort choosing addq/subq/lda. 410;; With complications like 411;; 412;; The NT stack unwind code can't handle a subq to adjust the stack 413;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3, 414;; the exception handling code will loop if a subq is used and an 415;; exception occurs. 416;; 417;; The 19980616 change to emit prologues as RTL also confused some 418;; versions of GDB, which also interprets prologues. This has been 419;; fixed as of GDB 4.18, but it does not harm to unconditionally 420;; use lda here. 421;; 422;; and the fact that the three insns schedule exactly the same, it's 423;; just not worth the effort. 424 425(define_insn "*adddi_internal" 426 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 427 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r") 428 (match_operand:DI 2 "add_operand" "r,K,L")))] 429 "" 430 "@ 431 addq %1,%2,%0 432 lda %0,%2(%1) 433 ldah %0,%h2(%1)") 434 435;; ??? Allow large constants when basing off the frame pointer or some 436;; virtual register that may eliminate to the frame pointer. This is 437;; done because register elimination offsets will change the hi/lo split, 438;; and if we split before reload, we will require additional instructions. 439 440(define_insn "*adddi_fp_hack" 441 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 442 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r") 443 (match_operand:DI 2 "const_int_operand" "K,L,n")))] 444 "NONSTRICT_REG_OK_FP_BASE_P (operands[1]) 445 && INTVAL (operands[2]) >= 0 446 /* This is the largest constant an lda+ldah pair can add, minus 447 an upper bound on the displacement between SP and AP during 448 register elimination. See INITIAL_ELIMINATION_OFFSET. */ 449 && INTVAL (operands[2]) 450 < (0x7fff8000 451 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD 452 - ALPHA_ROUND(current_function_outgoing_args_size) 453 - (ALPHA_ROUND (get_frame_size () 454 + max_reg_num () * UNITS_PER_WORD 455 + current_function_pretend_args_size) 456 - current_function_pretend_args_size))" 457 "@ 458 lda %0,%2(%1) 459 ldah %0,%h2(%1) 460 #") 461 462;; Don't do this if we are adjusting SP since we don't want to do it 463;; in two steps. Don't split FP sources for the reason listed above. 464(define_split 465 [(set (match_operand:DI 0 "register_operand" "") 466 (plus:DI (match_operand:DI 1 "register_operand" "") 467 (match_operand:DI 2 "const_int_operand" "")))] 468 "! add_operand (operands[2], DImode) 469 && operands[0] != stack_pointer_rtx 470 && operands[1] != frame_pointer_rtx 471 && operands[1] != arg_pointer_rtx" 472 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) 473 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] 474{ 475 HOST_WIDE_INT val = INTVAL (operands[2]); 476 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 477 HOST_WIDE_INT rest = val - low; 478 479 operands[4] = GEN_INT (low); 480 if (CONST_OK_FOR_LETTER_P (rest, 'L')) 481 operands[3] = GEN_INT (rest); 482 else if (! no_new_pseudos) 483 { 484 operands[3] = gen_reg_rtx (DImode); 485 emit_move_insn (operands[3], operands[2]); 486 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); 487 DONE; 488 } 489 else 490 FAIL; 491}) 492 493(define_insn "*saddl" 494 [(set (match_operand:SI 0 "register_operand" "=r,r") 495 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") 496 (match_operand:SI 2 "const48_operand" "I,I")) 497 (match_operand:SI 3 "sext_add_operand" "rI,O")))] 498 "" 499 "@ 500 s%2addl %1,%3,%0 501 s%2subl %1,%n3,%0") 502 503(define_insn "*saddl_se" 504 [(set (match_operand:DI 0 "register_operand" "=r,r") 505 (sign_extend:DI 506 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") 507 (match_operand:SI 2 "const48_operand" "I,I")) 508 (match_operand:SI 3 "sext_add_operand" "rI,O"))))] 509 "" 510 "@ 511 s%2addl %1,%3,%0 512 s%2subl %1,%n3,%0") 513 514(define_split 515 [(set (match_operand:DI 0 "register_operand" "") 516 (sign_extend:DI 517 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator" 518 [(match_operand 2 "" "") 519 (match_operand 3 "" "")]) 520 (match_operand:SI 4 "const48_operand" "")) 521 (match_operand:SI 5 "sext_add_operand" "")))) 522 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))] 523 "" 524 [(set (match_dup 6) (match_dup 7)) 525 (set (match_dup 0) 526 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4)) 527 (match_dup 5))))] 528{ 529 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 530 operands[2], operands[3]); 531 operands[8] = gen_lowpart (SImode, operands[6]); 532}) 533 534(define_insn "*saddq" 535 [(set (match_operand:DI 0 "register_operand" "=r,r") 536 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r") 537 (match_operand:DI 2 "const48_operand" "I,I")) 538 (match_operand:DI 3 "sext_add_operand" "rI,O")))] 539 "" 540 "@ 541 s%2addq %1,%3,%0 542 s%2subq %1,%n3,%0") 543 544(define_insn "addvdi3" 545 [(set (match_operand:DI 0 "register_operand" "=r,r") 546 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 547 (match_operand:DI 2 "sext_add_operand" "rI,O"))) 548 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1)) 549 (sign_extend:TI (match_dup 2))) 550 (sign_extend:TI (plus:DI (match_dup 1) 551 (match_dup 2)))) 552 (const_int 0))] 553 "" 554 "@ 555 addqv %r1,%2,%0 556 subqv %r1,%n2,%0") 557 558(define_insn "negsi2" 559 [(set (match_operand:SI 0 "register_operand" "=r") 560 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] 561 "" 562 "subl $31,%1,%0") 563 564(define_insn "*negsi_se" 565 [(set (match_operand:DI 0 "register_operand" "=r") 566 (sign_extend:DI (neg:SI 567 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))] 568 "" 569 "subl $31,%1,%0") 570 571(define_insn "negvsi2" 572 [(set (match_operand:SI 0 "register_operand" "=r") 573 (neg:SI (match_operand:SI 1 "register_operand" "r"))) 574 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1))) 575 (sign_extend:DI (neg:SI (match_dup 1)))) 576 (const_int 0))] 577 "" 578 "sublv $31,%1,%0") 579 580(define_insn "negdi2" 581 [(set (match_operand:DI 0 "register_operand" "=r") 582 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] 583 "" 584 "subq $31,%1,%0") 585 586(define_insn "negvdi2" 587 [(set (match_operand:DI 0 "register_operand" "=r") 588 (neg:DI (match_operand:DI 1 "register_operand" "r"))) 589 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1))) 590 (sign_extend:TI (neg:DI (match_dup 1)))) 591 (const_int 0))] 592 "" 593 "subqv $31,%1,%0") 594 595(define_expand "subsi3" 596 [(set (match_operand:SI 0 "register_operand" "") 597 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "") 598 (match_operand:SI 2 "reg_or_8bit_operand" "")))] 599 "! optimize" 600 "") 601 602(define_insn "*subsi_internal" 603 [(set (match_operand:SI 0 "register_operand" "=r") 604 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 605 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))] 606 "" 607 "subl %r1,%2,%0") 608 609(define_insn "*subsi_se" 610 [(set (match_operand:DI 0 "register_operand" "=r") 611 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 612 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 613 "" 614 "subl %r1,%2,%0") 615 616(define_insn "*subsi_se2" 617 [(set (match_operand:DI 0 "register_operand" "=r") 618 (sign_extend:DI 619 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 620 (match_operand:DI 2 "reg_or_8bit_operand" "rI")) 621 0)))] 622 "" 623 "subl %r1,%2,%0") 624 625(define_insn "subvsi3" 626 [(set (match_operand:SI 0 "register_operand" "=r") 627 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 628 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))) 629 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1)) 630 (sign_extend:DI (match_dup 2))) 631 (sign_extend:DI (minus:SI (match_dup 1) 632 (match_dup 2)))) 633 (const_int 0))] 634 "" 635 "sublv %r1,%2,%0") 636 637(define_insn "subdi3" 638 [(set (match_operand:DI 0 "register_operand" "=r") 639 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 640 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))] 641 "" 642 "subq %r1,%2,%0") 643 644(define_insn "*ssubl" 645 [(set (match_operand:SI 0 "register_operand" "=r") 646 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r") 647 (match_operand:SI 2 "const48_operand" "I")) 648 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))] 649 "" 650 "s%2subl %1,%3,%0") 651 652(define_insn "*ssubl_se" 653 [(set (match_operand:DI 0 "register_operand" "=r") 654 (sign_extend:DI 655 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r") 656 (match_operand:SI 2 "const48_operand" "I")) 657 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] 658 "" 659 "s%2subl %1,%3,%0") 660 661(define_insn "*ssubq" 662 [(set (match_operand:DI 0 "register_operand" "=r") 663 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r") 664 (match_operand:DI 2 "const48_operand" "I")) 665 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))] 666 "" 667 "s%2subq %1,%3,%0") 668 669(define_insn "subvdi3" 670 [(set (match_operand:DI 0 "register_operand" "=r") 671 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 672 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))) 673 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1)) 674 (sign_extend:TI (match_dup 2))) 675 (sign_extend:TI (minus:DI (match_dup 1) 676 (match_dup 2)))) 677 (const_int 0))] 678 "" 679 "subqv %r1,%2,%0") 680 681;; The Unicos/Mk assembler doesn't support mull. 682 683(define_insn "mulsi3" 684 [(set (match_operand:SI 0 "register_operand" "=r") 685 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") 686 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))] 687 "!TARGET_ABI_UNICOSMK" 688 "mull %r1,%2,%0" 689 [(set_attr "type" "imul") 690 (set_attr "opsize" "si")]) 691 692(define_insn "*mulsi_se" 693 [(set (match_operand:DI 0 "register_operand" "=r") 694 (sign_extend:DI 695 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") 696 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 697 "!TARGET_ABI_UNICOSMK" 698 "mull %r1,%2,%0" 699 [(set_attr "type" "imul") 700 (set_attr "opsize" "si")]) 701 702(define_insn "mulvsi3" 703 [(set (match_operand:SI 0 "register_operand" "=r") 704 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") 705 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))) 706 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1)) 707 (sign_extend:DI (match_dup 2))) 708 (sign_extend:DI (mult:SI (match_dup 1) 709 (match_dup 2)))) 710 (const_int 0))] 711 "!TARGET_ABI_UNICOSMK" 712 "mullv %r1,%2,%0" 713 [(set_attr "type" "imul") 714 (set_attr "opsize" "si")]) 715 716(define_insn "muldi3" 717 [(set (match_operand:DI 0 "register_operand" "=r") 718 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") 719 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))] 720 "" 721 "mulq %r1,%2,%0" 722 [(set_attr "type" "imul")]) 723 724(define_insn "mulvdi3" 725 [(set (match_operand:DI 0 "register_operand" "=r") 726 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ") 727 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))) 728 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1)) 729 (sign_extend:TI (match_dup 2))) 730 (sign_extend:TI (mult:DI (match_dup 1) 731 (match_dup 2)))) 732 (const_int 0))] 733 "" 734 "mulqv %r1,%2,%0" 735 [(set_attr "type" "imul")]) 736 737(define_expand "umuldi3_highpart" 738 [(set (match_operand:DI 0 "register_operand" "") 739 (truncate:DI 740 (lshiftrt:TI 741 (mult:TI (zero_extend:TI 742 (match_operand:DI 1 "register_operand" "")) 743 (match_operand:DI 2 "reg_or_8bit_operand" "")) 744 (const_int 64))))] 745 "" 746{ 747 if (REG_P (operands[2])) 748 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]); 749}) 750 751(define_insn "*umuldi3_highpart_reg" 752 [(set (match_operand:DI 0 "register_operand" "=r") 753 (truncate:DI 754 (lshiftrt:TI 755 (mult:TI (zero_extend:TI 756 (match_operand:DI 1 "register_operand" "r")) 757 (zero_extend:TI 758 (match_operand:DI 2 "register_operand" "r"))) 759 (const_int 64))))] 760 "" 761 "umulh %1,%2,%0" 762 [(set_attr "type" "imul") 763 (set_attr "opsize" "udi")]) 764 765(define_insn "*umuldi3_highpart_const" 766 [(set (match_operand:DI 0 "register_operand" "=r") 767 (truncate:DI 768 (lshiftrt:TI 769 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) 770 (match_operand:TI 2 "cint8_operand" "I")) 771 (const_int 64))))] 772 "" 773 "umulh %1,%2,%0" 774 [(set_attr "type" "imul") 775 (set_attr "opsize" "udi")]) 776 777;; The divide and remainder operations take their inputs from r24 and 778;; r25, put their output in r27, and clobber r23 and r28 on all 779;; systems except Unicos/Mk. On Unicos, the standard library provides 780;; subroutines which use the standard calling convention and work on 781;; DImode operands. 782 783;; ??? Force sign-extension here because some versions of OSF/1 and 784;; Interix/NT don't do the right thing if the inputs are not properly 785;; sign-extended. But Linux, for instance, does not have this 786;; problem. Is it worth the complication here to eliminate the sign 787;; extension? 788 789(define_expand "divsi3" 790 [(set (match_dup 3) 791 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))) 792 (set (match_dup 4) 793 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))) 794 (parallel [(set (match_dup 5) 795 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4)))) 796 (clobber (reg:DI 23)) 797 (clobber (reg:DI 28))]) 798 (set (match_operand:SI 0 "nonimmediate_operand" "") 799 (subreg:SI (match_dup 5) 0))] 800 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK" 801{ 802 operands[3] = gen_reg_rtx (DImode); 803 operands[4] = gen_reg_rtx (DImode); 804 operands[5] = gen_reg_rtx (DImode); 805}) 806 807(define_expand "udivsi3" 808 [(set (match_dup 3) 809 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))) 810 (set (match_dup 4) 811 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))) 812 (parallel [(set (match_dup 5) 813 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4)))) 814 (clobber (reg:DI 23)) 815 (clobber (reg:DI 28))]) 816 (set (match_operand:SI 0 "nonimmediate_operand" "") 817 (subreg:SI (match_dup 5) 0))] 818 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK" 819{ 820 operands[3] = gen_reg_rtx (DImode); 821 operands[4] = gen_reg_rtx (DImode); 822 operands[5] = gen_reg_rtx (DImode); 823}) 824 825(define_expand "modsi3" 826 [(set (match_dup 3) 827 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))) 828 (set (match_dup 4) 829 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))) 830 (parallel [(set (match_dup 5) 831 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4)))) 832 (clobber (reg:DI 23)) 833 (clobber (reg:DI 28))]) 834 (set (match_operand:SI 0 "nonimmediate_operand" "") 835 (subreg:SI (match_dup 5) 0))] 836 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK" 837{ 838 operands[3] = gen_reg_rtx (DImode); 839 operands[4] = gen_reg_rtx (DImode); 840 operands[5] = gen_reg_rtx (DImode); 841}) 842 843(define_expand "umodsi3" 844 [(set (match_dup 3) 845 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))) 846 (set (match_dup 4) 847 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))) 848 (parallel [(set (match_dup 5) 849 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4)))) 850 (clobber (reg:DI 23)) 851 (clobber (reg:DI 28))]) 852 (set (match_operand:SI 0 "nonimmediate_operand" "") 853 (subreg:SI (match_dup 5) 0))] 854 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK" 855{ 856 operands[3] = gen_reg_rtx (DImode); 857 operands[4] = gen_reg_rtx (DImode); 858 operands[5] = gen_reg_rtx (DImode); 859}) 860 861(define_expand "divdi3" 862 [(parallel [(set (match_operand:DI 0 "register_operand" "") 863 (div:DI (match_operand:DI 1 "register_operand" "") 864 (match_operand:DI 2 "register_operand" ""))) 865 (clobber (reg:DI 23)) 866 (clobber (reg:DI 28))])] 867 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK" 868 "") 869 870(define_expand "udivdi3" 871 [(parallel [(set (match_operand:DI 0 "register_operand" "") 872 (udiv:DI (match_operand:DI 1 "register_operand" "") 873 (match_operand:DI 2 "register_operand" ""))) 874 (clobber (reg:DI 23)) 875 (clobber (reg:DI 28))])] 876 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK" 877 "") 878 879(define_expand "moddi3" 880 [(use (match_operand:DI 0 "register_operand" "")) 881 (use (match_operand:DI 1 "register_operand" "")) 882 (use (match_operand:DI 2 "register_operand" ""))] 883 "!TARGET_ABI_OPEN_VMS" 884{ 885 if (TARGET_ABI_UNICOSMK) 886 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2])); 887 else 888 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2])); 889 DONE; 890}) 891 892(define_expand "moddi3_dft" 893 [(parallel [(set (match_operand:DI 0 "register_operand" "") 894 (mod:DI (match_operand:DI 1 "register_operand" "") 895 (match_operand:DI 2 "register_operand" ""))) 896 (clobber (reg:DI 23)) 897 (clobber (reg:DI 28))])] 898 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK" 899 "") 900 901;; On Unicos/Mk, we do as the system's C compiler does: 902;; compute the quotient, multiply and subtract. 903 904(define_expand "moddi3_umk" 905 [(use (match_operand:DI 0 "register_operand" "")) 906 (use (match_operand:DI 1 "register_operand" "")) 907 (use (match_operand:DI 2 "register_operand" ""))] 908 "TARGET_ABI_UNICOSMK" 909{ 910 rtx div, mul = gen_reg_rtx (DImode); 911 912 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2], 913 NULL_RTX, 0, OPTAB_LIB); 914 div = force_reg (DImode, div); 915 emit_insn (gen_muldi3 (mul, operands[2], div)); 916 emit_insn (gen_subdi3 (operands[0], operands[1], mul)); 917 DONE; 918}) 919 920(define_expand "umoddi3" 921 [(use (match_operand:DI 0 "register_operand" "")) 922 (use (match_operand:DI 1 "register_operand" "")) 923 (use (match_operand:DI 2 "register_operand" ""))] 924 "! TARGET_ABI_OPEN_VMS" 925{ 926 if (TARGET_ABI_UNICOSMK) 927 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2])); 928 else 929 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2])); 930 DONE; 931}) 932 933(define_expand "umoddi3_dft" 934 [(parallel [(set (match_operand:DI 0 "register_operand" "") 935 (umod:DI (match_operand:DI 1 "register_operand" "") 936 (match_operand:DI 2 "register_operand" ""))) 937 (clobber (reg:DI 23)) 938 (clobber (reg:DI 28))])] 939 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK" 940 "") 941 942(define_expand "umoddi3_umk" 943 [(use (match_operand:DI 0 "register_operand" "")) 944 (use (match_operand:DI 1 "register_operand" "")) 945 (use (match_operand:DI 2 "register_operand" ""))] 946 "TARGET_ABI_UNICOSMK" 947{ 948 rtx div, mul = gen_reg_rtx (DImode); 949 950 div = expand_binop (DImode, udiv_optab, operands[1], operands[2], 951 NULL_RTX, 1, OPTAB_LIB); 952 div = force_reg (DImode, div); 953 emit_insn (gen_muldi3 (mul, operands[2], div)); 954 emit_insn (gen_subdi3 (operands[0], operands[1], mul)); 955 DONE; 956}) 957 958;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as 959;; expanded by the assembler. 960 961(define_insn_and_split "*divmodsi_internal_er" 962 [(set (match_operand:DI 0 "register_operand" "=c") 963 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 964 [(match_operand:DI 1 "register_operand" "a") 965 (match_operand:DI 2 "register_operand" "b")]))) 966 (clobber (reg:DI 23)) 967 (clobber (reg:DI 28))] 968 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS" 969 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#" 970 "&& reload_completed" 971 [(parallel [(set (match_dup 0) 972 (sign_extend:DI (match_dup 3))) 973 (use (match_dup 0)) 974 (use (match_dup 4)) 975 (clobber (reg:DI 23)) 976 (clobber (reg:DI 28))])] 977{ 978 const char *str; 979 switch (GET_CODE (operands[3])) 980 { 981 case DIV: 982 str = "__divl"; 983 break; 984 case UDIV: 985 str = "__divlu"; 986 break; 987 case MOD: 988 str = "__reml"; 989 break; 990 case UMOD: 991 str = "__remlu"; 992 break; 993 default: 994 abort (); 995 } 996 operands[4] = GEN_INT (alpha_next_sequence_number++); 997 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 998 gen_rtx_SYMBOL_REF (DImode, str), 999 operands[4])); 1000} 1001 [(set_attr "type" "jsr") 1002 (set_attr "length" "8")]) 1003 1004(define_insn "*divmodsi_internal_er_1" 1005 [(set (match_operand:DI 0 "register_operand" "=c") 1006 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 1007 [(match_operand:DI 1 "register_operand" "a") 1008 (match_operand:DI 2 "register_operand" "b")]))) 1009 (use (match_operand:DI 4 "register_operand" "c")) 1010 (use (match_operand 5 "const_int_operand" "")) 1011 (clobber (reg:DI 23)) 1012 (clobber (reg:DI 28))] 1013 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS" 1014 "jsr $23,($27),__%E3%J5" 1015 [(set_attr "type" "jsr") 1016 (set_attr "length" "4")]) 1017 1018(define_insn "*divmodsi_internal" 1019 [(set (match_operand:DI 0 "register_operand" "=c") 1020 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 1021 [(match_operand:DI 1 "register_operand" "a") 1022 (match_operand:DI 2 "register_operand" "b")]))) 1023 (clobber (reg:DI 23)) 1024 (clobber (reg:DI 28))] 1025 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK" 1026 "%E3 %1,%2,%0" 1027 [(set_attr "type" "jsr") 1028 (set_attr "length" "8")]) 1029 1030(define_insn_and_split "*divmoddi_internal_er" 1031 [(set (match_operand:DI 0 "register_operand" "=c") 1032 (match_operator:DI 3 "divmod_operator" 1033 [(match_operand:DI 1 "register_operand" "a") 1034 (match_operand:DI 2 "register_operand" "b")])) 1035 (clobber (reg:DI 23)) 1036 (clobber (reg:DI 28))] 1037 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS" 1038 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#" 1039 "&& reload_completed" 1040 [(parallel [(set (match_dup 0) (match_dup 3)) 1041 (use (match_dup 0)) 1042 (use (match_dup 4)) 1043 (clobber (reg:DI 23)) 1044 (clobber (reg:DI 28))])] 1045{ 1046 const char *str; 1047 switch (GET_CODE (operands[3])) 1048 { 1049 case DIV: 1050 str = "__divq"; 1051 break; 1052 case UDIV: 1053 str = "__divqu"; 1054 break; 1055 case MOD: 1056 str = "__remq"; 1057 break; 1058 case UMOD: 1059 str = "__remqu"; 1060 break; 1061 default: 1062 abort (); 1063 } 1064 operands[4] = GEN_INT (alpha_next_sequence_number++); 1065 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 1066 gen_rtx_SYMBOL_REF (DImode, str), 1067 operands[4])); 1068} 1069 [(set_attr "type" "jsr") 1070 (set_attr "length" "8")]) 1071 1072(define_insn "*divmoddi_internal_er_1" 1073 [(set (match_operand:DI 0 "register_operand" "=c") 1074 (match_operator:DI 3 "divmod_operator" 1075 [(match_operand:DI 1 "register_operand" "a") 1076 (match_operand:DI 2 "register_operand" "b")])) 1077 (use (match_operand:DI 4 "register_operand" "c")) 1078 (use (match_operand 5 "const_int_operand" "")) 1079 (clobber (reg:DI 23)) 1080 (clobber (reg:DI 28))] 1081 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS" 1082 "jsr $23,($27),__%E3%J5" 1083 [(set_attr "type" "jsr") 1084 (set_attr "length" "4")]) 1085 1086(define_insn "*divmoddi_internal" 1087 [(set (match_operand:DI 0 "register_operand" "=c") 1088 (match_operator:DI 3 "divmod_operator" 1089 [(match_operand:DI 1 "register_operand" "a") 1090 (match_operand:DI 2 "register_operand" "b")])) 1091 (clobber (reg:DI 23)) 1092 (clobber (reg:DI 28))] 1093 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK" 1094 "%E3 %1,%2,%0" 1095 [(set_attr "type" "jsr") 1096 (set_attr "length" "8")]) 1097 1098;; Next are the basic logical operations. These only exist in DImode. 1099 1100(define_insn "anddi3" 1101 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 1102 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 1103 (match_operand:DI 2 "and_operand" "rI,N,MH")))] 1104 "" 1105 "@ 1106 and %r1,%2,%0 1107 bic %r1,%N2,%0 1108 zapnot %r1,%m2,%0" 1109 [(set_attr "type" "ilog,ilog,shift")]) 1110 1111;; There are times when we can split an AND into two AND insns. This occurs 1112;; when we can first clear any bytes and then clear anything else. For 1113;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07". 1114;; Only do this when running on 64-bit host since the computations are 1115;; too messy otherwise. 1116 1117(define_split 1118 [(set (match_operand:DI 0 "register_operand" "") 1119 (and:DI (match_operand:DI 1 "register_operand" "") 1120 (match_operand:DI 2 "const_int_operand" "")))] 1121 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)" 1122 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3))) 1123 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))] 1124{ 1125 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]); 1126 unsigned HOST_WIDE_INT mask2 = mask1; 1127 int i; 1128 1129 /* For each byte that isn't all zeros, make it all ones. */ 1130 for (i = 0; i < 64; i += 8) 1131 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0) 1132 mask1 |= (HOST_WIDE_INT) 0xff << i; 1133 1134 /* Now turn on any bits we've just turned off. */ 1135 mask2 |= ~ mask1; 1136 1137 operands[3] = GEN_INT (mask1); 1138 operands[4] = GEN_INT (mask2); 1139}) 1140 1141(define_expand "zero_extendqihi2" 1142 [(set (match_operand:HI 0 "register_operand" "") 1143 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] 1144 "" 1145{ 1146 if (! TARGET_BWX) 1147 operands[1] = force_reg (QImode, operands[1]); 1148}) 1149 1150(define_insn "*zero_extendqihi2_bwx" 1151 [(set (match_operand:HI 0 "register_operand" "=r,r") 1152 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] 1153 "TARGET_BWX" 1154 "@ 1155 and %1,0xff,%0 1156 ldbu %0,%1" 1157 [(set_attr "type" "ilog,ild")]) 1158 1159(define_insn "*zero_extendqihi2_nobwx" 1160 [(set (match_operand:HI 0 "register_operand" "=r") 1161 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))] 1162 "! TARGET_BWX" 1163 "and %1,0xff,%0" 1164 [(set_attr "type" "ilog")]) 1165 1166(define_expand "zero_extendqisi2" 1167 [(set (match_operand:SI 0 "register_operand" "") 1168 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] 1169 "" 1170{ 1171 if (! TARGET_BWX) 1172 operands[1] = force_reg (QImode, operands[1]); 1173}) 1174 1175(define_insn "*zero_extendqisi2_bwx" 1176 [(set (match_operand:SI 0 "register_operand" "=r,r") 1177 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] 1178 "TARGET_BWX" 1179 "@ 1180 and %1,0xff,%0 1181 ldbu %0,%1" 1182 [(set_attr "type" "ilog,ild")]) 1183 1184(define_insn "*zero_extendqisi2_nobwx" 1185 [(set (match_operand:SI 0 "register_operand" "=r") 1186 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))] 1187 "! TARGET_BWX" 1188 "and %1,0xff,%0" 1189 [(set_attr "type" "ilog")]) 1190 1191(define_expand "zero_extendqidi2" 1192 [(set (match_operand:DI 0 "register_operand" "") 1193 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))] 1194 "" 1195{ 1196 if (! TARGET_BWX) 1197 operands[1] = force_reg (QImode, operands[1]); 1198}) 1199 1200(define_insn "*zero_extendqidi2_bwx" 1201 [(set (match_operand:DI 0 "register_operand" "=r,r") 1202 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] 1203 "TARGET_BWX" 1204 "@ 1205 and %1,0xff,%0 1206 ldbu %0,%1" 1207 [(set_attr "type" "ilog,ild")]) 1208 1209(define_insn "*zero_extendqidi2_nobwx" 1210 [(set (match_operand:DI 0 "register_operand" "=r") 1211 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))] 1212 "! TARGET_BWX" 1213 "and %1,0xff,%0" 1214 [(set_attr "type" "ilog")]) 1215 1216(define_expand "zero_extendhisi2" 1217 [(set (match_operand:SI 0 "register_operand" "") 1218 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] 1219 "" 1220{ 1221 if (! TARGET_BWX) 1222 operands[1] = force_reg (HImode, operands[1]); 1223}) 1224 1225(define_insn "*zero_extendhisi2_bwx" 1226 [(set (match_operand:SI 0 "register_operand" "=r,r") 1227 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] 1228 "TARGET_BWX" 1229 "@ 1230 zapnot %1,3,%0 1231 ldwu %0,%1" 1232 [(set_attr "type" "shift,ild")]) 1233 1234(define_insn "*zero_extendhisi2_nobwx" 1235 [(set (match_operand:SI 0 "register_operand" "=r") 1236 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))] 1237 "! TARGET_BWX" 1238 "zapnot %1,3,%0" 1239 [(set_attr "type" "shift")]) 1240 1241(define_expand "zero_extendhidi2" 1242 [(set (match_operand:DI 0 "register_operand" "") 1243 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))] 1244 "" 1245{ 1246 if (! TARGET_BWX) 1247 operands[1] = force_reg (HImode, operands[1]); 1248}) 1249 1250(define_insn "*zero_extendhidi2_bwx" 1251 [(set (match_operand:DI 0 "register_operand" "=r,r") 1252 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] 1253 "TARGET_BWX" 1254 "@ 1255 zapnot %1,3,%0 1256 ldwu %0,%1" 1257 [(set_attr "type" "shift,ild")]) 1258 1259(define_insn "*zero_extendhidi2_nobwx" 1260 [(set (match_operand:DI 0 "register_operand" "=r") 1261 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))] 1262 "" 1263 "zapnot %1,3,%0" 1264 [(set_attr "type" "shift")]) 1265 1266(define_insn "zero_extendsidi2" 1267 [(set (match_operand:DI 0 "register_operand" "=r") 1268 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] 1269 "" 1270 "zapnot %1,15,%0" 1271 [(set_attr "type" "shift")]) 1272 1273(define_insn "andnotdi3" 1274 [(set (match_operand:DI 0 "register_operand" "=r") 1275 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")) 1276 (match_operand:DI 2 "reg_or_0_operand" "rJ")))] 1277 "" 1278 "bic %r2,%1,%0" 1279 [(set_attr "type" "ilog")]) 1280 1281(define_insn "iordi3" 1282 [(set (match_operand:DI 0 "register_operand" "=r,r") 1283 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1284 (match_operand:DI 2 "or_operand" "rI,N")))] 1285 "" 1286 "@ 1287 bis %r1,%2,%0 1288 ornot %r1,%N2,%0" 1289 [(set_attr "type" "ilog")]) 1290 1291(define_insn "one_cmpldi2" 1292 [(set (match_operand:DI 0 "register_operand" "=r") 1293 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] 1294 "" 1295 "ornot $31,%1,%0" 1296 [(set_attr "type" "ilog")]) 1297 1298(define_insn "*iornot" 1299 [(set (match_operand:DI 0 "register_operand" "=r") 1300 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")) 1301 (match_operand:DI 2 "reg_or_0_operand" "rJ")))] 1302 "" 1303 "ornot %r2,%1,%0" 1304 [(set_attr "type" "ilog")]) 1305 1306(define_insn "xordi3" 1307 [(set (match_operand:DI 0 "register_operand" "=r,r") 1308 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1309 (match_operand:DI 2 "or_operand" "rI,N")))] 1310 "" 1311 "@ 1312 xor %r1,%2,%0 1313 eqv %r1,%N2,%0" 1314 [(set_attr "type" "ilog")]) 1315 1316(define_insn "*xornot" 1317 [(set (match_operand:DI 0 "register_operand" "=r") 1318 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ") 1319 (match_operand:DI 2 "register_operand" "rI"))))] 1320 "" 1321 "eqv %r1,%2,%0" 1322 [(set_attr "type" "ilog")]) 1323 1324;; Handle FFS and related insns iff we support CIX. 1325 1326(define_expand "ffsdi2" 1327 [(set (match_dup 2) 1328 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ)) 1329 (set (match_dup 3) 1330 (plus:DI (match_dup 2) (const_int 1))) 1331 (set (match_operand:DI 0 "register_operand" "") 1332 (if_then_else:DI (eq (match_dup 1) (const_int 0)) 1333 (const_int 0) (match_dup 3)))] 1334 "TARGET_CIX" 1335{ 1336 operands[2] = gen_reg_rtx (DImode); 1337 operands[3] = gen_reg_rtx (DImode); 1338}) 1339 1340(define_insn "*cttz" 1341 [(set (match_operand:DI 0 "register_operand" "=r") 1342 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))] 1343 "TARGET_CIX" 1344 "cttz %1,%0" 1345 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just 1346 ; reuse the existing type name. 1347 [(set_attr "type" "mvi")]) 1348 1349(define_insn "clzdi2" 1350 [(set (match_operand:DI 0 "register_operand" "=r") 1351 (clz:DI (match_operand:DI 1 "register_operand" "r")))] 1352 "TARGET_CIX" 1353 "ctlz %1,%0" 1354 [(set_attr "type" "mvi")]) 1355 1356(define_insn "ctzdi2" 1357 [(set (match_operand:DI 0 "register_operand" "=r") 1358 (ctz:DI (match_operand:DI 1 "register_operand" "r")))] 1359 "TARGET_CIX" 1360 "cttz %1,%0" 1361 [(set_attr "type" "mvi")]) 1362 1363(define_insn "popcountdi2" 1364 [(set (match_operand:DI 0 "register_operand" "=r") 1365 (popcount:DI (match_operand:DI 1 "register_operand" "r")))] 1366 "TARGET_CIX" 1367 "ctpop %1,%0" 1368 [(set_attr "type" "mvi")]) 1369 1370;; Next come the shifts and the various extract and insert operations. 1371 1372(define_insn "ashldi3" 1373 [(set (match_operand:DI 0 "register_operand" "=r,r") 1374 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") 1375 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))] 1376 "" 1377{ 1378 switch (which_alternative) 1379 { 1380 case 0: 1381 if (operands[2] == const1_rtx) 1382 return "addq %r1,%r1,%0"; 1383 else 1384 return "s%P2addq %r1,0,%0"; 1385 case 1: 1386 return "sll %r1,%2,%0"; 1387 default: 1388 abort(); 1389 } 1390} 1391 [(set_attr "type" "iadd,shift")]) 1392 1393(define_insn "*ashldi_se" 1394 [(set (match_operand:DI 0 "register_operand" "=r") 1395 (sign_extend:DI 1396 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1397 (match_operand:DI 2 "const_int_operand" "P")) 1398 0)))] 1399 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3" 1400{ 1401 if (operands[2] == const1_rtx) 1402 return "addl %r1,%r1,%0"; 1403 else 1404 return "s%P2addl %r1,0,%0"; 1405} 1406 [(set_attr "type" "iadd")]) 1407 1408(define_insn "lshrdi3" 1409 [(set (match_operand:DI 0 "register_operand" "=r") 1410 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1411 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1412 "" 1413 "srl %r1,%2,%0" 1414 [(set_attr "type" "shift")]) 1415 1416(define_insn "ashrdi3" 1417 [(set (match_operand:DI 0 "register_operand" "=r") 1418 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1419 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1420 "" 1421 "sra %r1,%2,%0" 1422 [(set_attr "type" "shift")]) 1423 1424(define_expand "extendqihi2" 1425 [(set (match_dup 2) 1426 (ashift:DI (match_operand:QI 1 "some_operand" "") 1427 (const_int 56))) 1428 (set (match_operand:HI 0 "register_operand" "") 1429 (ashiftrt:DI (match_dup 2) 1430 (const_int 56)))] 1431 "" 1432{ 1433 if (TARGET_BWX) 1434 { 1435 emit_insn (gen_extendqihi2x (operands[0], 1436 force_reg (QImode, operands[1]))); 1437 DONE; 1438 } 1439 1440 /* If we have an unaligned MEM, extend to DImode (which we do 1441 specially) and then copy to the result. */ 1442 if (unaligned_memory_operand (operands[1], HImode)) 1443 { 1444 rtx temp = gen_reg_rtx (DImode); 1445 1446 emit_insn (gen_extendqidi2 (temp, operands[1])); 1447 emit_move_insn (operands[0], gen_lowpart (HImode, temp)); 1448 DONE; 1449 } 1450 1451 operands[0] = gen_lowpart (DImode, operands[0]); 1452 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1])); 1453 operands[2] = gen_reg_rtx (DImode); 1454}) 1455 1456(define_insn "extendqidi2x" 1457 [(set (match_operand:DI 0 "register_operand" "=r") 1458 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))] 1459 "TARGET_BWX" 1460 "sextb %1,%0" 1461 [(set_attr "type" "shift")]) 1462 1463(define_insn "extendhidi2x" 1464 [(set (match_operand:DI 0 "register_operand" "=r") 1465 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))] 1466 "TARGET_BWX" 1467 "sextw %1,%0" 1468 [(set_attr "type" "shift")]) 1469 1470(define_insn "extendqisi2x" 1471 [(set (match_operand:SI 0 "register_operand" "=r") 1472 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))] 1473 "TARGET_BWX" 1474 "sextb %1,%0" 1475 [(set_attr "type" "shift")]) 1476 1477(define_insn "extendhisi2x" 1478 [(set (match_operand:SI 0 "register_operand" "=r") 1479 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))] 1480 "TARGET_BWX" 1481 "sextw %1,%0" 1482 [(set_attr "type" "shift")]) 1483 1484(define_insn "extendqihi2x" 1485 [(set (match_operand:HI 0 "register_operand" "=r") 1486 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))] 1487 "TARGET_BWX" 1488 "sextb %1,%0" 1489 [(set_attr "type" "shift")]) 1490 1491(define_expand "extendqisi2" 1492 [(set (match_dup 2) 1493 (ashift:DI (match_operand:QI 1 "some_operand" "") 1494 (const_int 56))) 1495 (set (match_operand:SI 0 "register_operand" "") 1496 (ashiftrt:DI (match_dup 2) 1497 (const_int 56)))] 1498 "" 1499{ 1500 if (TARGET_BWX) 1501 { 1502 emit_insn (gen_extendqisi2x (operands[0], 1503 force_reg (QImode, operands[1]))); 1504 DONE; 1505 } 1506 1507 /* If we have an unaligned MEM, extend to a DImode form of 1508 the result (which we do specially). */ 1509 if (unaligned_memory_operand (operands[1], QImode)) 1510 { 1511 rtx temp = gen_reg_rtx (DImode); 1512 1513 emit_insn (gen_extendqidi2 (temp, operands[1])); 1514 emit_move_insn (operands[0], gen_lowpart (SImode, temp)); 1515 DONE; 1516 } 1517 1518 operands[0] = gen_lowpart (DImode, operands[0]); 1519 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1])); 1520 operands[2] = gen_reg_rtx (DImode); 1521}) 1522 1523(define_expand "extendqidi2" 1524 [(set (match_dup 2) 1525 (ashift:DI (match_operand:QI 1 "some_operand" "") 1526 (const_int 56))) 1527 (set (match_operand:DI 0 "register_operand" "") 1528 (ashiftrt:DI (match_dup 2) 1529 (const_int 56)))] 1530 "" 1531{ 1532 if (TARGET_BWX) 1533 { 1534 emit_insn (gen_extendqidi2x (operands[0], 1535 force_reg (QImode, operands[1]))); 1536 DONE; 1537 } 1538 1539 if (unaligned_memory_operand (operands[1], QImode)) 1540 { 1541 rtx seq 1542 = gen_unaligned_extendqidi (operands[0], 1543 get_unaligned_address (operands[1], 1)); 1544 1545 alpha_set_memflags (seq, operands[1]); 1546 emit_insn (seq); 1547 DONE; 1548 } 1549 1550 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1])); 1551 operands[2] = gen_reg_rtx (DImode); 1552}) 1553 1554(define_expand "extendhisi2" 1555 [(set (match_dup 2) 1556 (ashift:DI (match_operand:HI 1 "some_operand" "") 1557 (const_int 48))) 1558 (set (match_operand:SI 0 "register_operand" "") 1559 (ashiftrt:DI (match_dup 2) 1560 (const_int 48)))] 1561 "" 1562{ 1563 if (TARGET_BWX) 1564 { 1565 emit_insn (gen_extendhisi2x (operands[0], 1566 force_reg (HImode, operands[1]))); 1567 DONE; 1568 } 1569 1570 /* If we have an unaligned MEM, extend to a DImode form of 1571 the result (which we do specially). */ 1572 if (unaligned_memory_operand (operands[1], HImode)) 1573 { 1574 rtx temp = gen_reg_rtx (DImode); 1575 1576 emit_insn (gen_extendhidi2 (temp, operands[1])); 1577 emit_move_insn (operands[0], gen_lowpart (SImode, temp)); 1578 DONE; 1579 } 1580 1581 operands[0] = gen_lowpart (DImode, operands[0]); 1582 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1])); 1583 operands[2] = gen_reg_rtx (DImode); 1584}) 1585 1586(define_expand "extendhidi2" 1587 [(set (match_dup 2) 1588 (ashift:DI (match_operand:HI 1 "some_operand" "") 1589 (const_int 48))) 1590 (set (match_operand:DI 0 "register_operand" "") 1591 (ashiftrt:DI (match_dup 2) 1592 (const_int 48)))] 1593 "" 1594{ 1595 if (TARGET_BWX) 1596 { 1597 emit_insn (gen_extendhidi2x (operands[0], 1598 force_reg (HImode, operands[1]))); 1599 DONE; 1600 } 1601 1602 if (unaligned_memory_operand (operands[1], HImode)) 1603 { 1604 rtx seq 1605 = gen_unaligned_extendhidi (operands[0], 1606 get_unaligned_address (operands[1], 2)); 1607 1608 alpha_set_memflags (seq, operands[1]); 1609 emit_insn (seq); 1610 DONE; 1611 } 1612 1613 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1])); 1614 operands[2] = gen_reg_rtx (DImode); 1615}) 1616 1617;; Here's how we sign extend an unaligned byte and halfword. Doing this 1618;; as a pattern saves one instruction. The code is similar to that for 1619;; the unaligned loads (see below). 1620;; 1621;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result. 1622(define_expand "unaligned_extendqidi" 1623 [(use (match_operand:QI 0 "register_operand" "")) 1624 (use (match_operand:DI 1 "address_operand" ""))] 1625 "" 1626{ 1627 if (WORDS_BIG_ENDIAN) 1628 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1])); 1629 else 1630 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1])); 1631 DONE; 1632}) 1633 1634(define_expand "unaligned_extendqidi_le" 1635 [(set (match_dup 2) (match_operand:DI 1 "address_operand" "")) 1636 (set (match_dup 3) 1637 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1)) 1638 (const_int -8)))) 1639 (set (match_dup 4) 1640 (ashift:DI (match_dup 3) 1641 (minus:DI (const_int 64) 1642 (ashift:DI 1643 (and:DI (match_dup 2) (const_int 7)) 1644 (const_int 3))))) 1645 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0) 1646 (ashiftrt:DI (match_dup 4) (const_int 56)))] 1647 "! WORDS_BIG_ENDIAN" 1648{ 1649 operands[2] = gen_reg_rtx (DImode); 1650 operands[3] = gen_reg_rtx (DImode); 1651 operands[4] = gen_reg_rtx (DImode); 1652}) 1653 1654(define_expand "unaligned_extendqidi_be" 1655 [(set (match_dup 2) (match_operand:DI 1 "address_operand" "")) 1656 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1))) 1657 (set (match_dup 4) 1658 (mem:DI (and:DI (match_dup 3) 1659 (const_int -8)))) 1660 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2))) 1661 (set (match_dup 6) 1662 (ashift:DI (match_dup 4) 1663 (ashift:DI 1664 (and:DI 1665 (plus:DI (match_dup 5) (const_int 1)) 1666 (const_int 7)) 1667 (const_int 3)))) 1668 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0) 1669 (ashiftrt:DI (match_dup 6) (const_int 56)))] 1670 "WORDS_BIG_ENDIAN" 1671{ 1672 operands[2] = gen_reg_rtx (DImode); 1673 operands[3] = gen_reg_rtx (DImode); 1674 operands[4] = gen_reg_rtx (DImode); 1675 operands[5] = gen_reg_rtx (DImode); 1676 operands[6] = gen_reg_rtx (DImode); 1677}) 1678 1679(define_expand "unaligned_extendhidi" 1680 [(use (match_operand:QI 0 "register_operand" "")) 1681 (use (match_operand:DI 1 "address_operand" ""))] 1682 "" 1683{ 1684 operands[0] = gen_lowpart (DImode, operands[0]); 1685 emit_insn ((WORDS_BIG_ENDIAN 1686 ? gen_unaligned_extendhidi_be 1687 : gen_unaligned_extendhidi_le) (operands[0], operands[1])); 1688 DONE; 1689}) 1690 1691(define_expand "unaligned_extendhidi_le" 1692 [(set (match_dup 2) (match_operand:DI 1 "address_operand" "")) 1693 (set (match_dup 3) 1694 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2)) 1695 (const_int -8)))) 1696 (set (match_dup 4) 1697 (ashift:DI (match_dup 3) 1698 (minus:DI (const_int 64) 1699 (ashift:DI 1700 (and:DI (match_dup 2) (const_int 7)) 1701 (const_int 3))))) 1702 (set (match_operand:DI 0 "register_operand" "") 1703 (ashiftrt:DI (match_dup 4) (const_int 48)))] 1704 "! WORDS_BIG_ENDIAN" 1705{ 1706 operands[2] = gen_reg_rtx (DImode); 1707 operands[3] = gen_reg_rtx (DImode); 1708 operands[4] = gen_reg_rtx (DImode); 1709}) 1710 1711(define_expand "unaligned_extendhidi_be" 1712 [(set (match_dup 2) (match_operand:DI 1 "address_operand" "")) 1713 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2))) 1714 (set (match_dup 4) 1715 (mem:DI (and:DI (match_dup 3) 1716 (const_int -8)))) 1717 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3))) 1718 (set (match_dup 6) 1719 (ashift:DI (match_dup 4) 1720 (ashift:DI 1721 (and:DI 1722 (plus:DI (match_dup 5) (const_int 1)) 1723 (const_int 7)) 1724 (const_int 3)))) 1725 (set (match_operand:DI 0 "register_operand" "") 1726 (ashiftrt:DI (match_dup 6) (const_int 48)))] 1727 "WORDS_BIG_ENDIAN" 1728{ 1729 operands[2] = gen_reg_rtx (DImode); 1730 operands[3] = gen_reg_rtx (DImode); 1731 operands[4] = gen_reg_rtx (DImode); 1732 operands[5] = gen_reg_rtx (DImode); 1733 operands[6] = gen_reg_rtx (DImode); 1734}) 1735 1736(define_insn "*extxl_const" 1737 [(set (match_operand:DI 0 "register_operand" "=r") 1738 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1739 (match_operand:DI 2 "mode_width_operand" "n") 1740 (match_operand:DI 3 "mul8_operand" "I")))] 1741 "" 1742 "ext%M2l %r1,%s3,%0" 1743 [(set_attr "type" "shift")]) 1744 1745(define_insn "extxl_le" 1746 [(set (match_operand:DI 0 "register_operand" "=r") 1747 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1748 (match_operand:DI 2 "mode_width_operand" "n") 1749 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1750 (const_int 3))))] 1751 "! WORDS_BIG_ENDIAN" 1752 "ext%M2l %r1,%3,%0" 1753 [(set_attr "type" "shift")]) 1754 1755(define_insn "extxl_be" 1756 [(set (match_operand:DI 0 "register_operand" "=r") 1757 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1758 (match_operand:DI 2 "mode_width_operand" "n") 1759 (minus:DI 1760 (const_int 56) 1761 (ashift:DI 1762 (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1763 (const_int 3)))))] 1764 "WORDS_BIG_ENDIAN" 1765 "ext%M2l %r1,%3,%0" 1766 [(set_attr "type" "shift")]) 1767 1768;; Combine has some strange notion of preserving existing undefined behavior 1769;; in shifts larger than a word size. So capture these patterns that it 1770;; should have turned into zero_extracts. 1771 1772(define_insn "*extxl_1_le" 1773 [(set (match_operand:DI 0 "register_operand" "=r") 1774 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1775 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1776 (const_int 3))) 1777 (match_operand:DI 3 "mode_mask_operand" "n")))] 1778 "! WORDS_BIG_ENDIAN" 1779 "ext%U3l %1,%2,%0" 1780 [(set_attr "type" "shift")]) 1781 1782(define_insn "*extxl_1_be" 1783 [(set (match_operand:DI 0 "register_operand" "=r") 1784 (and:DI (lshiftrt:DI 1785 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1786 (minus:DI (const_int 56) 1787 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1788 (const_int 3)))) 1789 (match_operand:DI 3 "mode_mask_operand" "n")))] 1790 "WORDS_BIG_ENDIAN" 1791 "ext%U3l %1,%2,%0" 1792 [(set_attr "type" "shift")]) 1793 1794(define_insn "*extql_2_le" 1795 [(set (match_operand:DI 0 "register_operand" "=r") 1796 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1797 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1798 (const_int 3))))] 1799 "! WORDS_BIG_ENDIAN" 1800 "extql %1,%2,%0" 1801 [(set_attr "type" "shift")]) 1802 1803(define_insn "*extql_2_be" 1804 [(set (match_operand:DI 0 "register_operand" "=r") 1805 (lshiftrt:DI 1806 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1807 (minus:DI (const_int 56) 1808 (ashift:DI 1809 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1810 (const_int 3)))))] 1811 "WORDS_BIG_ENDIAN" 1812 "extql %1,%2,%0" 1813 [(set_attr "type" "shift")]) 1814 1815(define_insn "extqh_le" 1816 [(set (match_operand:DI 0 "register_operand" "=r") 1817 (ashift:DI 1818 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1819 (minus:DI (const_int 64) 1820 (ashift:DI 1821 (and:DI 1822 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1823 (const_int 7)) 1824 (const_int 3)))))] 1825 "! WORDS_BIG_ENDIAN" 1826 "extqh %r1,%2,%0" 1827 [(set_attr "type" "shift")]) 1828 1829(define_insn "extqh_be" 1830 [(set (match_operand:DI 0 "register_operand" "=r") 1831 (ashift:DI 1832 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1833 (ashift:DI 1834 (and:DI 1835 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1836 (const_int 1)) 1837 (const_int 7)) 1838 (const_int 3))))] 1839 "WORDS_BIG_ENDIAN" 1840 "extqh %r1,%2,%0" 1841 [(set_attr "type" "shift")]) 1842 1843(define_insn "extlh_le" 1844 [(set (match_operand:DI 0 "register_operand" "=r") 1845 (ashift:DI 1846 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1847 (const_int 2147483647)) 1848 (minus:DI (const_int 64) 1849 (ashift:DI 1850 (and:DI 1851 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1852 (const_int 7)) 1853 (const_int 3)))))] 1854 "! WORDS_BIG_ENDIAN" 1855 "extlh %r1,%2,%0" 1856 [(set_attr "type" "shift")]) 1857 1858(define_insn "extlh_be" 1859 [(set (match_operand:DI 0 "register_operand" "=r") 1860 (and:DI 1861 (ashift:DI 1862 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1863 (ashift:DI 1864 (and:DI 1865 (plus:DI 1866 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1867 (const_int 1)) 1868 (const_int 7)) 1869 (const_int 3))) 1870 (const_int 2147483647)))] 1871 "WORDS_BIG_ENDIAN" 1872 "extlh %r1,%2,%0" 1873 [(set_attr "type" "shift")]) 1874 1875(define_insn "extwh_le" 1876 [(set (match_operand:DI 0 "register_operand" "=r") 1877 (ashift:DI 1878 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1879 (const_int 65535)) 1880 (minus:DI (const_int 64) 1881 (ashift:DI 1882 (and:DI 1883 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1884 (const_int 7)) 1885 (const_int 3)))))] 1886 "! WORDS_BIG_ENDIAN" 1887 "extwh %r1,%2,%0" 1888 [(set_attr "type" "shift")]) 1889 1890(define_insn "extwh_be" 1891 [(set (match_operand:DI 0 "register_operand" "=r") 1892 (and:DI 1893 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1894 (ashift:DI 1895 (and:DI 1896 (plus:DI 1897 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1898 (const_int 1)) 1899 (const_int 7)) 1900 (const_int 3))) 1901 (const_int 65535)))] 1902 "WORDS_BIG_ENDIAN" 1903 "extwh %r1,%2,%0" 1904 [(set_attr "type" "shift")]) 1905 1906;; This converts an extXl into an extXh with an appropriate adjustment 1907;; to the address calculation. 1908 1909;;(define_split 1910;; [(set (match_operand:DI 0 "register_operand" "") 1911;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "") 1912;; (match_operand:DI 2 "mode_width_operand" "") 1913;; (ashift:DI (match_operand:DI 3 "" "") 1914;; (const_int 3))) 1915;; (match_operand:DI 4 "const_int_operand" ""))) 1916;; (clobber (match_operand:DI 5 "register_operand" ""))] 1917;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])" 1918;; [(set (match_dup 5) (match_dup 6)) 1919;; (set (match_dup 0) 1920;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2) 1921;; (ashift:DI (plus:DI (match_dup 5) 1922;; (match_dup 7)) 1923;; (const_int 3))) 1924;; (match_dup 4)))] 1925;; " 1926;;{ 1927;; operands[6] = plus_constant (operands[3], 1928;; INTVAL (operands[2]) / BITS_PER_UNIT); 1929;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT); 1930;;}") 1931 1932(define_insn "*insbl_const" 1933 [(set (match_operand:DI 0 "register_operand" "=r") 1934 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r")) 1935 (match_operand:DI 2 "mul8_operand" "I")))] 1936 "" 1937 "insbl %1,%s2,%0" 1938 [(set_attr "type" "shift")]) 1939 1940(define_insn "*inswl_const" 1941 [(set (match_operand:DI 0 "register_operand" "=r") 1942 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r")) 1943 (match_operand:DI 2 "mul8_operand" "I")))] 1944 "" 1945 "inswl %1,%s2,%0" 1946 [(set_attr "type" "shift")]) 1947 1948(define_insn "*insll_const" 1949 [(set (match_operand:DI 0 "register_operand" "=r") 1950 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) 1951 (match_operand:DI 2 "mul8_operand" "I")))] 1952 "" 1953 "insll %1,%s2,%0" 1954 [(set_attr "type" "shift")]) 1955 1956(define_insn "insbl_le" 1957 [(set (match_operand:DI 0 "register_operand" "=r") 1958 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r")) 1959 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1960 (const_int 3))))] 1961 "! WORDS_BIG_ENDIAN" 1962 "insbl %1,%2,%0" 1963 [(set_attr "type" "shift")]) 1964 1965(define_insn "insbl_be" 1966 [(set (match_operand:DI 0 "register_operand" "=r") 1967 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r")) 1968 (minus:DI (const_int 56) 1969 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1970 (const_int 3)))))] 1971 "WORDS_BIG_ENDIAN" 1972 "insbl %1,%2,%0" 1973 [(set_attr "type" "shift")]) 1974 1975(define_insn "inswl_le" 1976 [(set (match_operand:DI 0 "register_operand" "=r") 1977 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r")) 1978 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1979 (const_int 3))))] 1980 "! WORDS_BIG_ENDIAN" 1981 "inswl %1,%2,%0" 1982 [(set_attr "type" "shift")]) 1983 1984(define_insn "inswl_be" 1985 [(set (match_operand:DI 0 "register_operand" "=r") 1986 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r")) 1987 (minus:DI (const_int 56) 1988 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1989 (const_int 3)))))] 1990 "WORDS_BIG_ENDIAN" 1991 "inswl %1,%2,%0" 1992 [(set_attr "type" "shift")]) 1993 1994(define_insn "insll_le" 1995 [(set (match_operand:DI 0 "register_operand" "=r") 1996 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) 1997 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1998 (const_int 3))))] 1999 "! WORDS_BIG_ENDIAN" 2000 "insll %1,%2,%0" 2001 [(set_attr "type" "shift")]) 2002 2003(define_insn "insll_be" 2004 [(set (match_operand:DI 0 "register_operand" "=r") 2005 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) 2006 (minus:DI (const_int 56) 2007 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 2008 (const_int 3)))))] 2009 "WORDS_BIG_ENDIAN" 2010 "insll %1,%2,%0" 2011 [(set_attr "type" "shift")]) 2012 2013(define_insn "insql_le" 2014 [(set (match_operand:DI 0 "register_operand" "=r") 2015 (ashift:DI (match_operand:DI 1 "register_operand" "r") 2016 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 2017 (const_int 3))))] 2018 "! WORDS_BIG_ENDIAN" 2019 "insql %1,%2,%0" 2020 [(set_attr "type" "shift")]) 2021 2022(define_insn "insql_be" 2023 [(set (match_operand:DI 0 "register_operand" "=r") 2024 (ashift:DI (match_operand:DI 1 "register_operand" "r") 2025 (minus:DI (const_int 56) 2026 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 2027 (const_int 3)))))] 2028 "WORDS_BIG_ENDIAN" 2029 "insql %1,%2,%0" 2030 [(set_attr "type" "shift")]) 2031 2032;; Combine has this sometimes habit of moving the and outside of the 2033;; shift, making life more interesting. 2034 2035(define_insn "*insxl" 2036 [(set (match_operand:DI 0 "register_operand" "=r") 2037 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") 2038 (match_operand:DI 2 "mul8_operand" "I")) 2039 (match_operand:DI 3 "immediate_operand" "i")))] 2040 "HOST_BITS_PER_WIDE_INT == 64 2041 && GET_CODE (operands[3]) == CONST_INT 2042 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 2043 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 2044 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 2045 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 2046 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 2047 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))" 2048{ 2049#if HOST_BITS_PER_WIDE_INT == 64 2050 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 2051 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 2052 return "insbl %1,%s2,%0"; 2053 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 2054 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 2055 return "inswl %1,%s2,%0"; 2056 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 2057 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 2058 return "insll %1,%s2,%0"; 2059#endif 2060 abort(); 2061} 2062 [(set_attr "type" "shift")]) 2063 2064;; We do not include the insXh insns because they are complex to express 2065;; and it does not appear that we would ever want to generate them. 2066;; 2067;; Since we need them for block moves, though, cop out and use unspec. 2068 2069(define_insn "insxh" 2070 [(set (match_operand:DI 0 "register_operand" "=r") 2071 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 2072 (match_operand:DI 2 "mode_width_operand" "n") 2073 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2074 UNSPEC_INSXH))] 2075 "" 2076 "ins%M2h %1,%3,%0" 2077 [(set_attr "type" "shift")]) 2078 2079(define_insn "mskxl_le" 2080 [(set (match_operand:DI 0 "register_operand" "=r") 2081 (and:DI (not:DI (ashift:DI 2082 (match_operand:DI 2 "mode_mask_operand" "n") 2083 (ashift:DI 2084 (match_operand:DI 3 "reg_or_8bit_operand" "rI") 2085 (const_int 3)))) 2086 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 2087 "! WORDS_BIG_ENDIAN" 2088 "msk%U2l %r1,%3,%0" 2089 [(set_attr "type" "shift")]) 2090 2091(define_insn "mskxl_be" 2092 [(set (match_operand:DI 0 "register_operand" "=r") 2093 (and:DI (not:DI (ashift:DI 2094 (match_operand:DI 2 "mode_mask_operand" "n") 2095 (minus:DI (const_int 56) 2096 (ashift:DI 2097 (match_operand:DI 3 "reg_or_8bit_operand" "rI") 2098 (const_int 3))))) 2099 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 2100 "WORDS_BIG_ENDIAN" 2101 "msk%U2l %r1,%3,%0" 2102 [(set_attr "type" "shift")]) 2103 2104;; We do not include the mskXh insns because it does not appear we would 2105;; ever generate one. 2106;; 2107;; Again, we do for block moves and we use unspec again. 2108 2109(define_insn "mskxh" 2110 [(set (match_operand:DI 0 "register_operand" "=r") 2111 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 2112 (match_operand:DI 2 "mode_width_operand" "n") 2113 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2114 UNSPEC_MSKXH))] 2115 "" 2116 "msk%M2h %1,%3,%0" 2117 [(set_attr "type" "shift")]) 2118 2119;; Prefer AND + NE over LSHIFTRT + AND. 2120 2121(define_insn_and_split "*ze_and_ne" 2122 [(set (match_operand:DI 0 "register_operand" "=r") 2123 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2124 (const_int 1) 2125 (match_operand 2 "const_int_operand" "I")))] 2126 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 2127 "#" 2128 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 2129 [(set (match_dup 0) 2130 (and:DI (match_dup 1) (match_dup 3))) 2131 (set (match_dup 0) 2132 (ne:DI (match_dup 0) (const_int 0)))] 2133 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));") 2134 2135;; Floating-point operations. All the double-precision insns can extend 2136;; from single, so indicate that. The exception are the ones that simply 2137;; play with the sign bits; it's not clear what to do there. 2138 2139(define_insn "abssf2" 2140 [(set (match_operand:SF 0 "register_operand" "=f") 2141 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] 2142 "TARGET_FP" 2143 "cpys $f31,%R1,%0" 2144 [(set_attr "type" "fcpys")]) 2145 2146(define_insn "*nabssf2" 2147 [(set (match_operand:SF 0 "register_operand" "=f") 2148 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))] 2149 "TARGET_FP" 2150 "cpysn $f31,%R1,%0" 2151 [(set_attr "type" "fadd")]) 2152 2153(define_insn "absdf2" 2154 [(set (match_operand:DF 0 "register_operand" "=f") 2155 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] 2156 "TARGET_FP" 2157 "cpys $f31,%R1,%0" 2158 [(set_attr "type" "fcpys")]) 2159 2160(define_insn "*nabsdf2" 2161 [(set (match_operand:DF 0 "register_operand" "=f") 2162 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))] 2163 "TARGET_FP" 2164 "cpysn $f31,%R1,%0" 2165 [(set_attr "type" "fadd")]) 2166 2167(define_expand "abstf2" 2168 [(parallel [(set (match_operand:TF 0 "register_operand" "") 2169 (abs:TF (match_operand:TF 1 "reg_or_0_operand" ""))) 2170 (use (match_dup 2))])] 2171 "TARGET_HAS_XFLOATING_LIBS" 2172{ 2173#if HOST_BITS_PER_WIDE_INT >= 64 2174 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63)); 2175#else 2176 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode)); 2177#endif 2178}) 2179 2180(define_insn_and_split "*abstf_internal" 2181 [(set (match_operand:TF 0 "register_operand" "=r") 2182 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 2183 (use (match_operand:DI 2 "register_operand" "r"))] 2184 "TARGET_HAS_XFLOATING_LIBS" 2185 "#" 2186 "&& reload_completed" 2187 [(const_int 0)] 2188 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;") 2189 2190(define_insn "negsf2" 2191 [(set (match_operand:SF 0 "register_operand" "=f") 2192 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] 2193 "TARGET_FP" 2194 "cpysn %R1,%R1,%0" 2195 [(set_attr "type" "fadd")]) 2196 2197(define_insn "negdf2" 2198 [(set (match_operand:DF 0 "register_operand" "=f") 2199 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] 2200 "TARGET_FP" 2201 "cpysn %R1,%R1,%0" 2202 [(set_attr "type" "fadd")]) 2203 2204(define_expand "negtf2" 2205 [(parallel [(set (match_operand:TF 0 "register_operand" "") 2206 (neg:TF (match_operand:TF 1 "reg_or_0_operand" ""))) 2207 (use (match_dup 2))])] 2208 "TARGET_HAS_XFLOATING_LIBS" 2209{ 2210#if HOST_BITS_PER_WIDE_INT >= 64 2211 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63)); 2212#else 2213 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode)); 2214#endif 2215}) 2216 2217(define_insn_and_split "*negtf_internal" 2218 [(set (match_operand:TF 0 "register_operand" "=r") 2219 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 2220 (use (match_operand:DI 2 "register_operand" "r"))] 2221 "TARGET_HAS_XFLOATING_LIBS" 2222 "#" 2223 "&& reload_completed" 2224 [(const_int 0)] 2225 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;") 2226 2227(define_insn "*addsf_ieee" 2228 [(set (match_operand:SF 0 "register_operand" "=&f") 2229 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") 2230 (match_operand:SF 2 "reg_or_0_operand" "fG")))] 2231 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2232 "add%,%/ %R1,%R2,%0" 2233 [(set_attr "type" "fadd") 2234 (set_attr "trap" "yes") 2235 (set_attr "round_suffix" "normal") 2236 (set_attr "trap_suffix" "u_su_sui")]) 2237 2238(define_insn "addsf3" 2239 [(set (match_operand:SF 0 "register_operand" "=f") 2240 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") 2241 (match_operand:SF 2 "reg_or_0_operand" "fG")))] 2242 "TARGET_FP" 2243 "add%,%/ %R1,%R2,%0" 2244 [(set_attr "type" "fadd") 2245 (set_attr "trap" "yes") 2246 (set_attr "round_suffix" "normal") 2247 (set_attr "trap_suffix" "u_su_sui")]) 2248 2249(define_insn "*adddf_ieee" 2250 [(set (match_operand:DF 0 "register_operand" "=&f") 2251 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") 2252 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 2253 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2254 "add%-%/ %R1,%R2,%0" 2255 [(set_attr "type" "fadd") 2256 (set_attr "trap" "yes") 2257 (set_attr "round_suffix" "normal") 2258 (set_attr "trap_suffix" "u_su_sui")]) 2259 2260(define_insn "adddf3" 2261 [(set (match_operand:DF 0 "register_operand" "=f") 2262 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") 2263 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 2264 "TARGET_FP" 2265 "add%-%/ %R1,%R2,%0" 2266 [(set_attr "type" "fadd") 2267 (set_attr "trap" "yes") 2268 (set_attr "round_suffix" "normal") 2269 (set_attr "trap_suffix" "u_su_sui")]) 2270 2271(define_insn "*adddf_ext1" 2272 [(set (match_operand:DF 0 "register_operand" "=f") 2273 (plus:DF (float_extend:DF 2274 (match_operand:SF 1 "reg_or_0_operand" "fG")) 2275 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 2276 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2277 "add%-%/ %R1,%R2,%0" 2278 [(set_attr "type" "fadd") 2279 (set_attr "trap" "yes") 2280 (set_attr "round_suffix" "normal") 2281 (set_attr "trap_suffix" "u_su_sui")]) 2282 2283(define_insn "*adddf_ext2" 2284 [(set (match_operand:DF 0 "register_operand" "=f") 2285 (plus:DF (float_extend:DF 2286 (match_operand:SF 1 "reg_or_0_operand" "%fG")) 2287 (float_extend:DF 2288 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 2289 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2290 "add%-%/ %R1,%R2,%0" 2291 [(set_attr "type" "fadd") 2292 (set_attr "trap" "yes") 2293 (set_attr "round_suffix" "normal") 2294 (set_attr "trap_suffix" "u_su_sui")]) 2295 2296(define_expand "addtf3" 2297 [(use (match_operand 0 "register_operand" "")) 2298 (use (match_operand 1 "general_operand" "")) 2299 (use (match_operand 2 "general_operand" ""))] 2300 "TARGET_HAS_XFLOATING_LIBS" 2301 "alpha_emit_xfloating_arith (PLUS, operands); DONE;") 2302 2303;; Define conversion operators between DFmode and SImode, using the cvtql 2304;; instruction. To allow combine et al to do useful things, we keep the 2305;; operation as a unit until after reload, at which point we split the 2306;; instructions. 2307;; 2308;; Note that we (attempt to) only consider this optimization when the 2309;; ultimate destination is memory. If we will be doing further integer 2310;; processing, it is cheaper to do the truncation in the int regs. 2311 2312(define_insn "*cvtql" 2313 [(set (match_operand:SF 0 "register_operand" "=f") 2314 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")] 2315 UNSPEC_CVTQL))] 2316 "TARGET_FP" 2317 "cvtql%/ %R1,%0" 2318 [(set_attr "type" "fadd") 2319 (set_attr "trap" "yes") 2320 (set_attr "trap_suffix" "v_sv")]) 2321 2322(define_insn_and_split "*fix_truncdfsi_ieee" 2323 [(set (match_operand:SI 0 "memory_operand" "=m") 2324 (subreg:SI 2325 (match_operator:DI 4 "fix_operator" 2326 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 2327 (clobber (match_scratch:DI 2 "=&f")) 2328 (clobber (match_scratch:SF 3 "=&f"))] 2329 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2330 "#" 2331 "&& reload_completed" 2332 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)])) 2333 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2334 (set (match_dup 5) (match_dup 3))] 2335{ 2336 operands[5] = adjust_address (operands[0], SFmode, 0); 2337} 2338 [(set_attr "type" "fadd") 2339 (set_attr "trap" "yes")]) 2340 2341(define_insn_and_split "*fix_truncdfsi_internal" 2342 [(set (match_operand:SI 0 "memory_operand" "=m") 2343 (subreg:SI 2344 (match_operator:DI 3 "fix_operator" 2345 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 2346 (clobber (match_scratch:DI 2 "=f"))] 2347 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2348 "#" 2349 "&& reload_completed" 2350 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)])) 2351 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2352 (set (match_dup 5) (match_dup 4))] 2353{ 2354 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 2355 operands[5] = adjust_address (operands[0], SFmode, 0); 2356} 2357 [(set_attr "type" "fadd") 2358 (set_attr "trap" "yes")]) 2359 2360(define_insn "*fix_truncdfdi_ieee" 2361 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f") 2362 (match_operator:DI 2 "fix_operator" 2363 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))] 2364 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2365 "cvt%-q%/ %R1,%0" 2366 [(set_attr "type" "fadd") 2367 (set_attr "trap" "yes") 2368 (set_attr "round_suffix" "c") 2369 (set_attr "trap_suffix" "v_sv_svi")]) 2370 2371(define_insn "*fix_truncdfdi2" 2372 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f") 2373 (match_operator:DI 2 "fix_operator" 2374 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))] 2375 "TARGET_FP" 2376 "cvt%-q%/ %R1,%0" 2377 [(set_attr "type" "fadd") 2378 (set_attr "trap" "yes") 2379 (set_attr "round_suffix" "c") 2380 (set_attr "trap_suffix" "v_sv_svi")]) 2381 2382(define_expand "fix_truncdfdi2" 2383 [(set (match_operand:DI 0 "reg_no_subreg_operand" "") 2384 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))] 2385 "TARGET_FP" 2386 "") 2387 2388(define_expand "fixuns_truncdfdi2" 2389 [(set (match_operand:DI 0 "reg_no_subreg_operand" "") 2390 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))] 2391 "TARGET_FP" 2392 "") 2393 2394;; Likewise between SFmode and SImode. 2395 2396(define_insn_and_split "*fix_truncsfsi_ieee" 2397 [(set (match_operand:SI 0 "memory_operand" "=m") 2398 (subreg:SI 2399 (match_operator:DI 4 "fix_operator" 2400 [(float_extend:DF 2401 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2402 (clobber (match_scratch:DI 2 "=&f")) 2403 (clobber (match_scratch:SF 3 "=&f"))] 2404 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2405 "#" 2406 "&& reload_completed" 2407 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))])) 2408 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2409 (set (match_dup 5) (match_dup 3))] 2410{ 2411 operands[5] = adjust_address (operands[0], SFmode, 0); 2412} 2413 [(set_attr "type" "fadd") 2414 (set_attr "trap" "yes")]) 2415 2416(define_insn_and_split "*fix_truncsfsi_internal" 2417 [(set (match_operand:SI 0 "memory_operand" "=m") 2418 (subreg:SI 2419 (match_operator:DI 3 "fix_operator" 2420 [(float_extend:DF 2421 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2422 (clobber (match_scratch:DI 2 "=f"))] 2423 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2424 "#" 2425 "&& reload_completed" 2426 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))])) 2427 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2428 (set (match_dup 5) (match_dup 4))] 2429{ 2430 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 2431 operands[5] = adjust_address (operands[0], SFmode, 0); 2432} 2433 [(set_attr "type" "fadd") 2434 (set_attr "trap" "yes")]) 2435 2436(define_insn "*fix_truncsfdi_ieee" 2437 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f") 2438 (match_operator:DI 2 "fix_operator" 2439 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))] 2440 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2441 "cvt%-q%/ %R1,%0" 2442 [(set_attr "type" "fadd") 2443 (set_attr "trap" "yes") 2444 (set_attr "round_suffix" "c") 2445 (set_attr "trap_suffix" "v_sv_svi")]) 2446 2447(define_insn "*fix_truncsfdi2" 2448 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f") 2449 (match_operator:DI 2 "fix_operator" 2450 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))] 2451 "TARGET_FP" 2452 "cvt%-q%/ %R1,%0" 2453 [(set_attr "type" "fadd") 2454 (set_attr "trap" "yes") 2455 (set_attr "round_suffix" "c") 2456 (set_attr "trap_suffix" "v_sv_svi")]) 2457 2458(define_expand "fix_truncsfdi2" 2459 [(set (match_operand:DI 0 "reg_no_subreg_operand" "") 2460 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))] 2461 "TARGET_FP" 2462 "") 2463 2464(define_expand "fixuns_truncsfdi2" 2465 [(set (match_operand:DI 0 "reg_no_subreg_operand" "") 2466 (unsigned_fix:DI 2467 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))] 2468 "TARGET_FP" 2469 "") 2470 2471(define_expand "fix_trunctfdi2" 2472 [(use (match_operand:DI 0 "register_operand" "")) 2473 (use (match_operand:TF 1 "general_operand" ""))] 2474 "TARGET_HAS_XFLOATING_LIBS" 2475 "alpha_emit_xfloating_cvt (FIX, operands); DONE;") 2476 2477(define_expand "fixuns_trunctfdi2" 2478 [(use (match_operand:DI 0 "register_operand" "")) 2479 (use (match_operand:TF 1 "general_operand" ""))] 2480 "TARGET_HAS_XFLOATING_LIBS" 2481 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;") 2482 2483(define_insn "*floatdisf_ieee" 2484 [(set (match_operand:SF 0 "register_operand" "=&f") 2485 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] 2486 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2487 "cvtq%,%/ %1,%0" 2488 [(set_attr "type" "fadd") 2489 (set_attr "trap" "yes") 2490 (set_attr "round_suffix" "normal") 2491 (set_attr "trap_suffix" "sui")]) 2492 2493(define_insn "floatdisf2" 2494 [(set (match_operand:SF 0 "register_operand" "=f") 2495 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] 2496 "TARGET_FP" 2497 "cvtq%,%/ %1,%0" 2498 [(set_attr "type" "fadd") 2499 (set_attr "trap" "yes") 2500 (set_attr "round_suffix" "normal") 2501 (set_attr "trap_suffix" "sui")]) 2502 2503(define_insn_and_split "*floatsisf2_ieee" 2504 [(set (match_operand:SF 0 "register_operand" "=&f") 2505 (float:SF (match_operand:SI 1 "memory_operand" "m"))) 2506 (clobber (match_scratch:DI 2 "=&f")) 2507 (clobber (match_scratch:SF 3 "=&f"))] 2508 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2509 "#" 2510 "&& reload_completed" 2511 [(set (match_dup 3) (match_dup 1)) 2512 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2513 (set (match_dup 0) (float:SF (match_dup 2)))] 2514{ 2515 operands[1] = adjust_address (operands[1], SFmode, 0); 2516}) 2517 2518(define_insn_and_split "*floatsisf2" 2519 [(set (match_operand:SF 0 "register_operand" "=f") 2520 (float:SF (match_operand:SI 1 "memory_operand" "m")))] 2521 "TARGET_FP" 2522 "#" 2523 "&& reload_completed" 2524 [(set (match_dup 0) (match_dup 1)) 2525 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ)) 2526 (set (match_dup 0) (float:SF (match_dup 2)))] 2527{ 2528 operands[1] = adjust_address (operands[1], SFmode, 0); 2529 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2530}) 2531 2532(define_insn "*floatdidf_ieee" 2533 [(set (match_operand:DF 0 "register_operand" "=&f") 2534 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] 2535 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2536 "cvtq%-%/ %1,%0" 2537 [(set_attr "type" "fadd") 2538 (set_attr "trap" "yes") 2539 (set_attr "round_suffix" "normal") 2540 (set_attr "trap_suffix" "sui")]) 2541 2542(define_insn "floatdidf2" 2543 [(set (match_operand:DF 0 "register_operand" "=f") 2544 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] 2545 "TARGET_FP" 2546 "cvtq%-%/ %1,%0" 2547 [(set_attr "type" "fadd") 2548 (set_attr "trap" "yes") 2549 (set_attr "round_suffix" "normal") 2550 (set_attr "trap_suffix" "sui")]) 2551 2552(define_insn_and_split "*floatsidf2_ieee" 2553 [(set (match_operand:DF 0 "register_operand" "=&f") 2554 (float:DF (match_operand:SI 1 "memory_operand" "m"))) 2555 (clobber (match_scratch:DI 2 "=&f")) 2556 (clobber (match_scratch:SF 3 "=&f"))] 2557 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2558 "#" 2559 "&& reload_completed" 2560 [(set (match_dup 3) (match_dup 1)) 2561 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2562 (set (match_dup 0) (float:DF (match_dup 2)))] 2563{ 2564 operands[1] = adjust_address (operands[1], SFmode, 0); 2565}) 2566 2567(define_insn_and_split "*floatsidf2" 2568 [(set (match_operand:DF 0 "register_operand" "=f") 2569 (float:DF (match_operand:SI 1 "memory_operand" "m")))] 2570 "TARGET_FP" 2571 "#" 2572 "&& reload_completed" 2573 [(set (match_dup 3) (match_dup 1)) 2574 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2575 (set (match_dup 0) (float:DF (match_dup 2)))] 2576{ 2577 operands[1] = adjust_address (operands[1], SFmode, 0); 2578 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2579 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0])); 2580}) 2581 2582(define_expand "floatditf2" 2583 [(use (match_operand:TF 0 "register_operand" "")) 2584 (use (match_operand:DI 1 "general_operand" ""))] 2585 "TARGET_HAS_XFLOATING_LIBS" 2586 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;") 2587 2588(define_expand "floatunsdisf2" 2589 [(use (match_operand:SF 0 "register_operand" "")) 2590 (use (match_operand:DI 1 "register_operand" ""))] 2591 "TARGET_FP" 2592 "alpha_emit_floatuns (operands); DONE;") 2593 2594(define_expand "floatunsdidf2" 2595 [(use (match_operand:DF 0 "register_operand" "")) 2596 (use (match_operand:DI 1 "register_operand" ""))] 2597 "TARGET_FP" 2598 "alpha_emit_floatuns (operands); DONE;") 2599 2600(define_expand "floatunsditf2" 2601 [(use (match_operand:TF 0 "register_operand" "")) 2602 (use (match_operand:DI 1 "general_operand" ""))] 2603 "TARGET_HAS_XFLOATING_LIBS" 2604 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;") 2605 2606(define_expand "extendsfdf2" 2607 [(set (match_operand:DF 0 "register_operand" "") 2608 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] 2609 "TARGET_FP" 2610{ 2611 if (alpha_fptm >= ALPHA_FPTM_SU) 2612 operands[1] = force_reg (SFmode, operands[1]); 2613}) 2614 2615;; The Unicos/Mk assembler doesn't support cvtst, but we've already 2616;; asserted that alpha_fptm == ALPHA_FPTM_N. 2617 2618(define_insn "*extendsfdf2_ieee" 2619 [(set (match_operand:DF 0 "register_operand" "=&f") 2620 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] 2621 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2622 "cvtsts %1,%0" 2623 [(set_attr "type" "fadd") 2624 (set_attr "trap" "yes")]) 2625 2626(define_insn "*extendsfdf2_internal" 2627 [(set (match_operand:DF 0 "register_operand" "=f,f,m") 2628 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))] 2629 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2630 "@ 2631 cpys %1,%1,%0 2632 ld%, %0,%1 2633 st%- %1,%0" 2634 [(set_attr "type" "fcpys,fld,fst")]) 2635 2636(define_expand "extendsftf2" 2637 [(use (match_operand:TF 0 "register_operand" "")) 2638 (use (match_operand:SF 1 "general_operand" ""))] 2639 "TARGET_HAS_XFLOATING_LIBS" 2640{ 2641 rtx tmp = gen_reg_rtx (DFmode); 2642 emit_insn (gen_extendsfdf2 (tmp, operands[1])); 2643 emit_insn (gen_extenddftf2 (operands[0], tmp)); 2644 DONE; 2645}) 2646 2647(define_expand "extenddftf2" 2648 [(use (match_operand:TF 0 "register_operand" "")) 2649 (use (match_operand:DF 1 "general_operand" ""))] 2650 "TARGET_HAS_XFLOATING_LIBS" 2651 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;") 2652 2653(define_insn "*truncdfsf2_ieee" 2654 [(set (match_operand:SF 0 "register_operand" "=&f") 2655 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))] 2656 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2657 "cvt%-%,%/ %R1,%0" 2658 [(set_attr "type" "fadd") 2659 (set_attr "trap" "yes") 2660 (set_attr "round_suffix" "normal") 2661 (set_attr "trap_suffix" "u_su_sui")]) 2662 2663(define_insn "truncdfsf2" 2664 [(set (match_operand:SF 0 "register_operand" "=f") 2665 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))] 2666 "TARGET_FP" 2667 "cvt%-%,%/ %R1,%0" 2668 [(set_attr "type" "fadd") 2669 (set_attr "trap" "yes") 2670 (set_attr "round_suffix" "normal") 2671 (set_attr "trap_suffix" "u_su_sui")]) 2672 2673(define_expand "trunctfdf2" 2674 [(use (match_operand:DF 0 "register_operand" "")) 2675 (use (match_operand:TF 1 "general_operand" ""))] 2676 "TARGET_HAS_XFLOATING_LIBS" 2677 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;") 2678 2679(define_expand "trunctfsf2" 2680 [(use (match_operand:SF 0 "register_operand" "")) 2681 (use (match_operand:TF 1 "general_operand" ""))] 2682 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS" 2683{ 2684 rtx tmpf, sticky, arg, lo, hi; 2685 2686 tmpf = gen_reg_rtx (DFmode); 2687 sticky = gen_reg_rtx (DImode); 2688 arg = copy_to_mode_reg (TFmode, operands[1]); 2689 lo = gen_lowpart (DImode, arg); 2690 hi = gen_highpart (DImode, arg); 2691 2692 /* Convert the low word of the TFmode value into a sticky rounding bit, 2693 then or it into the low bit of the high word. This leaves the sticky 2694 bit at bit 48 of the fraction, which is representable in DFmode, 2695 which prevents rounding error in the final conversion to SFmode. */ 2696 2697 emit_insn (gen_rtx_SET (VOIDmode, sticky, 2698 gen_rtx_NE (DImode, lo, const0_rtx))); 2699 emit_insn (gen_iordi3 (hi, hi, sticky)); 2700 emit_insn (gen_trunctfdf2 (tmpf, arg)); 2701 emit_insn (gen_truncdfsf2 (operands[0], tmpf)); 2702 DONE; 2703}) 2704 2705(define_insn "*divsf3_ieee" 2706 [(set (match_operand:SF 0 "register_operand" "=&f") 2707 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG") 2708 (match_operand:SF 2 "reg_or_0_operand" "fG")))] 2709 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2710 "div%,%/ %R1,%R2,%0" 2711 [(set_attr "type" "fdiv") 2712 (set_attr "opsize" "si") 2713 (set_attr "trap" "yes") 2714 (set_attr "round_suffix" "normal") 2715 (set_attr "trap_suffix" "u_su_sui")]) 2716 2717(define_insn "divsf3" 2718 [(set (match_operand:SF 0 "register_operand" "=f") 2719 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG") 2720 (match_operand:SF 2 "reg_or_0_operand" "fG")))] 2721 "TARGET_FP" 2722 "div%,%/ %R1,%R2,%0" 2723 [(set_attr "type" "fdiv") 2724 (set_attr "opsize" "si") 2725 (set_attr "trap" "yes") 2726 (set_attr "round_suffix" "normal") 2727 (set_attr "trap_suffix" "u_su_sui")]) 2728 2729(define_insn "*divdf3_ieee" 2730 [(set (match_operand:DF 0 "register_operand" "=&f") 2731 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 2732 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 2733 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2734 "div%-%/ %R1,%R2,%0" 2735 [(set_attr "type" "fdiv") 2736 (set_attr "trap" "yes") 2737 (set_attr "round_suffix" "normal") 2738 (set_attr "trap_suffix" "u_su_sui")]) 2739 2740(define_insn "divdf3" 2741 [(set (match_operand:DF 0 "register_operand" "=f") 2742 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 2743 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 2744 "TARGET_FP" 2745 "div%-%/ %R1,%R2,%0" 2746 [(set_attr "type" "fdiv") 2747 (set_attr "trap" "yes") 2748 (set_attr "round_suffix" "normal") 2749 (set_attr "trap_suffix" "u_su_sui")]) 2750 2751(define_insn "*divdf_ext1" 2752 [(set (match_operand:DF 0 "register_operand" "=f") 2753 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) 2754 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 2755 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2756 "div%-%/ %R1,%R2,%0" 2757 [(set_attr "type" "fdiv") 2758 (set_attr "trap" "yes") 2759 (set_attr "round_suffix" "normal") 2760 (set_attr "trap_suffix" "u_su_sui")]) 2761 2762(define_insn "*divdf_ext2" 2763 [(set (match_operand:DF 0 "register_operand" "=f") 2764 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 2765 (float_extend:DF 2766 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 2767 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2768 "div%-%/ %R1,%R2,%0" 2769 [(set_attr "type" "fdiv") 2770 (set_attr "trap" "yes") 2771 (set_attr "round_suffix" "normal") 2772 (set_attr "trap_suffix" "u_su_sui")]) 2773 2774(define_insn "*divdf_ext3" 2775 [(set (match_operand:DF 0 "register_operand" "=f") 2776 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) 2777 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 2778 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2779 "div%-%/ %R1,%R2,%0" 2780 [(set_attr "type" "fdiv") 2781 (set_attr "trap" "yes") 2782 (set_attr "round_suffix" "normal") 2783 (set_attr "trap_suffix" "u_su_sui")]) 2784 2785(define_expand "divtf3" 2786 [(use (match_operand 0 "register_operand" "")) 2787 (use (match_operand 1 "general_operand" "")) 2788 (use (match_operand 2 "general_operand" ""))] 2789 "TARGET_HAS_XFLOATING_LIBS" 2790 "alpha_emit_xfloating_arith (DIV, operands); DONE;") 2791 2792(define_insn "*mulsf3_ieee" 2793 [(set (match_operand:SF 0 "register_operand" "=&f") 2794 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") 2795 (match_operand:SF 2 "reg_or_0_operand" "fG")))] 2796 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2797 "mul%,%/ %R1,%R2,%0" 2798 [(set_attr "type" "fmul") 2799 (set_attr "trap" "yes") 2800 (set_attr "round_suffix" "normal") 2801 (set_attr "trap_suffix" "u_su_sui")]) 2802 2803(define_insn "mulsf3" 2804 [(set (match_operand:SF 0 "register_operand" "=f") 2805 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") 2806 (match_operand:SF 2 "reg_or_0_operand" "fG")))] 2807 "TARGET_FP" 2808 "mul%,%/ %R1,%R2,%0" 2809 [(set_attr "type" "fmul") 2810 (set_attr "trap" "yes") 2811 (set_attr "round_suffix" "normal") 2812 (set_attr "trap_suffix" "u_su_sui")]) 2813 2814(define_insn "*muldf3_ieee" 2815 [(set (match_operand:DF 0 "register_operand" "=&f") 2816 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") 2817 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 2818 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2819 "mul%-%/ %R1,%R2,%0" 2820 [(set_attr "type" "fmul") 2821 (set_attr "trap" "yes") 2822 (set_attr "round_suffix" "normal") 2823 (set_attr "trap_suffix" "u_su_sui")]) 2824 2825(define_insn "muldf3" 2826 [(set (match_operand:DF 0 "register_operand" "=f") 2827 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") 2828 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 2829 "TARGET_FP" 2830 "mul%-%/ %R1,%R2,%0" 2831 [(set_attr "type" "fmul") 2832 (set_attr "trap" "yes") 2833 (set_attr "round_suffix" "normal") 2834 (set_attr "trap_suffix" "u_su_sui")]) 2835 2836(define_insn "*muldf_ext1" 2837 [(set (match_operand:DF 0 "register_operand" "=f") 2838 (mult:DF (float_extend:DF 2839 (match_operand:SF 1 "reg_or_0_operand" "fG")) 2840 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 2841 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2842 "mul%-%/ %R1,%R2,%0" 2843 [(set_attr "type" "fmul") 2844 (set_attr "trap" "yes") 2845 (set_attr "round_suffix" "normal") 2846 (set_attr "trap_suffix" "u_su_sui")]) 2847 2848(define_insn "*muldf_ext2" 2849 [(set (match_operand:DF 0 "register_operand" "=f") 2850 (mult:DF (float_extend:DF 2851 (match_operand:SF 1 "reg_or_0_operand" "%fG")) 2852 (float_extend:DF 2853 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 2854 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2855 "mul%-%/ %R1,%R2,%0" 2856 [(set_attr "type" "fmul") 2857 (set_attr "trap" "yes") 2858 (set_attr "round_suffix" "normal") 2859 (set_attr "trap_suffix" "u_su_sui")]) 2860 2861(define_expand "multf3" 2862 [(use (match_operand 0 "register_operand" "")) 2863 (use (match_operand 1 "general_operand" "")) 2864 (use (match_operand 2 "general_operand" ""))] 2865 "TARGET_HAS_XFLOATING_LIBS" 2866 "alpha_emit_xfloating_arith (MULT, operands); DONE;") 2867 2868(define_insn "*subsf3_ieee" 2869 [(set (match_operand:SF 0 "register_operand" "=&f") 2870 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG") 2871 (match_operand:SF 2 "reg_or_0_operand" "fG")))] 2872 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2873 "sub%,%/ %R1,%R2,%0" 2874 [(set_attr "type" "fadd") 2875 (set_attr "trap" "yes") 2876 (set_attr "round_suffix" "normal") 2877 (set_attr "trap_suffix" "u_su_sui")]) 2878 2879(define_insn "subsf3" 2880 [(set (match_operand:SF 0 "register_operand" "=f") 2881 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG") 2882 (match_operand:SF 2 "reg_or_0_operand" "fG")))] 2883 "TARGET_FP" 2884 "sub%,%/ %R1,%R2,%0" 2885 [(set_attr "type" "fadd") 2886 (set_attr "trap" "yes") 2887 (set_attr "round_suffix" "normal") 2888 (set_attr "trap_suffix" "u_su_sui")]) 2889 2890(define_insn "*subdf3_ieee" 2891 [(set (match_operand:DF 0 "register_operand" "=&f") 2892 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 2893 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 2894 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2895 "sub%-%/ %R1,%R2,%0" 2896 [(set_attr "type" "fadd") 2897 (set_attr "trap" "yes") 2898 (set_attr "round_suffix" "normal") 2899 (set_attr "trap_suffix" "u_su_sui")]) 2900 2901(define_insn "subdf3" 2902 [(set (match_operand:DF 0 "register_operand" "=f") 2903 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 2904 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 2905 "TARGET_FP" 2906 "sub%-%/ %R1,%R2,%0" 2907 [(set_attr "type" "fadd") 2908 (set_attr "trap" "yes") 2909 (set_attr "round_suffix" "normal") 2910 (set_attr "trap_suffix" "u_su_sui")]) 2911 2912(define_insn "*subdf_ext1" 2913 [(set (match_operand:DF 0 "register_operand" "=f") 2914 (minus:DF (float_extend:DF 2915 (match_operand:SF 1 "reg_or_0_operand" "fG")) 2916 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 2917 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2918 "sub%-%/ %R1,%R2,%0" 2919 [(set_attr "type" "fadd") 2920 (set_attr "trap" "yes") 2921 (set_attr "round_suffix" "normal") 2922 (set_attr "trap_suffix" "u_su_sui")]) 2923 2924(define_insn "*subdf_ext2" 2925 [(set (match_operand:DF 0 "register_operand" "=f") 2926 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 2927 (float_extend:DF 2928 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 2929 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2930 "sub%-%/ %R1,%R2,%0" 2931 [(set_attr "type" "fadd") 2932 (set_attr "trap" "yes") 2933 (set_attr "round_suffix" "normal") 2934 (set_attr "trap_suffix" "u_su_sui")]) 2935 2936(define_insn "*subdf_ext3" 2937 [(set (match_operand:DF 0 "register_operand" "=f") 2938 (minus:DF (float_extend:DF 2939 (match_operand:SF 1 "reg_or_0_operand" "fG")) 2940 (float_extend:DF 2941 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 2942 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2943 "sub%-%/ %R1,%R2,%0" 2944 [(set_attr "type" "fadd") 2945 (set_attr "trap" "yes") 2946 (set_attr "round_suffix" "normal") 2947 (set_attr "trap_suffix" "u_su_sui")]) 2948 2949(define_expand "subtf3" 2950 [(use (match_operand 0 "register_operand" "")) 2951 (use (match_operand 1 "general_operand" "")) 2952 (use (match_operand 2 "general_operand" ""))] 2953 "TARGET_HAS_XFLOATING_LIBS" 2954 "alpha_emit_xfloating_arith (MINUS, operands); DONE;") 2955 2956(define_insn "*sqrtsf2_ieee" 2957 [(set (match_operand:SF 0 "register_operand" "=&f") 2958 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] 2959 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU" 2960 "sqrt%,%/ %R1,%0" 2961 [(set_attr "type" "fsqrt") 2962 (set_attr "opsize" "si") 2963 (set_attr "trap" "yes") 2964 (set_attr "round_suffix" "normal") 2965 (set_attr "trap_suffix" "u_su_sui")]) 2966 2967(define_insn "sqrtsf2" 2968 [(set (match_operand:SF 0 "register_operand" "=f") 2969 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] 2970 "TARGET_FP && TARGET_FIX" 2971 "sqrt%,%/ %R1,%0" 2972 [(set_attr "type" "fsqrt") 2973 (set_attr "opsize" "si") 2974 (set_attr "trap" "yes") 2975 (set_attr "round_suffix" "normal") 2976 (set_attr "trap_suffix" "u_su_sui")]) 2977 2978(define_insn "*sqrtdf2_ieee" 2979 [(set (match_operand:DF 0 "register_operand" "=&f") 2980 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] 2981 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU" 2982 "sqrt%-%/ %R1,%0" 2983 [(set_attr "type" "fsqrt") 2984 (set_attr "trap" "yes") 2985 (set_attr "round_suffix" "normal") 2986 (set_attr "trap_suffix" "u_su_sui")]) 2987 2988(define_insn "sqrtdf2" 2989 [(set (match_operand:DF 0 "register_operand" "=f") 2990 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] 2991 "TARGET_FP && TARGET_FIX" 2992 "sqrt%-%/ %R1,%0" 2993 [(set_attr "type" "fsqrt") 2994 (set_attr "trap" "yes") 2995 (set_attr "round_suffix" "normal") 2996 (set_attr "trap_suffix" "u_su_sui")]) 2997 2998;; Next are all the integer comparisons, and conditional moves and branches 2999;; and some of the related define_expand's and define_split's. 3000 3001(define_insn "*setcc_internal" 3002 [(set (match_operand 0 "register_operand" "=r") 3003 (match_operator 1 "alpha_comparison_operator" 3004 [(match_operand:DI 2 "register_operand" "r") 3005 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))] 3006 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 3007 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 3008 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 3009 "cmp%C1 %2,%3,%0" 3010 [(set_attr "type" "icmp")]) 3011 3012;; Yes, we can technically support reg_or_8bit_operand in operand 2, 3013;; but that's non-canonical rtl and allowing that causes inefficiencies 3014;; from cse on. 3015(define_insn "*setcc_swapped_internal" 3016 [(set (match_operand 0 "register_operand" "=r") 3017 (match_operator 1 "alpha_swapped_comparison_operator" 3018 [(match_operand:DI 2 "register_operand" "r") 3019 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))] 3020 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 3021 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 3022 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 3023 "cmp%c1 %r3,%2,%0" 3024 [(set_attr "type" "icmp")]) 3025 3026;; Use match_operator rather than ne directly so that we can match 3027;; multiple integer modes. 3028(define_insn "*setne_internal" 3029 [(set (match_operand 0 "register_operand" "=r") 3030 (match_operator 1 "signed_comparison_operator" 3031 [(match_operand:DI 2 "register_operand" "r") 3032 (const_int 0)]))] 3033 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 3034 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 3035 && GET_CODE (operands[1]) == NE 3036 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 3037 "cmpult $31,%2,%0" 3038 [(set_attr "type" "icmp")]) 3039 3040;; The mode folding trick can't be used with const_int operands, since 3041;; reload needs to know the proper mode. 3042;; 3043;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand 3044;; in order to create more pairs of constants. As long as we're allowing 3045;; two constants at the same time, and will have to reload one of them... 3046 3047(define_insn "*movqicc_internal" 3048 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r") 3049 (if_then_else:QI 3050 (match_operator 2 "signed_comparison_operator" 3051 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") 3052 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) 3053 (match_operand:QI 1 "add_operand" "rI,0,rI,0") 3054 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))] 3055 "(operands[3] == const0_rtx || operands[4] == const0_rtx)" 3056 "@ 3057 cmov%C2 %r3,%1,%0 3058 cmov%D2 %r3,%5,%0 3059 cmov%c2 %r4,%1,%0 3060 cmov%d2 %r4,%5,%0" 3061 [(set_attr "type" "icmov")]) 3062 3063(define_insn "*movhicc_internal" 3064 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") 3065 (if_then_else:HI 3066 (match_operator 2 "signed_comparison_operator" 3067 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") 3068 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) 3069 (match_operand:HI 1 "add_operand" "rI,0,rI,0") 3070 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))] 3071 "(operands[3] == const0_rtx || operands[4] == const0_rtx)" 3072 "@ 3073 cmov%C2 %r3,%1,%0 3074 cmov%D2 %r3,%5,%0 3075 cmov%c2 %r4,%1,%0 3076 cmov%d2 %r4,%5,%0" 3077 [(set_attr "type" "icmov")]) 3078 3079(define_insn "*movsicc_internal" 3080 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 3081 (if_then_else:SI 3082 (match_operator 2 "signed_comparison_operator" 3083 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") 3084 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) 3085 (match_operand:SI 1 "add_operand" "rI,0,rI,0") 3086 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))] 3087 "(operands[3] == const0_rtx || operands[4] == const0_rtx)" 3088 "@ 3089 cmov%C2 %r3,%1,%0 3090 cmov%D2 %r3,%5,%0 3091 cmov%c2 %r4,%1,%0 3092 cmov%d2 %r4,%5,%0" 3093 [(set_attr "type" "icmov")]) 3094 3095(define_insn "*movdicc_internal" 3096 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") 3097 (if_then_else:DI 3098 (match_operator 2 "signed_comparison_operator" 3099 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") 3100 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) 3101 (match_operand:DI 1 "add_operand" "rI,0,rI,0") 3102 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))] 3103 "(operands[3] == const0_rtx || operands[4] == const0_rtx)" 3104 "@ 3105 cmov%C2 %r3,%1,%0 3106 cmov%D2 %r3,%5,%0 3107 cmov%c2 %r4,%1,%0 3108 cmov%d2 %r4,%5,%0" 3109 [(set_attr "type" "icmov")]) 3110 3111(define_insn "*movqicc_lbc" 3112 [(set (match_operand:QI 0 "register_operand" "=r,r") 3113 (if_then_else:QI 3114 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 3115 (const_int 1) 3116 (const_int 0)) 3117 (const_int 0)) 3118 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0") 3119 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))] 3120 "" 3121 "@ 3122 cmovlbc %r2,%1,%0 3123 cmovlbs %r2,%3,%0" 3124 [(set_attr "type" "icmov")]) 3125 3126(define_insn "*movhicc_lbc" 3127 [(set (match_operand:HI 0 "register_operand" "=r,r") 3128 (if_then_else:HI 3129 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 3130 (const_int 1) 3131 (const_int 0)) 3132 (const_int 0)) 3133 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0") 3134 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))] 3135 "" 3136 "@ 3137 cmovlbc %r2,%1,%0 3138 cmovlbs %r2,%3,%0" 3139 [(set_attr "type" "icmov")]) 3140 3141(define_insn "*movsicc_lbc" 3142 [(set (match_operand:SI 0 "register_operand" "=r,r") 3143 (if_then_else:SI 3144 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 3145 (const_int 1) 3146 (const_int 0)) 3147 (const_int 0)) 3148 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0") 3149 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))] 3150 "" 3151 "@ 3152 cmovlbc %r2,%1,%0 3153 cmovlbs %r2,%3,%0" 3154 [(set_attr "type" "icmov")]) 3155 3156(define_insn "*movdicc_lbc" 3157 [(set (match_operand:DI 0 "register_operand" "=r,r") 3158 (if_then_else:DI 3159 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 3160 (const_int 1) 3161 (const_int 0)) 3162 (const_int 0)) 3163 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0") 3164 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))] 3165 "" 3166 "@ 3167 cmovlbc %r2,%1,%0 3168 cmovlbs %r2,%3,%0" 3169 [(set_attr "type" "icmov")]) 3170 3171(define_insn "*movqicc_lbs" 3172 [(set (match_operand:QI 0 "register_operand" "=r,r") 3173 (if_then_else:QI 3174 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 3175 (const_int 1) 3176 (const_int 0)) 3177 (const_int 0)) 3178 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0") 3179 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))] 3180 "" 3181 "@ 3182 cmovlbs %r2,%1,%0 3183 cmovlbc %r2,%3,%0" 3184 [(set_attr "type" "icmov")]) 3185 3186(define_insn "*movhicc_lbs" 3187 [(set (match_operand:HI 0 "register_operand" "=r,r") 3188 (if_then_else:HI 3189 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 3190 (const_int 1) 3191 (const_int 0)) 3192 (const_int 0)) 3193 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0") 3194 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))] 3195 "" 3196 "@ 3197 cmovlbs %r2,%1,%0 3198 cmovlbc %r2,%3,%0" 3199 [(set_attr "type" "icmov")]) 3200 3201(define_insn "*movsicc_lbs" 3202 [(set (match_operand:SI 0 "register_operand" "=r,r") 3203 (if_then_else:SI 3204 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 3205 (const_int 1) 3206 (const_int 0)) 3207 (const_int 0)) 3208 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0") 3209 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))] 3210 "" 3211 "@ 3212 cmovlbs %r2,%1,%0 3213 cmovlbc %r2,%3,%0" 3214 [(set_attr "type" "icmov")]) 3215 3216(define_insn "*movdicc_lbs" 3217 [(set (match_operand:DI 0 "register_operand" "=r,r") 3218 (if_then_else:DI 3219 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 3220 (const_int 1) 3221 (const_int 0)) 3222 (const_int 0)) 3223 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0") 3224 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))] 3225 "" 3226 "@ 3227 cmovlbs %r2,%1,%0 3228 cmovlbc %r2,%3,%0" 3229 [(set_attr "type" "icmov")]) 3230 3231;; For ABS, we have two choices, depending on whether the input and output 3232;; registers are the same or not. 3233(define_expand "absdi2" 3234 [(set (match_operand:DI 0 "register_operand" "") 3235 (abs:DI (match_operand:DI 1 "register_operand" "")))] 3236 "" 3237{ 3238 if (rtx_equal_p (operands[0], operands[1])) 3239 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode))); 3240 else 3241 emit_insn (gen_absdi2_diff (operands[0], operands[1])); 3242 DONE; 3243}) 3244 3245(define_expand "absdi2_same" 3246 [(set (match_operand:DI 1 "register_operand" "") 3247 (neg:DI (match_operand:DI 0 "register_operand" ""))) 3248 (set (match_dup 0) 3249 (if_then_else:DI (ge (match_dup 0) (const_int 0)) 3250 (match_dup 0) 3251 (match_dup 1)))] 3252 "" 3253 "") 3254 3255(define_expand "absdi2_diff" 3256 [(set (match_operand:DI 0 "register_operand" "") 3257 (neg:DI (match_operand:DI 1 "register_operand" ""))) 3258 (set (match_dup 0) 3259 (if_then_else:DI (lt (match_dup 1) (const_int 0)) 3260 (match_dup 0) 3261 (match_dup 1)))] 3262 "" 3263 "") 3264 3265(define_split 3266 [(set (match_operand:DI 0 "register_operand" "") 3267 (abs:DI (match_dup 0))) 3268 (clobber (match_operand:DI 1 "register_operand" ""))] 3269 "" 3270 [(set (match_dup 1) (neg:DI (match_dup 0))) 3271 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0)) 3272 (match_dup 0) (match_dup 1)))] 3273 "") 3274 3275(define_split 3276 [(set (match_operand:DI 0 "register_operand" "") 3277 (abs:DI (match_operand:DI 1 "register_operand" "")))] 3278 "! rtx_equal_p (operands[0], operands[1])" 3279 [(set (match_dup 0) (neg:DI (match_dup 1))) 3280 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0)) 3281 (match_dup 0) (match_dup 1)))] 3282 "") 3283 3284(define_split 3285 [(set (match_operand:DI 0 "register_operand" "") 3286 (neg:DI (abs:DI (match_dup 0)))) 3287 (clobber (match_operand:DI 1 "register_operand" ""))] 3288 "" 3289 [(set (match_dup 1) (neg:DI (match_dup 0))) 3290 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0)) 3291 (match_dup 0) (match_dup 1)))] 3292 "") 3293 3294(define_split 3295 [(set (match_operand:DI 0 "register_operand" "") 3296 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))] 3297 "! rtx_equal_p (operands[0], operands[1])" 3298 [(set (match_dup 0) (neg:DI (match_dup 1))) 3299 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0)) 3300 (match_dup 0) (match_dup 1)))] 3301 "") 3302 3303(define_insn "sminqi3" 3304 [(set (match_operand:QI 0 "register_operand" "=r") 3305 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ") 3306 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))] 3307 "TARGET_MAX" 3308 "minsb8 %r1,%2,%0" 3309 [(set_attr "type" "mvi")]) 3310 3311(define_insn "uminqi3" 3312 [(set (match_operand:QI 0 "register_operand" "=r") 3313 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ") 3314 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))] 3315 "TARGET_MAX" 3316 "minub8 %r1,%2,%0" 3317 [(set_attr "type" "mvi")]) 3318 3319(define_insn "smaxqi3" 3320 [(set (match_operand:QI 0 "register_operand" "=r") 3321 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ") 3322 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))] 3323 "TARGET_MAX" 3324 "maxsb8 %r1,%2,%0" 3325 [(set_attr "type" "mvi")]) 3326 3327(define_insn "umaxqi3" 3328 [(set (match_operand:QI 0 "register_operand" "=r") 3329 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ") 3330 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))] 3331 "TARGET_MAX" 3332 "maxub8 %r1,%2,%0" 3333 [(set_attr "type" "mvi")]) 3334 3335(define_insn "sminhi3" 3336 [(set (match_operand:HI 0 "register_operand" "=r") 3337 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ") 3338 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))] 3339 "TARGET_MAX" 3340 "minsw4 %r1,%2,%0" 3341 [(set_attr "type" "mvi")]) 3342 3343(define_insn "uminhi3" 3344 [(set (match_operand:HI 0 "register_operand" "=r") 3345 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ") 3346 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))] 3347 "TARGET_MAX" 3348 "minuw4 %r1,%2,%0" 3349 [(set_attr "type" "mvi")]) 3350 3351(define_insn "smaxhi3" 3352 [(set (match_operand:HI 0 "register_operand" "=r") 3353 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ") 3354 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))] 3355 "TARGET_MAX" 3356 "maxsw4 %r1,%2,%0" 3357 [(set_attr "type" "mvi")]) 3358 3359(define_insn "umaxhi3" 3360 [(set (match_operand:HI 0 "register_operand" "=r") 3361 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ") 3362 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))] 3363 "TARGET_MAX" 3364 "maxuw4 %r1,%2,%0" 3365 [(set_attr "type" "mvi")]) 3366 3367(define_expand "smaxdi3" 3368 [(set (match_dup 3) 3369 (le:DI (match_operand:DI 1 "reg_or_0_operand" "") 3370 (match_operand:DI 2 "reg_or_8bit_operand" ""))) 3371 (set (match_operand:DI 0 "register_operand" "") 3372 (if_then_else:DI (eq (match_dup 3) (const_int 0)) 3373 (match_dup 1) (match_dup 2)))] 3374 "" 3375 { operands[3] = gen_reg_rtx (DImode); }) 3376 3377(define_split 3378 [(set (match_operand:DI 0 "register_operand" "") 3379 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "") 3380 (match_operand:DI 2 "reg_or_8bit_operand" ""))) 3381 (clobber (match_operand:DI 3 "register_operand" ""))] 3382 "operands[2] != const0_rtx" 3383 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2))) 3384 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 3385 (match_dup 1) (match_dup 2)))] 3386 "") 3387 3388(define_insn "*smax_const0" 3389 [(set (match_operand:DI 0 "register_operand" "=r") 3390 (smax:DI (match_operand:DI 1 "register_operand" "0") 3391 (const_int 0)))] 3392 "" 3393 "cmovlt %0,0,%0" 3394 [(set_attr "type" "icmov")]) 3395 3396(define_expand "smindi3" 3397 [(set (match_dup 3) 3398 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "") 3399 (match_operand:DI 2 "reg_or_8bit_operand" ""))) 3400 (set (match_operand:DI 0 "register_operand" "") 3401 (if_then_else:DI (ne (match_dup 3) (const_int 0)) 3402 (match_dup 1) (match_dup 2)))] 3403 "" 3404 { operands[3] = gen_reg_rtx (DImode); }) 3405 3406(define_split 3407 [(set (match_operand:DI 0 "register_operand" "") 3408 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "") 3409 (match_operand:DI 2 "reg_or_8bit_operand" ""))) 3410 (clobber (match_operand:DI 3 "register_operand" ""))] 3411 "operands[2] != const0_rtx" 3412 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2))) 3413 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 3414 (match_dup 1) (match_dup 2)))] 3415 "") 3416 3417(define_insn "*smin_const0" 3418 [(set (match_operand:DI 0 "register_operand" "=r") 3419 (smin:DI (match_operand:DI 1 "register_operand" "0") 3420 (const_int 0)))] 3421 "" 3422 "cmovgt %0,0,%0" 3423 [(set_attr "type" "icmov")]) 3424 3425(define_expand "umaxdi3" 3426 [(set (match_dup 3) 3427 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "") 3428 (match_operand:DI 2 "reg_or_8bit_operand" ""))) 3429 (set (match_operand:DI 0 "register_operand" "") 3430 (if_then_else:DI (eq (match_dup 3) (const_int 0)) 3431 (match_dup 1) (match_dup 2)))] 3432 "" 3433 "operands[3] = gen_reg_rtx (DImode);") 3434 3435(define_split 3436 [(set (match_operand:DI 0 "register_operand" "") 3437 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "") 3438 (match_operand:DI 2 "reg_or_8bit_operand" ""))) 3439 (clobber (match_operand:DI 3 "register_operand" ""))] 3440 "operands[2] != const0_rtx" 3441 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2))) 3442 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 3443 (match_dup 1) (match_dup 2)))] 3444 "") 3445 3446(define_expand "umindi3" 3447 [(set (match_dup 3) 3448 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "") 3449 (match_operand:DI 2 "reg_or_8bit_operand" ""))) 3450 (set (match_operand:DI 0 "register_operand" "") 3451 (if_then_else:DI (ne (match_dup 3) (const_int 0)) 3452 (match_dup 1) (match_dup 2)))] 3453 "" 3454 "operands[3] = gen_reg_rtx (DImode);") 3455 3456(define_split 3457 [(set (match_operand:DI 0 "register_operand" "") 3458 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "") 3459 (match_operand:DI 2 "reg_or_8bit_operand" ""))) 3460 (clobber (match_operand:DI 3 "register_operand" ""))] 3461 "operands[2] != const0_rtx" 3462 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2))) 3463 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 3464 (match_dup 1) (match_dup 2)))] 3465 "") 3466 3467(define_insn "*bcc_normal" 3468 [(set (pc) 3469 (if_then_else 3470 (match_operator 1 "signed_comparison_operator" 3471 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3472 (const_int 0)]) 3473 (label_ref (match_operand 0 "" "")) 3474 (pc)))] 3475 "" 3476 "b%C1 %r2,%0" 3477 [(set_attr "type" "ibr")]) 3478 3479(define_insn "*bcc_reverse" 3480 [(set (pc) 3481 (if_then_else 3482 (match_operator 1 "signed_comparison_operator" 3483 [(match_operand:DI 2 "register_operand" "r") 3484 (const_int 0)]) 3485 3486 (pc) 3487 (label_ref (match_operand 0 "" ""))))] 3488 "" 3489 "b%c1 %2,%0" 3490 [(set_attr "type" "ibr")]) 3491 3492(define_insn "*blbs_normal" 3493 [(set (pc) 3494 (if_then_else 3495 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 3496 (const_int 1) 3497 (const_int 0)) 3498 (const_int 0)) 3499 (label_ref (match_operand 0 "" "")) 3500 (pc)))] 3501 "" 3502 "blbs %r1,%0" 3503 [(set_attr "type" "ibr")]) 3504 3505(define_insn "*blbc_normal" 3506 [(set (pc) 3507 (if_then_else 3508 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 3509 (const_int 1) 3510 (const_int 0)) 3511 (const_int 0)) 3512 (label_ref (match_operand 0 "" "")) 3513 (pc)))] 3514 "" 3515 "blbc %r1,%0" 3516 [(set_attr "type" "ibr")]) 3517 3518(define_split 3519 [(parallel 3520 [(set (pc) 3521 (if_then_else 3522 (match_operator 1 "comparison_operator" 3523 [(zero_extract:DI (match_operand:DI 2 "register_operand" "") 3524 (const_int 1) 3525 (match_operand:DI 3 "const_int_operand" "")) 3526 (const_int 0)]) 3527 (label_ref (match_operand 0 "" "")) 3528 (pc))) 3529 (clobber (match_operand:DI 4 "register_operand" ""))])] 3530 "INTVAL (operands[3]) != 0" 3531 [(set (match_dup 4) 3532 (lshiftrt:DI (match_dup 2) (match_dup 3))) 3533 (set (pc) 3534 (if_then_else (match_op_dup 1 3535 [(zero_extract:DI (match_dup 4) 3536 (const_int 1) 3537 (const_int 0)) 3538 (const_int 0)]) 3539 (label_ref (match_dup 0)) 3540 (pc)))] 3541 "") 3542 3543;; The following are the corresponding floating-point insns. Recall 3544;; we need to have variants that expand the arguments from SFmode 3545;; to DFmode. 3546 3547(define_insn "*cmpdf_ieee" 3548 [(set (match_operand:DF 0 "register_operand" "=&f") 3549 (match_operator:DF 1 "alpha_fp_comparison_operator" 3550 [(match_operand:DF 2 "reg_or_0_operand" "fG") 3551 (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 3552 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 3553 "cmp%-%C1%/ %R2,%R3,%0" 3554 [(set_attr "type" "fadd") 3555 (set_attr "trap" "yes") 3556 (set_attr "trap_suffix" "su")]) 3557 3558(define_insn "*cmpdf_internal" 3559 [(set (match_operand:DF 0 "register_operand" "=f") 3560 (match_operator:DF 1 "alpha_fp_comparison_operator" 3561 [(match_operand:DF 2 "reg_or_0_operand" "fG") 3562 (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 3563 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 3564 "cmp%-%C1%/ %R2,%R3,%0" 3565 [(set_attr "type" "fadd") 3566 (set_attr "trap" "yes") 3567 (set_attr "trap_suffix" "su")]) 3568 3569(define_insn "*cmpdf_ieee_ext1" 3570 [(set (match_operand:DF 0 "register_operand" "=&f") 3571 (match_operator:DF 1 "alpha_fp_comparison_operator" 3572 [(float_extend:DF 3573 (match_operand:SF 2 "reg_or_0_operand" "fG")) 3574 (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 3575 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 3576 "cmp%-%C1%/ %R2,%R3,%0" 3577 [(set_attr "type" "fadd") 3578 (set_attr "trap" "yes") 3579 (set_attr "trap_suffix" "su")]) 3580 3581(define_insn "*cmpdf_ext1" 3582 [(set (match_operand:DF 0 "register_operand" "=f") 3583 (match_operator:DF 1 "alpha_fp_comparison_operator" 3584 [(float_extend:DF 3585 (match_operand:SF 2 "reg_or_0_operand" "fG")) 3586 (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 3587 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 3588 "cmp%-%C1%/ %R2,%R3,%0" 3589 [(set_attr "type" "fadd") 3590 (set_attr "trap" "yes") 3591 (set_attr "trap_suffix" "su")]) 3592 3593(define_insn "*cmpdf_ieee_ext2" 3594 [(set (match_operand:DF 0 "register_operand" "=&f") 3595 (match_operator:DF 1 "alpha_fp_comparison_operator" 3596 [(match_operand:DF 2 "reg_or_0_operand" "fG") 3597 (float_extend:DF 3598 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 3599 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 3600 "cmp%-%C1%/ %R2,%R3,%0" 3601 [(set_attr "type" "fadd") 3602 (set_attr "trap" "yes") 3603 (set_attr "trap_suffix" "su")]) 3604 3605(define_insn "*cmpdf_ext2" 3606 [(set (match_operand:DF 0 "register_operand" "=f") 3607 (match_operator:DF 1 "alpha_fp_comparison_operator" 3608 [(match_operand:DF 2 "reg_or_0_operand" "fG") 3609 (float_extend:DF 3610 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 3611 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 3612 "cmp%-%C1%/ %R2,%R3,%0" 3613 [(set_attr "type" "fadd") 3614 (set_attr "trap" "yes") 3615 (set_attr "trap_suffix" "su")]) 3616 3617(define_insn "*cmpdf_ieee_ext3" 3618 [(set (match_operand:DF 0 "register_operand" "=&f") 3619 (match_operator:DF 1 "alpha_fp_comparison_operator" 3620 [(float_extend:DF 3621 (match_operand:SF 2 "reg_or_0_operand" "fG")) 3622 (float_extend:DF 3623 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 3624 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 3625 "cmp%-%C1%/ %R2,%R3,%0" 3626 [(set_attr "type" "fadd") 3627 (set_attr "trap" "yes") 3628 (set_attr "trap_suffix" "su")]) 3629 3630(define_insn "*cmpdf_ext3" 3631 [(set (match_operand:DF 0 "register_operand" "=f") 3632 (match_operator:DF 1 "alpha_fp_comparison_operator" 3633 [(float_extend:DF 3634 (match_operand:SF 2 "reg_or_0_operand" "fG")) 3635 (float_extend:DF 3636 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 3637 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 3638 "cmp%-%C1%/ %R2,%R3,%0" 3639 [(set_attr "type" "fadd") 3640 (set_attr "trap" "yes") 3641 (set_attr "trap_suffix" "su")]) 3642 3643(define_insn "*movdfcc_internal" 3644 [(set (match_operand:DF 0 "register_operand" "=f,f") 3645 (if_then_else:DF 3646 (match_operator 3 "signed_comparison_operator" 3647 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 3648 (match_operand:DF 2 "const0_operand" "G,G")]) 3649 (match_operand:DF 1 "reg_or_0_operand" "fG,0") 3650 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 3651 "TARGET_FP" 3652 "@ 3653 fcmov%C3 %R4,%R1,%0 3654 fcmov%D3 %R4,%R5,%0" 3655 [(set_attr "type" "fcmov")]) 3656 3657(define_insn "*movsfcc_internal" 3658 [(set (match_operand:SF 0 "register_operand" "=f,f") 3659 (if_then_else:SF 3660 (match_operator 3 "signed_comparison_operator" 3661 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 3662 (match_operand:DF 2 "const0_operand" "G,G")]) 3663 (match_operand:SF 1 "reg_or_0_operand" "fG,0") 3664 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] 3665 "TARGET_FP" 3666 "@ 3667 fcmov%C3 %R4,%R1,%0 3668 fcmov%D3 %R4,%R5,%0" 3669 [(set_attr "type" "fcmov")]) 3670 3671(define_insn "*movdfcc_ext1" 3672 [(set (match_operand:DF 0 "register_operand" "=f,f") 3673 (if_then_else:DF 3674 (match_operator 3 "signed_comparison_operator" 3675 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 3676 (match_operand:DF 2 "const0_operand" "G,G")]) 3677 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 3678 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 3679 "TARGET_FP" 3680 "@ 3681 fcmov%C3 %R4,%R1,%0 3682 fcmov%D3 %R4,%R5,%0" 3683 [(set_attr "type" "fcmov")]) 3684 3685(define_insn "*movdfcc_ext2" 3686 [(set (match_operand:DF 0 "register_operand" "=f,f") 3687 (if_then_else:DF 3688 (match_operator 3 "signed_comparison_operator" 3689 [(float_extend:DF 3690 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 3691 (match_operand:DF 2 "const0_operand" "G,G")]) 3692 (match_operand:DF 1 "reg_or_0_operand" "fG,0") 3693 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 3694 "TARGET_FP" 3695 "@ 3696 fcmov%C3 %R4,%R1,%0 3697 fcmov%D3 %R4,%R5,%0" 3698 [(set_attr "type" "fcmov")]) 3699 3700(define_insn "*movdfcc_ext3" 3701 [(set (match_operand:SF 0 "register_operand" "=f,f") 3702 (if_then_else:SF 3703 (match_operator 3 "signed_comparison_operator" 3704 [(float_extend:DF 3705 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 3706 (match_operand:DF 2 "const0_operand" "G,G")]) 3707 (match_operand:SF 1 "reg_or_0_operand" "fG,0") 3708 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] 3709 "TARGET_FP" 3710 "@ 3711 fcmov%C3 %R4,%R1,%0 3712 fcmov%D3 %R4,%R5,%0" 3713 [(set_attr "type" "fcmov")]) 3714 3715(define_insn "*movdfcc_ext4" 3716 [(set (match_operand:DF 0 "register_operand" "=f,f") 3717 (if_then_else:DF 3718 (match_operator 3 "signed_comparison_operator" 3719 [(float_extend:DF 3720 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 3721 (match_operand:DF 2 "const0_operand" "G,G")]) 3722 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 3723 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 3724 "TARGET_FP" 3725 "@ 3726 fcmov%C3 %R4,%R1,%0 3727 fcmov%D3 %R4,%R5,%0" 3728 [(set_attr "type" "fcmov")]) 3729 3730(define_expand "maxdf3" 3731 [(set (match_dup 3) 3732 (le:DF (match_operand:DF 1 "reg_or_0_operand" "") 3733 (match_operand:DF 2 "reg_or_0_operand" ""))) 3734 (set (match_operand:DF 0 "register_operand" "") 3735 (if_then_else:DF (eq (match_dup 3) (match_dup 4)) 3736 (match_dup 1) (match_dup 2)))] 3737 "TARGET_FP" 3738{ 3739 operands[3] = gen_reg_rtx (DFmode); 3740 operands[4] = CONST0_RTX (DFmode); 3741}) 3742 3743(define_expand "mindf3" 3744 [(set (match_dup 3) 3745 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "") 3746 (match_operand:DF 2 "reg_or_0_operand" ""))) 3747 (set (match_operand:DF 0 "register_operand" "") 3748 (if_then_else:DF (ne (match_dup 3) (match_dup 4)) 3749 (match_dup 1) (match_dup 2)))] 3750 "TARGET_FP" 3751{ 3752 operands[3] = gen_reg_rtx (DFmode); 3753 operands[4] = CONST0_RTX (DFmode); 3754}) 3755 3756(define_expand "maxsf3" 3757 [(set (match_dup 3) 3758 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "")) 3759 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "")))) 3760 (set (match_operand:SF 0 "register_operand" "") 3761 (if_then_else:SF (eq (match_dup 3) (match_dup 4)) 3762 (match_dup 1) (match_dup 2)))] 3763 "TARGET_FP" 3764{ 3765 operands[3] = gen_reg_rtx (DFmode); 3766 operands[4] = CONST0_RTX (DFmode); 3767}) 3768 3769(define_expand "minsf3" 3770 [(set (match_dup 3) 3771 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "")) 3772 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "")))) 3773 (set (match_operand:SF 0 "register_operand" "") 3774 (if_then_else:SF (ne (match_dup 3) (match_dup 4)) 3775 (match_dup 1) (match_dup 2)))] 3776 "TARGET_FP" 3777{ 3778 operands[3] = gen_reg_rtx (DFmode); 3779 operands[4] = CONST0_RTX (DFmode); 3780}) 3781 3782(define_insn "*fbcc_normal" 3783 [(set (pc) 3784 (if_then_else 3785 (match_operator 1 "signed_comparison_operator" 3786 [(match_operand:DF 2 "reg_or_0_operand" "fG") 3787 (match_operand:DF 3 "const0_operand" "G")]) 3788 (label_ref (match_operand 0 "" "")) 3789 (pc)))] 3790 "TARGET_FP" 3791 "fb%C1 %R2,%0" 3792 [(set_attr "type" "fbr")]) 3793 3794(define_insn "*fbcc_ext_normal" 3795 [(set (pc) 3796 (if_then_else 3797 (match_operator 1 "signed_comparison_operator" 3798 [(float_extend:DF 3799 (match_operand:SF 2 "reg_or_0_operand" "fG")) 3800 (match_operand:DF 3 "const0_operand" "G")]) 3801 (label_ref (match_operand 0 "" "")) 3802 (pc)))] 3803 "TARGET_FP" 3804 "fb%C1 %R2,%0" 3805 [(set_attr "type" "fbr")]) 3806 3807;; These are the main define_expand's used to make conditional branches 3808;; and compares. 3809 3810(define_expand "cmpdf" 3811 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "") 3812 (match_operand:DF 1 "reg_or_0_operand" "")))] 3813 "TARGET_FP" 3814{ 3815 alpha_compare.op0 = operands[0]; 3816 alpha_compare.op1 = operands[1]; 3817 alpha_compare.fp_p = 1; 3818 DONE; 3819}) 3820 3821(define_expand "cmptf" 3822 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "") 3823 (match_operand:TF 1 "general_operand" "")))] 3824 "TARGET_HAS_XFLOATING_LIBS" 3825{ 3826 alpha_compare.op0 = operands[0]; 3827 alpha_compare.op1 = operands[1]; 3828 alpha_compare.fp_p = 1; 3829 DONE; 3830}) 3831 3832(define_expand "cmpdi" 3833 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "") 3834 (match_operand:DI 1 "general_operand" "")))] 3835 "" 3836{ 3837 alpha_compare.op0 = operands[0]; 3838 alpha_compare.op1 = operands[1]; 3839 alpha_compare.fp_p = 0; 3840 DONE; 3841}) 3842 3843(define_expand "beq" 3844 [(set (pc) 3845 (if_then_else (match_dup 1) 3846 (label_ref (match_operand 0 "" "")) 3847 (pc)))] 3848 "" 3849 "{ operands[1] = alpha_emit_conditional_branch (EQ); }") 3850 3851(define_expand "bne" 3852 [(set (pc) 3853 (if_then_else (match_dup 1) 3854 (label_ref (match_operand 0 "" "")) 3855 (pc)))] 3856 "" 3857 "{ operands[1] = alpha_emit_conditional_branch (NE); }") 3858 3859(define_expand "blt" 3860 [(set (pc) 3861 (if_then_else (match_dup 1) 3862 (label_ref (match_operand 0 "" "")) 3863 (pc)))] 3864 "" 3865 "{ operands[1] = alpha_emit_conditional_branch (LT); }") 3866 3867(define_expand "ble" 3868 [(set (pc) 3869 (if_then_else (match_dup 1) 3870 (label_ref (match_operand 0 "" "")) 3871 (pc)))] 3872 "" 3873 "{ operands[1] = alpha_emit_conditional_branch (LE); }") 3874 3875(define_expand "bgt" 3876 [(set (pc) 3877 (if_then_else (match_dup 1) 3878 (label_ref (match_operand 0 "" "")) 3879 (pc)))] 3880 "" 3881 "{ operands[1] = alpha_emit_conditional_branch (GT); }") 3882 3883(define_expand "bge" 3884 [(set (pc) 3885 (if_then_else (match_dup 1) 3886 (label_ref (match_operand 0 "" "")) 3887 (pc)))] 3888 "" 3889 "{ operands[1] = alpha_emit_conditional_branch (GE); }") 3890 3891(define_expand "bltu" 3892 [(set (pc) 3893 (if_then_else (match_dup 1) 3894 (label_ref (match_operand 0 "" "")) 3895 (pc)))] 3896 "" 3897 "{ operands[1] = alpha_emit_conditional_branch (LTU); }") 3898 3899(define_expand "bleu" 3900 [(set (pc) 3901 (if_then_else (match_dup 1) 3902 (label_ref (match_operand 0 "" "")) 3903 (pc)))] 3904 "" 3905 "{ operands[1] = alpha_emit_conditional_branch (LEU); }") 3906 3907(define_expand "bgtu" 3908 [(set (pc) 3909 (if_then_else (match_dup 1) 3910 (label_ref (match_operand 0 "" "")) 3911 (pc)))] 3912 "" 3913 "{ operands[1] = alpha_emit_conditional_branch (GTU); }") 3914 3915(define_expand "bgeu" 3916 [(set (pc) 3917 (if_then_else (match_dup 1) 3918 (label_ref (match_operand 0 "" "")) 3919 (pc)))] 3920 "" 3921 "{ operands[1] = alpha_emit_conditional_branch (GEU); }") 3922 3923(define_expand "bunordered" 3924 [(set (pc) 3925 (if_then_else (match_dup 1) 3926 (label_ref (match_operand 0 "" "")) 3927 (pc)))] 3928 "" 3929 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }") 3930 3931(define_expand "bordered" 3932 [(set (pc) 3933 (if_then_else (match_dup 1) 3934 (label_ref (match_operand 0 "" "")) 3935 (pc)))] 3936 "" 3937 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }") 3938 3939(define_expand "seq" 3940 [(set (match_operand:DI 0 "register_operand" "") 3941 (match_dup 1))] 3942 "" 3943 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }") 3944 3945(define_expand "sne" 3946 [(set (match_operand:DI 0 "register_operand" "") 3947 (match_dup 1))] 3948 "" 3949 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }") 3950 3951(define_expand "slt" 3952 [(set (match_operand:DI 0 "register_operand" "") 3953 (match_dup 1))] 3954 "" 3955 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }") 3956 3957(define_expand "sle" 3958 [(set (match_operand:DI 0 "register_operand" "") 3959 (match_dup 1))] 3960 "" 3961 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }") 3962 3963(define_expand "sgt" 3964 [(set (match_operand:DI 0 "register_operand" "") 3965 (match_dup 1))] 3966 "" 3967 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }") 3968 3969(define_expand "sge" 3970 [(set (match_operand:DI 0 "register_operand" "") 3971 (match_dup 1))] 3972 "" 3973 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }") 3974 3975(define_expand "sltu" 3976 [(set (match_operand:DI 0 "register_operand" "") 3977 (match_dup 1))] 3978 "" 3979 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }") 3980 3981(define_expand "sleu" 3982 [(set (match_operand:DI 0 "register_operand" "") 3983 (match_dup 1))] 3984 "" 3985 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }") 3986 3987(define_expand "sgtu" 3988 [(set (match_operand:DI 0 "register_operand" "") 3989 (match_dup 1))] 3990 "" 3991 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }") 3992 3993(define_expand "sgeu" 3994 [(set (match_operand:DI 0 "register_operand" "") 3995 (match_dup 1))] 3996 "" 3997 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }") 3998 3999(define_expand "sunordered" 4000 [(set (match_operand:DI 0 "register_operand" "") 4001 (match_dup 1))] 4002 "" 4003 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }") 4004 4005(define_expand "sordered" 4006 [(set (match_operand:DI 0 "register_operand" "") 4007 (match_dup 1))] 4008 "" 4009 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }") 4010 4011;; These are the main define_expand's used to make conditional moves. 4012 4013(define_expand "movsicc" 4014 [(set (match_operand:SI 0 "register_operand" "") 4015 (if_then_else:SI (match_operand 1 "comparison_operator" "") 4016 (match_operand:SI 2 "reg_or_8bit_operand" "") 4017 (match_operand:SI 3 "reg_or_8bit_operand" "")))] 4018 "" 4019{ 4020 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0) 4021 FAIL; 4022}) 4023 4024(define_expand "movdicc" 4025 [(set (match_operand:DI 0 "register_operand" "") 4026 (if_then_else:DI (match_operand 1 "comparison_operator" "") 4027 (match_operand:DI 2 "reg_or_8bit_operand" "") 4028 (match_operand:DI 3 "reg_or_8bit_operand" "")))] 4029 "" 4030{ 4031 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0) 4032 FAIL; 4033}) 4034 4035(define_expand "movsfcc" 4036 [(set (match_operand:SF 0 "register_operand" "") 4037 (if_then_else:SF (match_operand 1 "comparison_operator" "") 4038 (match_operand:SF 2 "reg_or_8bit_operand" "") 4039 (match_operand:SF 3 "reg_or_8bit_operand" "")))] 4040 "" 4041{ 4042 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0) 4043 FAIL; 4044}) 4045 4046(define_expand "movdfcc" 4047 [(set (match_operand:DF 0 "register_operand" "") 4048 (if_then_else:DF (match_operand 1 "comparison_operator" "") 4049 (match_operand:DF 2 "reg_or_8bit_operand" "") 4050 (match_operand:DF 3 "reg_or_8bit_operand" "")))] 4051 "" 4052{ 4053 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0) 4054 FAIL; 4055}) 4056 4057;; These define_split definitions are used in cases when comparisons have 4058;; not be stated in the correct way and we need to reverse the second 4059;; comparison. For example, x >= 7 has to be done as x < 6 with the 4060;; comparison that tests the result being reversed. We have one define_split 4061;; for each use of a comparison. They do not match valid insns and need 4062;; not generate valid insns. 4063;; 4064;; We can also handle equality comparisons (and inequality comparisons in 4065;; cases where the resulting add cannot overflow) by doing an add followed by 4066;; a comparison with zero. This is faster since the addition takes one 4067;; less cycle than a compare when feeding into a conditional move. 4068;; For this case, we also have an SImode pattern since we can merge the add 4069;; and sign extend and the order doesn't matter. 4070;; 4071;; We do not do this for floating-point, since it isn't clear how the "wrong" 4072;; operation could have been generated. 4073 4074(define_split 4075 [(set (match_operand:DI 0 "register_operand" "") 4076 (if_then_else:DI 4077 (match_operator 1 "comparison_operator" 4078 [(match_operand:DI 2 "reg_or_0_operand" "") 4079 (match_operand:DI 3 "reg_or_cint_operand" "")]) 4080 (match_operand:DI 4 "reg_or_cint_operand" "") 4081 (match_operand:DI 5 "reg_or_cint_operand" ""))) 4082 (clobber (match_operand:DI 6 "register_operand" ""))] 4083 "operands[3] != const0_rtx" 4084 [(set (match_dup 6) (match_dup 7)) 4085 (set (match_dup 0) 4086 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 4087{ 4088 enum rtx_code code = GET_CODE (operands[1]); 4089 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 4090 4091 /* If we are comparing for equality with a constant and that constant 4092 appears in the arm when the register equals the constant, use the 4093 register since that is more likely to match (and to produce better code 4094 if both would). */ 4095 4096 if (code == EQ && GET_CODE (operands[3]) == CONST_INT 4097 && rtx_equal_p (operands[4], operands[3])) 4098 operands[4] = operands[2]; 4099 4100 else if (code == NE && GET_CODE (operands[3]) == CONST_INT 4101 && rtx_equal_p (operands[5], operands[3])) 4102 operands[5] = operands[2]; 4103 4104 if (code == NE || code == EQ 4105 || (extended_count (operands[2], DImode, unsignedp) >= 1 4106 && extended_count (operands[3], DImode, unsignedp) >= 1)) 4107 { 4108 if (GET_CODE (operands[3]) == CONST_INT) 4109 operands[7] = gen_rtx_PLUS (DImode, operands[2], 4110 GEN_INT (- INTVAL (operands[3]))); 4111 else 4112 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]); 4113 4114 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx); 4115 } 4116 4117 else if (code == EQ || code == LE || code == LT 4118 || code == LEU || code == LTU) 4119 { 4120 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]); 4121 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx); 4122 } 4123 else 4124 { 4125 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode, 4126 operands[2], operands[3]); 4127 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx); 4128 } 4129}) 4130 4131(define_split 4132 [(set (match_operand:DI 0 "register_operand" "") 4133 (if_then_else:DI 4134 (match_operator 1 "comparison_operator" 4135 [(match_operand:SI 2 "reg_or_0_operand" "") 4136 (match_operand:SI 3 "reg_or_cint_operand" "")]) 4137 (match_operand:DI 4 "reg_or_8bit_operand" "") 4138 (match_operand:DI 5 "reg_or_8bit_operand" ""))) 4139 (clobber (match_operand:DI 6 "register_operand" ""))] 4140 "operands[3] != const0_rtx 4141 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" 4142 [(set (match_dup 6) (match_dup 7)) 4143 (set (match_dup 0) 4144 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 4145{ 4146 enum rtx_code code = GET_CODE (operands[1]); 4147 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 4148 rtx tem; 4149 4150 if ((code != NE && code != EQ 4151 && ! (extended_count (operands[2], DImode, unsignedp) >= 1 4152 && extended_count (operands[3], DImode, unsignedp) >= 1))) 4153 FAIL; 4154 4155 if (GET_CODE (operands[3]) == CONST_INT) 4156 tem = gen_rtx_PLUS (SImode, operands[2], 4157 GEN_INT (- INTVAL (operands[3]))); 4158 else 4159 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]); 4160 4161 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem); 4162 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode, 4163 operands[6], const0_rtx); 4164}) 4165 4166(define_split 4167 [(set (pc) 4168 (if_then_else 4169 (match_operator 1 "comparison_operator" 4170 [(match_operand:DI 2 "reg_or_0_operand" "") 4171 (match_operand:DI 3 "reg_or_cint_operand" "")]) 4172 (label_ref (match_operand 0 "" "")) 4173 (pc))) 4174 (clobber (match_operand:DI 4 "register_operand" ""))] 4175 "operands[3] != const0_rtx" 4176 [(set (match_dup 4) (match_dup 5)) 4177 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))] 4178{ 4179 enum rtx_code code = GET_CODE (operands[1]); 4180 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 4181 4182 if (code == NE || code == EQ 4183 || (extended_count (operands[2], DImode, unsignedp) >= 1 4184 && extended_count (operands[3], DImode, unsignedp) >= 1)) 4185 { 4186 if (GET_CODE (operands[3]) == CONST_INT) 4187 operands[5] = gen_rtx_PLUS (DImode, operands[2], 4188 GEN_INT (- INTVAL (operands[3]))); 4189 else 4190 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]); 4191 4192 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx); 4193 } 4194 4195 else if (code == EQ || code == LE || code == LT 4196 || code == LEU || code == LTU) 4197 { 4198 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]); 4199 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx); 4200 } 4201 else 4202 { 4203 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode, 4204 operands[2], operands[3]); 4205 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx); 4206 } 4207}) 4208 4209(define_split 4210 [(set (pc) 4211 (if_then_else 4212 (match_operator 1 "comparison_operator" 4213 [(match_operand:SI 2 "reg_or_0_operand" "") 4214 (match_operand:SI 3 "const_int_operand" "")]) 4215 (label_ref (match_operand 0 "" "")) 4216 (pc))) 4217 (clobber (match_operand:DI 4 "register_operand" ""))] 4218 "operands[3] != const0_rtx 4219 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" 4220 [(set (match_dup 4) (match_dup 5)) 4221 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))] 4222{ 4223 rtx tem; 4224 4225 if (GET_CODE (operands[3]) == CONST_INT) 4226 tem = gen_rtx_PLUS (SImode, operands[2], 4227 GEN_INT (- INTVAL (operands[3]))); 4228 else 4229 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]); 4230 4231 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem); 4232 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode, 4233 operands[4], const0_rtx); 4234}) 4235 4236;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0". 4237;; This eliminates one, and sometimes two, insns when the AND can be done 4238;; with a ZAP. 4239(define_split 4240 [(set (match_operand:DI 0 "register_operand" "") 4241 (match_operator:DI 1 "comparison_operator" 4242 [(match_operand:DI 2 "register_operand" "") 4243 (match_operand:DI 3 "const_int_operand" "")])) 4244 (clobber (match_operand:DI 4 "register_operand" ""))] 4245 "exact_log2 (INTVAL (operands[3]) + 1) >= 0 4246 && (GET_CODE (operands[1]) == GTU 4247 || GET_CODE (operands[1]) == LEU 4248 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE) 4249 && extended_count (operands[2], DImode, 1) > 0))" 4250 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5))) 4251 (set (match_dup 0) (match_dup 6))] 4252{ 4253 operands[5] = GEN_INT (~ INTVAL (operands[3])); 4254 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU 4255 || GET_CODE (operands[1]) == GT) 4256 ? NE : EQ), 4257 DImode, operands[4], const0_rtx); 4258}) 4259 4260;; Prefer to use cmp and arithmetic when possible instead of a cmove. 4261 4262(define_split 4263 [(set (match_operand 0 "register_operand" "") 4264 (if_then_else (match_operator 1 "signed_comparison_operator" 4265 [(match_operand:DI 2 "reg_or_0_operand" "") 4266 (const_int 0)]) 4267 (match_operand 3 "const_int_operand" "") 4268 (match_operand 4 "const_int_operand" "")))] 4269 "" 4270 [(const_int 0)] 4271{ 4272 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0], 4273 operands[2], operands[3], operands[4])) 4274 DONE; 4275 else 4276 FAIL; 4277}) 4278 4279;; ??? Why combine is allowed to create such non-canonical rtl, I don't know. 4280;; Oh well, we match it in movcc, so it must be partially our fault. 4281(define_split 4282 [(set (match_operand 0 "register_operand" "") 4283 (if_then_else (match_operator 1 "signed_comparison_operator" 4284 [(const_int 0) 4285 (match_operand:DI 2 "reg_or_0_operand" "")]) 4286 (match_operand 3 "const_int_operand" "") 4287 (match_operand 4 "const_int_operand" "")))] 4288 "" 4289 [(const_int 0)] 4290{ 4291 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])), 4292 operands[0], operands[2], operands[3], 4293 operands[4])) 4294 DONE; 4295 else 4296 FAIL; 4297}) 4298 4299(define_insn_and_split "*cmp_sadd_di" 4300 [(set (match_operand:DI 0 "register_operand" "=r") 4301 (plus:DI (if_then_else:DI 4302 (match_operator 1 "alpha_zero_comparison_operator" 4303 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 4304 (const_int 0)]) 4305 (match_operand:DI 3 "const48_operand" "I") 4306 (const_int 0)) 4307 (match_operand:DI 4 "sext_add_operand" "rIO"))) 4308 (clobber (match_scratch:DI 5 "=r"))] 4309 "" 4310 "#" 4311 "! no_new_pseudos || reload_completed" 4312 [(set (match_dup 5) 4313 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 4314 (set (match_dup 0) 4315 (plus:DI (mult:DI (match_dup 5) (match_dup 3)) 4316 (match_dup 4)))] 4317{ 4318 if (! no_new_pseudos) 4319 operands[5] = gen_reg_rtx (DImode); 4320 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 4321 operands[5] = operands[0]; 4322}) 4323 4324(define_insn_and_split "*cmp_sadd_si" 4325 [(set (match_operand:SI 0 "register_operand" "=r") 4326 (plus:SI (if_then_else:SI 4327 (match_operator 1 "alpha_zero_comparison_operator" 4328 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 4329 (const_int 0)]) 4330 (match_operand:SI 3 "const48_operand" "I") 4331 (const_int 0)) 4332 (match_operand:SI 4 "sext_add_operand" "rIO"))) 4333 (clobber (match_scratch:SI 5 "=r"))] 4334 "" 4335 "#" 4336 "! no_new_pseudos || reload_completed" 4337 [(set (match_dup 5) 4338 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)])) 4339 (set (match_dup 0) 4340 (plus:SI (mult:SI (match_dup 5) (match_dup 3)) 4341 (match_dup 4)))] 4342{ 4343 if (! no_new_pseudos) 4344 operands[5] = gen_reg_rtx (DImode); 4345 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 4346 operands[5] = operands[0]; 4347}) 4348 4349(define_insn_and_split "*cmp_sadd_sidi" 4350 [(set (match_operand:DI 0 "register_operand" "=r") 4351 (sign_extend:DI 4352 (plus:SI (if_then_else:SI 4353 (match_operator 1 "alpha_zero_comparison_operator" 4354 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 4355 (const_int 0)]) 4356 (match_operand:SI 3 "const48_operand" "I") 4357 (const_int 0)) 4358 (match_operand:SI 4 "sext_add_operand" "rIO")))) 4359 (clobber (match_scratch:SI 5 "=r"))] 4360 "" 4361 "#" 4362 "! no_new_pseudos || reload_completed" 4363 [(set (match_dup 5) 4364 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)])) 4365 (set (match_dup 0) 4366 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3)) 4367 (match_dup 4))))] 4368{ 4369 if (! no_new_pseudos) 4370 operands[5] = gen_reg_rtx (DImode); 4371 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 4372 operands[5] = operands[0]; 4373}) 4374 4375(define_insn_and_split "*cmp_ssub_di" 4376 [(set (match_operand:DI 0 "register_operand" "=r") 4377 (minus:DI (if_then_else:DI 4378 (match_operator 1 "alpha_zero_comparison_operator" 4379 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 4380 (const_int 0)]) 4381 (match_operand:DI 3 "const48_operand" "I") 4382 (const_int 0)) 4383 (match_operand:DI 4 "reg_or_8bit_operand" "rI"))) 4384 (clobber (match_scratch:DI 5 "=r"))] 4385 "" 4386 "#" 4387 "! no_new_pseudos || reload_completed" 4388 [(set (match_dup 5) 4389 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 4390 (set (match_dup 0) 4391 (minus:DI (mult:DI (match_dup 5) (match_dup 3)) 4392 (match_dup 4)))] 4393{ 4394 if (! no_new_pseudos) 4395 operands[5] = gen_reg_rtx (DImode); 4396 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 4397 operands[5] = operands[0]; 4398}) 4399 4400(define_insn_and_split "*cmp_ssub_si" 4401 [(set (match_operand:SI 0 "register_operand" "=r") 4402 (minus:SI (if_then_else:SI 4403 (match_operator 1 "alpha_zero_comparison_operator" 4404 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 4405 (const_int 0)]) 4406 (match_operand:SI 3 "const48_operand" "I") 4407 (const_int 0)) 4408 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))) 4409 (clobber (match_scratch:SI 5 "=r"))] 4410 "" 4411 "#" 4412 "! no_new_pseudos || reload_completed" 4413 [(set (match_dup 5) 4414 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)])) 4415 (set (match_dup 0) 4416 (minus:SI (mult:SI (match_dup 5) (match_dup 3)) 4417 (match_dup 4)))] 4418{ 4419 if (! no_new_pseudos) 4420 operands[5] = gen_reg_rtx (DImode); 4421 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 4422 operands[5] = operands[0]; 4423}) 4424 4425(define_insn_and_split "*cmp_ssub_sidi" 4426 [(set (match_operand:DI 0 "register_operand" "=r") 4427 (sign_extend:DI 4428 (minus:SI (if_then_else:SI 4429 (match_operator 1 "alpha_zero_comparison_operator" 4430 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 4431 (const_int 0)]) 4432 (match_operand:SI 3 "const48_operand" "I") 4433 (const_int 0)) 4434 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))) 4435 (clobber (match_scratch:SI 5 "=r"))] 4436 "" 4437 "#" 4438 "! no_new_pseudos || reload_completed" 4439 [(set (match_dup 5) 4440 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)])) 4441 (set (match_dup 0) 4442 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3)) 4443 (match_dup 4))))] 4444{ 4445 if (! no_new_pseudos) 4446 operands[5] = gen_reg_rtx (DImode); 4447 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 4448 operands[5] = operands[0]; 4449}) 4450 4451;; Here are the CALL and unconditional branch insns. Calls on NT and OSF 4452;; work differently, so we have different patterns for each. 4453 4454;; On Unicos/Mk a call information word (CIW) must be generated for each 4455;; call. The CIW contains information about arguments passed in registers 4456;; and is stored in the caller's SSIB. Its offset relative to the beginning 4457;; of the SSIB is passed in $25. Handling this properly is quite complicated 4458;; in the presence of inlining since the CIWs for calls performed by the 4459;; inlined function must be stored in the SSIB of the function it is inlined 4460;; into as well. We encode the CIW in an unspec and append it to the list 4461;; of the CIWs for the current function only when the instruction for loading 4462;; $25 is generated. 4463 4464(define_expand "call" 4465 [(use (match_operand:DI 0 "" "")) 4466 (use (match_operand 1 "" "")) 4467 (use (match_operand 2 "" "")) 4468 (use (match_operand 3 "" ""))] 4469 "" 4470{ 4471 if (TARGET_ABI_WINDOWS_NT) 4472 emit_call_insn (gen_call_nt (operands[0], operands[1])); 4473 else if (TARGET_ABI_OPEN_VMS) 4474 emit_call_insn (gen_call_vms (operands[0], operands[2])); 4475 else if (TARGET_ABI_UNICOSMK) 4476 emit_call_insn (gen_call_umk (operands[0], operands[2])); 4477 else 4478 emit_call_insn (gen_call_osf (operands[0], operands[1])); 4479 DONE; 4480}) 4481 4482(define_expand "sibcall" 4483 [(parallel [(call (mem:DI (match_operand 0 "" "")) 4484 (match_operand 1 "" "")) 4485 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 4486 "TARGET_ABI_OSF" 4487{ 4488 if (GET_CODE (operands[0]) != MEM) 4489 abort (); 4490 operands[0] = XEXP (operands[0], 0); 4491}) 4492 4493(define_expand "call_osf" 4494 [(parallel [(call (mem:DI (match_operand 0 "" "")) 4495 (match_operand 1 "" "")) 4496 (use (reg:DI 29)) 4497 (clobber (reg:DI 26))])] 4498 "" 4499{ 4500 if (GET_CODE (operands[0]) != MEM) 4501 abort (); 4502 4503 operands[0] = XEXP (operands[0], 0); 4504 if (! call_operand (operands[0], Pmode)) 4505 operands[0] = copy_to_mode_reg (Pmode, operands[0]); 4506}) 4507 4508(define_expand "call_nt" 4509 [(parallel [(call (mem:DI (match_operand 0 "" "")) 4510 (match_operand 1 "" "")) 4511 (clobber (reg:DI 26))])] 4512 "" 4513{ 4514 if (GET_CODE (operands[0]) != MEM) 4515 abort (); 4516 4517 operands[0] = XEXP (operands[0], 0); 4518 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG) 4519 operands[0] = force_reg (DImode, operands[0]); 4520}) 4521 4522;; Calls on Unicos/Mk are always indirect. 4523;; op 0: symbol ref for called function 4524;; op 1: CIW for $25 represented by an unspec 4525 4526(define_expand "call_umk" 4527 [(parallel [(call (mem:DI (match_operand 0 "" "")) 4528 (match_operand 1 "" "")) 4529 (use (reg:DI 25)) 4530 (clobber (reg:DI 26))])] 4531 "" 4532{ 4533 if (GET_CODE (operands[0]) != MEM) 4534 abort (); 4535 4536 /* Always load the address of the called function into a register; 4537 load the CIW in $25. */ 4538 4539 operands[0] = XEXP (operands[0], 0); 4540 if (GET_CODE (operands[0]) != REG) 4541 operands[0] = force_reg (DImode, operands[0]); 4542 4543 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]); 4544}) 4545 4546;; 4547;; call openvms/alpha 4548;; op 0: symbol ref for called function 4549;; op 1: next_arg_reg (argument information value for R25) 4550;; 4551(define_expand "call_vms" 4552 [(parallel [(call (mem:DI (match_operand 0 "" "")) 4553 (match_operand 1 "" "")) 4554 (use (match_dup 2)) 4555 (use (reg:DI 25)) 4556 (use (reg:DI 26)) 4557 (clobber (reg:DI 27))])] 4558 "" 4559{ 4560 if (GET_CODE (operands[0]) != MEM) 4561 abort (); 4562 4563 operands[0] = XEXP (operands[0], 0); 4564 4565 /* Always load AI with argument information, then handle symbolic and 4566 indirect call differently. Load RA and set operands[2] to PV in 4567 both cases. */ 4568 4569 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]); 4570 if (GET_CODE (operands[0]) == SYMBOL_REF) 4571 { 4572 alpha_need_linkage (XSTR (operands[0], 0), 0); 4573 4574 operands[2] = const0_rtx; 4575 } 4576 else 4577 { 4578 emit_move_insn (gen_rtx_REG (Pmode, 26), 4579 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8))); 4580 operands[2] = operands[0]; 4581 } 4582 4583}) 4584 4585(define_expand "call_value" 4586 [(use (match_operand 0 "" "")) 4587 (use (match_operand:DI 1 "" "")) 4588 (use (match_operand 2 "" "")) 4589 (use (match_operand 3 "" "")) 4590 (use (match_operand 4 "" ""))] 4591 "" 4592{ 4593 if (TARGET_ABI_WINDOWS_NT) 4594 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2])); 4595 else if (TARGET_ABI_OPEN_VMS) 4596 emit_call_insn (gen_call_value_vms (operands[0], operands[1], 4597 operands[3])); 4598 else if (TARGET_ABI_UNICOSMK) 4599 emit_call_insn (gen_call_value_umk (operands[0], operands[1], 4600 operands[3])); 4601 else 4602 emit_call_insn (gen_call_value_osf (operands[0], operands[1], 4603 operands[2])); 4604 DONE; 4605}) 4606 4607(define_expand "sibcall_value" 4608 [(parallel [(set (match_operand 0 "" "") 4609 (call (mem:DI (match_operand 1 "" "")) 4610 (match_operand 2 "" ""))) 4611 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 4612 "TARGET_ABI_OSF" 4613{ 4614 if (GET_CODE (operands[1]) != MEM) 4615 abort (); 4616 operands[1] = XEXP (operands[1], 0); 4617}) 4618 4619(define_expand "call_value_osf" 4620 [(parallel [(set (match_operand 0 "" "") 4621 (call (mem:DI (match_operand 1 "" "")) 4622 (match_operand 2 "" ""))) 4623 (use (reg:DI 29)) 4624 (clobber (reg:DI 26))])] 4625 "" 4626{ 4627 if (GET_CODE (operands[1]) != MEM) 4628 abort (); 4629 4630 operands[1] = XEXP (operands[1], 0); 4631 if (! call_operand (operands[1], Pmode)) 4632 operands[1] = copy_to_mode_reg (Pmode, operands[1]); 4633}) 4634 4635(define_expand "call_value_nt" 4636 [(parallel [(set (match_operand 0 "" "") 4637 (call (mem:DI (match_operand 1 "" "")) 4638 (match_operand 2 "" ""))) 4639 (clobber (reg:DI 26))])] 4640 "" 4641{ 4642 if (GET_CODE (operands[1]) != MEM) 4643 abort (); 4644 4645 operands[1] = XEXP (operands[1], 0); 4646 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG) 4647 operands[1] = force_reg (DImode, operands[1]); 4648}) 4649 4650(define_expand "call_value_vms" 4651 [(parallel [(set (match_operand 0 "" "") 4652 (call (mem:DI (match_operand:DI 1 "" "")) 4653 (match_operand 2 "" ""))) 4654 (use (match_dup 3)) 4655 (use (reg:DI 25)) 4656 (use (reg:DI 26)) 4657 (clobber (reg:DI 27))])] 4658 "" 4659{ 4660 if (GET_CODE (operands[1]) != MEM) 4661 abort (); 4662 4663 operands[1] = XEXP (operands[1], 0); 4664 4665 /* Always load AI with argument information, then handle symbolic and 4666 indirect call differently. Load RA and set operands[3] to PV in 4667 both cases. */ 4668 4669 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]); 4670 if (GET_CODE (operands[1]) == SYMBOL_REF) 4671 { 4672 alpha_need_linkage (XSTR (operands[1], 0), 0); 4673 4674 operands[3] = const0_rtx; 4675 } 4676 else 4677 { 4678 emit_move_insn (gen_rtx_REG (Pmode, 26), 4679 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8))); 4680 operands[3] = operands[1]; 4681 } 4682}) 4683 4684(define_expand "call_value_umk" 4685 [(parallel [(set (match_operand 0 "" "") 4686 (call (mem:DI (match_operand 1 "" "")) 4687 (match_operand 2 "" ""))) 4688 (use (reg:DI 25)) 4689 (clobber (reg:DI 26))])] 4690 "" 4691{ 4692 if (GET_CODE (operands[1]) != MEM) 4693 abort (); 4694 4695 operands[1] = XEXP (operands[1], 0); 4696 if (GET_CODE (operands[1]) != REG) 4697 operands[1] = force_reg (DImode, operands[1]); 4698 4699 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]); 4700}) 4701 4702(define_insn "*call_osf_1_er" 4703 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 4704 (match_operand 1 "" "")) 4705 (use (reg:DI 29)) 4706 (clobber (reg:DI 26))] 4707 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4708 "@ 4709 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 4710 bsr $26,%0\t\t!samegp 4711 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 4712 [(set_attr "type" "jsr") 4713 (set_attr "length" "12,*,16")]) 4714 4715;; We must use peep2 instead of a split because we need accurate life 4716;; information for $gp. Consider the case of { bar(); while (1); }. 4717(define_peephole2 4718 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" "")) 4719 (match_operand 1 "" "")) 4720 (use (reg:DI 29)) 4721 (clobber (reg:DI 26))])] 4722 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 4723 && ! samegp_function_operand (operands[0], Pmode) 4724 && (peep2_regno_dead_p (1, 29) 4725 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 4726 [(parallel [(call (mem:DI (match_dup 2)) 4727 (match_dup 1)) 4728 (set (reg:DI 26) (plus:DI (pc) (const_int 4))) 4729 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) 4730 (use (match_dup 0)) 4731 (use (match_dup 3))])] 4732{ 4733 if (CONSTANT_P (operands[0])) 4734 { 4735 operands[2] = gen_rtx_REG (Pmode, 27); 4736 operands[3] = GEN_INT (alpha_next_sequence_number++); 4737 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 4738 operands[0], operands[3])); 4739 } 4740 else 4741 { 4742 operands[2] = operands[0]; 4743 operands[0] = const0_rtx; 4744 operands[3] = const0_rtx; 4745 } 4746}) 4747 4748(define_peephole2 4749 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" "")) 4750 (match_operand 1 "" "")) 4751 (use (reg:DI 29)) 4752 (clobber (reg:DI 26))])] 4753 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 4754 && ! samegp_function_operand (operands[0], Pmode) 4755 && ! (peep2_regno_dead_p (1, 29) 4756 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 4757 [(parallel [(call (mem:DI (match_dup 2)) 4758 (match_dup 1)) 4759 (set (reg:DI 26) (plus:DI (pc) (const_int 4))) 4760 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) 4761 (use (match_dup 0)) 4762 (use (match_dup 4))]) 4763 (set (reg:DI 29) 4764 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1)) 4765 (set (reg:DI 29) 4766 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))] 4767{ 4768 if (CONSTANT_P (operands[0])) 4769 { 4770 operands[2] = gen_rtx_REG (Pmode, 27); 4771 operands[4] = GEN_INT (alpha_next_sequence_number++); 4772 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 4773 operands[0], operands[4])); 4774 } 4775 else 4776 { 4777 operands[2] = operands[0]; 4778 operands[0] = const0_rtx; 4779 operands[4] = const0_rtx; 4780 } 4781 operands[3] = GEN_INT (alpha_next_sequence_number++); 4782}) 4783 4784;; We add a blockage unspec_volatile to prevent insns from moving down 4785;; from above the call to in between the call and the ldah gpdisp. 4786 4787(define_insn "*call_osf_2_er" 4788 [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 4789 (match_operand 1 "" "")) 4790 (set (reg:DI 26) (plus:DI (pc) (const_int 4))) 4791 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) 4792 (use (match_operand 2 "" "")) 4793 (use (match_operand 3 "const_int_operand" ""))] 4794 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4795 "jsr $26,(%0),%2%J3" 4796 [(set_attr "type" "jsr") 4797 (set_attr "cannot_copy" "true")]) 4798 4799;; We output a nop after noreturn calls at the very end of the function to 4800;; ensure that the return address always remains in the caller's code range, 4801;; as not doing so might confuse unwinding engines. 4802;; 4803;; The potential change in insn length is not reflected in the length 4804;; attributes at this stage. Since the extra space is only actually added at 4805;; the very end of the compilation process (via final/print_operand), it 4806;; really seems harmless and not worth the trouble of some extra computation 4807;; cost and complexity. 4808 4809(define_insn "*call_osf_1_noreturn" 4810 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 4811 (match_operand 1 "" "")) 4812 (use (reg:DI 29)) 4813 (clobber (reg:DI 26))] 4814 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 4815 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 4816 "@ 4817 jsr $26,($27),0%+ 4818 bsr $26,$%0..ng%+ 4819 jsr $26,%0%+" 4820 [(set_attr "type" "jsr") 4821 (set_attr "length" "*,*,8")]) 4822 4823(define_insn "*call_osf_1" 4824 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 4825 (match_operand 1 "" "")) 4826 (use (reg:DI 29)) 4827 (clobber (reg:DI 26))] 4828 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4829 "@ 4830 jsr $26,($27),0\;ldgp $29,0($26) 4831 bsr $26,$%0..ng 4832 jsr $26,%0\;ldgp $29,0($26)" 4833 [(set_attr "type" "jsr") 4834 (set_attr "length" "12,*,16")]) 4835 4836;; Note that the DEC assembler expands "jmp foo" with $at, which 4837;; doesn't do what we want. 4838(define_insn "*sibcall_osf_1_er" 4839 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 4840 (match_operand 1 "" "")) 4841 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 4842 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4843 "@ 4844 br $31,%0\t\t!samegp 4845 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#" 4846 [(set_attr "type" "jsr") 4847 (set_attr "length" "*,8")]) 4848 4849(define_insn "*sibcall_osf_1" 4850 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 4851 (match_operand 1 "" "")) 4852 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 4853 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4854 "@ 4855 br $31,$%0..ng 4856 lda $27,%0\;jmp $31,($27),%0" 4857 [(set_attr "type" "jsr") 4858 (set_attr "length" "*,8")]) 4859 4860(define_insn "*call_nt_1" 4861 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s")) 4862 (match_operand 1 "" "")) 4863 (clobber (reg:DI 26))] 4864 "TARGET_ABI_WINDOWS_NT" 4865 "@ 4866 jsr $26,(%0) 4867 bsr $26,%0 4868 jsr $26,%0" 4869 [(set_attr "type" "jsr") 4870 (set_attr "length" "*,*,12")]) 4871 4872; GAS relies on the order and position of instructions output below in order 4873; to generate relocs for VMS link to potentially optimize the call. 4874; Please do not molest. 4875(define_insn "*call_vms_1" 4876 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s")) 4877 (match_operand 1 "" "")) 4878 (use (match_operand:DI 2 "nonmemory_operand" "r,n")) 4879 (use (reg:DI 25)) 4880 (use (reg:DI 26)) 4881 (clobber (reg:DI 27))] 4882 "TARGET_ABI_OPEN_VMS" 4883{ 4884 switch (which_alternative) 4885 { 4886 case 0: 4887 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)"; 4888 case 1: 4889 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0); 4890 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0); 4891 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"; 4892 default: 4893 abort(); 4894 } 4895} 4896 [(set_attr "type" "jsr") 4897 (set_attr "length" "12,16")]) 4898 4899(define_insn "*call_umk_1" 4900 [(call (mem:DI (match_operand:DI 0 "call_operand" "r")) 4901 (match_operand 1 "" "")) 4902 (use (reg:DI 25)) 4903 (clobber (reg:DI 26))] 4904 "TARGET_ABI_UNICOSMK" 4905 "jsr $26,(%0)" 4906 [(set_attr "type" "jsr")]) 4907 4908;; Call subroutine returning any type. 4909 4910(define_expand "untyped_call" 4911 [(parallel [(call (match_operand 0 "" "") 4912 (const_int 0)) 4913 (match_operand 1 "" "") 4914 (match_operand 2 "" "")])] 4915 "" 4916{ 4917 int i; 4918 4919 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); 4920 4921 for (i = 0; i < XVECLEN (operands[2], 0); i++) 4922 { 4923 rtx set = XVECEXP (operands[2], 0, i); 4924 emit_move_insn (SET_DEST (set), SET_SRC (set)); 4925 } 4926 4927 /* The optimizer does not know that the call sets the function value 4928 registers we stored in the result block. We avoid problems by 4929 claiming that all hard registers are used and clobbered at this 4930 point. */ 4931 emit_insn (gen_blockage ()); 4932 4933 DONE; 4934}) 4935 4936;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 4937;; all of memory. This blocks insns from being moved across this point. 4938 4939(define_insn "blockage" 4940 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 4941 "" 4942 "" 4943 [(set_attr "length" "0") 4944 (set_attr "type" "none")]) 4945 4946(define_insn "jump" 4947 [(set (pc) 4948 (label_ref (match_operand 0 "" "")))] 4949 "" 4950 "br $31,%l0" 4951 [(set_attr "type" "ibr")]) 4952 4953(define_expand "return" 4954 [(return)] 4955 "direct_return ()" 4956 "") 4957 4958(define_insn "*return_internal" 4959 [(return)] 4960 "reload_completed" 4961 "ret $31,($26),1" 4962 [(set_attr "type" "ibr")]) 4963 4964(define_insn "indirect_jump" 4965 [(set (pc) (match_operand:DI 0 "register_operand" "r"))] 4966 "" 4967 "jmp $31,(%0),0" 4968 [(set_attr "type" "ibr")]) 4969 4970(define_expand "tablejump" 4971 [(parallel [(set (pc) 4972 (match_operand 0 "register_operand" "")) 4973 (use (label_ref:DI (match_operand 1 "" "")))])] 4974 "" 4975{ 4976 if (TARGET_ABI_WINDOWS_NT) 4977 { 4978 rtx dest = gen_reg_rtx (DImode); 4979 emit_insn (gen_extendsidi2 (dest, operands[0])); 4980 operands[0] = dest; 4981 } 4982 else if (TARGET_ABI_OSF) 4983 { 4984 rtx dest = gen_reg_rtx (DImode); 4985 emit_insn (gen_extendsidi2 (dest, operands[0])); 4986 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest)); 4987 operands[0] = dest; 4988 } 4989}) 4990 4991(define_insn "*tablejump_osf_nt_internal" 4992 [(set (pc) 4993 (match_operand:DI 0 "register_operand" "r")) 4994 (use (label_ref:DI (match_operand 1 "" "")))] 4995 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT) 4996 && alpha_tablejump_addr_vec (insn)" 4997{ 4998 operands[2] = alpha_tablejump_best_label (insn); 4999 return "jmp $31,(%0),%2"; 5000} 5001 [(set_attr "type" "ibr")]) 5002 5003(define_insn "*tablejump_internal" 5004 [(set (pc) 5005 (match_operand:DI 0 "register_operand" "r")) 5006 (use (label_ref (match_operand 1 "" "")))] 5007 "" 5008 "jmp $31,(%0),0" 5009 [(set_attr "type" "ibr")]) 5010 5011;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't 5012;; want to have to include pal.h in our .s file. 5013;; 5014;; Technically the type for call_pal is jsr, but we use that for determining 5015;; if we need a GP. Use ibr instead since it has the same EV5 scheduling 5016;; characteristics. 5017(define_insn "imb" 5018 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)] 5019 "" 5020 "call_pal 0x86" 5021 [(set_attr "type" "callpal")]) 5022 5023;; BUGCHK is documented common to OSF/1 and VMS PALcode. 5024;; NT does not document anything at 0x81 -- presumably it would generate 5025;; the equivalent of SIGILL, but this isn't that important. 5026;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode. 5027(define_insn "trap" 5028 [(trap_if (const_int 1) (const_int 0))] 5029 "!TARGET_ABI_WINDOWS_NT" 5030 "call_pal 0x81" 5031 [(set_attr "type" "callpal")]) 5032 5033;; For userland, we load the thread pointer from the TCB. 5034;; For the kernel, we load the per-cpu private value. 5035 5036(define_insn "load_tp" 5037 [(set (match_operand:DI 0 "register_operand" "=v") 5038 (unspec:DI [(const_int 0)] UNSPEC_TP))] 5039 "TARGET_ABI_OSF" 5040{ 5041 if (TARGET_TLS_KERNEL) 5042 return "call_pal 0x32"; 5043 else 5044 return "call_pal 0x9e"; 5045} 5046 [(set_attr "type" "callpal")]) 5047 5048;; For completeness, and possibly a __builtin function, here's how to 5049;; set the thread pointer. Since we don't describe enough of this 5050;; quantity for CSE, we have to use a volatile unspec, and then there's 5051;; not much point in creating an R16_REG register class. 5052 5053(define_expand "set_tp" 5054 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" "")) 5055 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 5056 "TARGET_ABI_OSF" 5057 "") 5058 5059(define_insn "*set_tp" 5060 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 5061 "TARGET_ABI_OSF" 5062{ 5063 if (TARGET_TLS_KERNEL) 5064 return "call_pal 0x31"; 5065 else 5066 return "call_pal 0x9f"; 5067} 5068 [(set_attr "type" "callpal")]) 5069 5070;; Finally, we have the basic data motion insns. The byte and word insns 5071;; are done via define_expand. Start with the floating-point insns, since 5072;; they are simpler. 5073 5074(define_insn "*movsf_nofix" 5075 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m") 5076 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))] 5077 "TARGET_FPREGS && ! TARGET_FIX 5078 && (register_operand (operands[0], SFmode) 5079 || reg_or_0_operand (operands[1], SFmode))" 5080 "@ 5081 cpys %R1,%R1,%0 5082 ld%, %0,%1 5083 bis $31,%r1,%0 5084 ldl %0,%1 5085 st%, %R1,%0 5086 stl %r1,%0" 5087 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")]) 5088 5089(define_insn "*movsf_fix" 5090 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 5091 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 5092 "TARGET_FPREGS && TARGET_FIX 5093 && (register_operand (operands[0], SFmode) 5094 || reg_or_0_operand (operands[1], SFmode))" 5095 "@ 5096 cpys %R1,%R1,%0 5097 ld%, %0,%1 5098 bis $31,%r1,%0 5099 ldl %0,%1 5100 st%, %R1,%0 5101 stl %r1,%0 5102 itofs %1,%0 5103 ftois %1,%0" 5104 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")]) 5105 5106(define_insn "*movsf_nofp" 5107 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") 5108 (match_operand:SF 1 "input_operand" "rG,m,r"))] 5109 "! TARGET_FPREGS 5110 && (register_operand (operands[0], SFmode) 5111 || reg_or_0_operand (operands[1], SFmode))" 5112 "@ 5113 bis $31,%r1,%0 5114 ldl %0,%1 5115 stl %r1,%0" 5116 [(set_attr "type" "ilog,ild,ist")]) 5117 5118(define_insn "*movdf_nofix" 5119 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m") 5120 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))] 5121 "TARGET_FPREGS && ! TARGET_FIX 5122 && (register_operand (operands[0], DFmode) 5123 || reg_or_0_operand (operands[1], DFmode))" 5124 "@ 5125 cpys %R1,%R1,%0 5126 ld%- %0,%1 5127 bis $31,%r1,%0 5128 ldq %0,%1 5129 st%- %R1,%0 5130 stq %r1,%0" 5131 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")]) 5132 5133(define_insn "*movdf_fix" 5134 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 5135 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 5136 "TARGET_FPREGS && TARGET_FIX 5137 && (register_operand (operands[0], DFmode) 5138 || reg_or_0_operand (operands[1], DFmode))" 5139 "@ 5140 cpys %R1,%R1,%0 5141 ld%- %0,%1 5142 bis $31,%r1,%0 5143 ldq %0,%1 5144 st%- %R1,%0 5145 stq %r1,%0 5146 itoft %1,%0 5147 ftoit %1,%0" 5148 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")]) 5149 5150(define_insn "*movdf_nofp" 5151 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m") 5152 (match_operand:DF 1 "input_operand" "rG,m,r"))] 5153 "! TARGET_FPREGS 5154 && (register_operand (operands[0], DFmode) 5155 || reg_or_0_operand (operands[1], DFmode))" 5156 "@ 5157 bis $31,%r1,%0 5158 ldq %0,%1 5159 stq %r1,%0" 5160 [(set_attr "type" "ilog,ild,ist")]) 5161 5162;; Subregs suck for register allocation. Pretend we can move TFmode 5163;; data between general registers until after reload. 5164 5165(define_insn_and_split "*movtf_internal" 5166 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o") 5167 (match_operand:TF 1 "input_operand" "roG,rG"))] 5168 "register_operand (operands[0], TFmode) 5169 || reg_or_0_operand (operands[1], TFmode)" 5170 "#" 5171 "reload_completed" 5172 [(set (match_dup 0) (match_dup 2)) 5173 (set (match_dup 1) (match_dup 3))] 5174{ 5175 alpha_split_tfmode_pair (operands); 5176 if (reg_overlap_mentioned_p (operands[0], operands[3])) 5177 { 5178 rtx tmp; 5179 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp; 5180 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp; 5181 } 5182}) 5183 5184(define_expand "movsf" 5185 [(set (match_operand:SF 0 "nonimmediate_operand" "") 5186 (match_operand:SF 1 "general_operand" ""))] 5187 "" 5188{ 5189 if (GET_CODE (operands[0]) == MEM 5190 && ! reg_or_0_operand (operands[1], SFmode)) 5191 operands[1] = force_reg (SFmode, operands[1]); 5192}) 5193 5194(define_expand "movdf" 5195 [(set (match_operand:DF 0 "nonimmediate_operand" "") 5196 (match_operand:DF 1 "general_operand" ""))] 5197 "" 5198{ 5199 if (GET_CODE (operands[0]) == MEM 5200 && ! reg_or_0_operand (operands[1], DFmode)) 5201 operands[1] = force_reg (DFmode, operands[1]); 5202}) 5203 5204(define_expand "movtf" 5205 [(set (match_operand:TF 0 "nonimmediate_operand" "") 5206 (match_operand:TF 1 "general_operand" ""))] 5207 "" 5208{ 5209 if (GET_CODE (operands[0]) == MEM 5210 && ! reg_or_0_operand (operands[1], TFmode)) 5211 operands[1] = force_reg (TFmode, operands[1]); 5212}) 5213 5214(define_insn "*movsi" 5215 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m") 5216 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ"))] 5217 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) 5218 && (register_operand (operands[0], SImode) 5219 || reg_or_0_operand (operands[1], SImode))" 5220 "@ 5221 bis $31,%r1,%0 5222 lda %0,%1($31) 5223 ldah %0,%h1($31) 5224 ldl %0,%1 5225 stl %r1,%0" 5226 [(set_attr "type" "ilog,iadd,iadd,ild,ist")]) 5227 5228(define_insn "*movsi_nt_vms" 5229 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m") 5230 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ"))] 5231 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS) 5232 && (register_operand (operands[0], SImode) 5233 || reg_or_0_operand (operands[1], SImode))" 5234 "@ 5235 bis $31,%1,%0 5236 lda %0,%1 5237 ldah %0,%h1 5238 lda %0,%1 5239 ldl %0,%1 5240 stl %r1,%0" 5241 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist")]) 5242 5243(define_insn "*movhi_nobwx" 5244 [(set (match_operand:HI 0 "register_operand" "=r,r") 5245 (match_operand:HI 1 "input_operand" "rJ,n"))] 5246 "! TARGET_BWX 5247 && (register_operand (operands[0], HImode) 5248 || register_operand (operands[1], HImode))" 5249 "@ 5250 bis $31,%r1,%0 5251 lda %0,%L1($31)" 5252 [(set_attr "type" "ilog,iadd")]) 5253 5254(define_insn "*movhi_bwx" 5255 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") 5256 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))] 5257 "TARGET_BWX 5258 && (register_operand (operands[0], HImode) 5259 || reg_or_0_operand (operands[1], HImode))" 5260 "@ 5261 bis $31,%r1,%0 5262 lda %0,%L1($31) 5263 ldwu %0,%1 5264 stw %r1,%0" 5265 [(set_attr "type" "ilog,iadd,ild,ist")]) 5266 5267(define_insn "*movqi_nobwx" 5268 [(set (match_operand:QI 0 "register_operand" "=r,r") 5269 (match_operand:QI 1 "input_operand" "rJ,n"))] 5270 "! TARGET_BWX 5271 && (register_operand (operands[0], QImode) 5272 || register_operand (operands[1], QImode))" 5273 "@ 5274 bis $31,%r1,%0 5275 lda %0,%L1($31)" 5276 [(set_attr "type" "ilog,iadd")]) 5277 5278(define_insn "*movqi_bwx" 5279 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m") 5280 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))] 5281 "TARGET_BWX 5282 && (register_operand (operands[0], QImode) 5283 || reg_or_0_operand (operands[1], QImode))" 5284 "@ 5285 bis $31,%r1,%0 5286 lda %0,%L1($31) 5287 ldbu %0,%1 5288 stb %r1,%0" 5289 [(set_attr "type" "ilog,iadd,ild,ist")]) 5290 5291;; We do two major things here: handle mem->mem and construct long 5292;; constants. 5293 5294(define_expand "movsi" 5295 [(set (match_operand:SI 0 "nonimmediate_operand" "") 5296 (match_operand:SI 1 "general_operand" ""))] 5297 "" 5298{ 5299 if (alpha_expand_mov (SImode, operands)) 5300 DONE; 5301}) 5302 5303;; Split a load of a large constant into the appropriate two-insn 5304;; sequence. 5305 5306(define_split 5307 [(set (match_operand:SI 0 "register_operand" "") 5308 (match_operand:SI 1 "const_int_operand" ""))] 5309 "! add_operand (operands[1], SImode)" 5310 [(set (match_dup 0) (match_dup 2)) 5311 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))] 5312{ 5313 rtx tem 5314 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2); 5315 5316 if (tem == operands[0]) 5317 DONE; 5318 else 5319 FAIL; 5320}) 5321 5322;; Split the load of an address into a four-insn sequence on Unicos/Mk. 5323;; Always generate a REG_EQUAL note for the last instruction to facilitate 5324;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL 5325;; notes and update LABEL_NUSES because this is not done automatically. 5326;; Labels may be incorrectly deleted if we don't do this. 5327;; 5328;; Describing what the individual instructions do correctly is too complicated 5329;; so use UNSPECs for each of the three parts of an address. 5330 5331(define_split 5332 [(set (match_operand:DI 0 "register_operand" "") 5333 (match_operand:DI 1 "symbolic_operand" ""))] 5334 "TARGET_ABI_UNICOSMK && reload_completed" 5335 [(const_int 0)] 5336{ 5337 rtx insn1, insn2, insn3; 5338 5339 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1])); 5340 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32))); 5341 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1])); 5342 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1])); 5343 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1], 5344 REG_NOTES (insn3)); 5345 if (GET_CODE (operands[1]) == LABEL_REF) 5346 { 5347 rtx label; 5348 5349 label = XEXP (operands[1], 0); 5350 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label, 5351 REG_NOTES (insn1)); 5352 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label, 5353 REG_NOTES (insn2)); 5354 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label, 5355 REG_NOTES (insn3)); 5356 LABEL_NUSES (label) += 3; 5357 } 5358 DONE; 5359}) 5360 5361;; Instructions for loading the three parts of an address on Unicos/Mk. 5362 5363(define_insn "umk_laum" 5364 [(set (match_operand:DI 0 "register_operand" "=r") 5365 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 5366 UNSPEC_UMK_LAUM))] 5367 "TARGET_ABI_UNICOSMK" 5368 "laum %r0,%t1($31)" 5369 [(set_attr "type" "iadd")]) 5370 5371(define_insn "umk_lalm" 5372 [(set (match_operand:DI 0 "register_operand" "=r") 5373 (plus:DI (match_operand:DI 1 "register_operand" "r") 5374 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 5375 UNSPEC_UMK_LALM)))] 5376 "TARGET_ABI_UNICOSMK" 5377 "lalm %r0,%t2(%r1)" 5378 [(set_attr "type" "iadd")]) 5379 5380(define_insn "umk_lal" 5381 [(set (match_operand:DI 0 "register_operand" "=r") 5382 (plus:DI (match_operand:DI 1 "register_operand" "r") 5383 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 5384 UNSPEC_UMK_LAL)))] 5385 "TARGET_ABI_UNICOSMK" 5386 "lal %r0,%t2(%r1)" 5387 [(set_attr "type" "iadd")]) 5388 5389;; Add a new call information word to the current function's list of CIWs 5390;; and load its index into $25. Doing it here ensures that the CIW will be 5391;; associated with the correct function even in the presence of inlining. 5392 5393(define_insn "*umk_load_ciw" 5394 [(set (reg:DI 25) 5395 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))] 5396 "TARGET_ABI_UNICOSMK" 5397{ 5398 operands[0] = unicosmk_add_call_info_word (operands[0]); 5399 return "lda $25,%0"; 5400} 5401 [(set_attr "type" "iadd")]) 5402 5403(define_insn "*movdi_er_low_l" 5404 [(set (match_operand:DI 0 "register_operand" "=r") 5405 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 5406 (match_operand:DI 2 "local_symbolic_operand" "")))] 5407 "TARGET_EXPLICIT_RELOCS" 5408{ 5409 if (true_regnum (operands[1]) == 29) 5410 return "lda %0,%2(%1)\t\t!gprel"; 5411 else 5412 return "lda %0,%2(%1)\t\t!gprellow"; 5413} 5414 [(set_attr "usegp" "yes")]) 5415 5416(define_split 5417 [(set (match_operand:DI 0 "register_operand" "") 5418 (match_operand:DI 1 "small_symbolic_operand" ""))] 5419 "TARGET_EXPLICIT_RELOCS && reload_completed" 5420 [(set (match_dup 0) 5421 (lo_sum:DI (match_dup 2) (match_dup 1)))] 5422 "operands[2] = pic_offset_table_rtx;") 5423 5424(define_split 5425 [(set (match_operand:DI 0 "register_operand" "") 5426 (match_operand:DI 1 "local_symbolic_operand" ""))] 5427 "TARGET_EXPLICIT_RELOCS && reload_completed" 5428 [(set (match_dup 0) 5429 (plus:DI (match_dup 2) (high:DI (match_dup 1)))) 5430 (set (match_dup 0) 5431 (lo_sum:DI (match_dup 0) (match_dup 1)))] 5432 "operands[2] = pic_offset_table_rtx;") 5433 5434(define_split 5435 [(match_operand 0 "some_small_symbolic_operand" "")] 5436 "TARGET_EXPLICIT_RELOCS && reload_completed" 5437 [(match_dup 0)] 5438 "operands[0] = split_small_symbolic_operand (operands[0]);") 5439 5440;; Accepts any symbolic, not just global, since function calls that 5441;; don't go via bsr still use !literal in hopes of linker relaxation. 5442(define_insn "movdi_er_high_g" 5443 [(set (match_operand:DI 0 "register_operand" "=r") 5444 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 5445 (match_operand:DI 2 "symbolic_operand" "") 5446 (match_operand 3 "const_int_operand" "")] 5447 UNSPEC_LITERAL))] 5448 "TARGET_EXPLICIT_RELOCS" 5449{ 5450 if (INTVAL (operands[3]) == 0) 5451 return "ldq %0,%2(%1)\t\t!literal"; 5452 else 5453 return "ldq %0,%2(%1)\t\t!literal!%3"; 5454} 5455 [(set_attr "type" "ldsym")]) 5456 5457(define_split 5458 [(set (match_operand:DI 0 "register_operand" "") 5459 (match_operand:DI 1 "global_symbolic_operand" ""))] 5460 "TARGET_EXPLICIT_RELOCS && reload_completed" 5461 [(set (match_dup 0) 5462 (unspec:DI [(match_dup 2) 5463 (match_dup 1) 5464 (const_int 0)] UNSPEC_LITERAL))] 5465 "operands[2] = pic_offset_table_rtx;") 5466 5467;; With RTL inlining, at -O3, rtl is generated, stored, then actually 5468;; compiled at the end of compilation. In the meantime, someone can 5469;; re-encode-section-info on some symbol changing it e.g. from global 5470;; to local-not-small. If this happens, we'd have emitted a plain 5471;; load rather than a high+losum load and not recognize the insn. 5472;; 5473;; So if rtl inlining is in effect, we delay the global/not-global 5474;; decision until rest_of_compilation by wrapping it in an UNSPEC_SYMBOL. 5475 5476(define_insn_and_split "movdi_er_maybe_g" 5477 [(set (match_operand:DI 0 "register_operand" "=r") 5478 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 5479 UNSPEC_SYMBOL))] 5480 "TARGET_EXPLICIT_RELOCS && flag_inline_functions" 5481 "#" 5482 "" 5483 [(set (match_dup 0) (match_dup 1))] 5484{ 5485 if (local_symbolic_operand (operands[1], Pmode) 5486 && !small_symbolic_operand (operands[1], Pmode)) 5487 { 5488 rtx subtarget = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode); 5489 rtx tmp; 5490 5491 tmp = gen_rtx_HIGH (Pmode, operands[1]); 5492 if (reload_completed) 5493 tmp = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmp); 5494 emit_insn (gen_rtx_SET (VOIDmode, subtarget, tmp)); 5495 5496 tmp = gen_rtx_LO_SUM (Pmode, subtarget, operands[1]); 5497 emit_insn (gen_rtx_SET (VOIDmode, operands[0], tmp)); 5498 DONE; 5499 } 5500}) 5501 5502(define_insn "movdi_er_tlsgd" 5503 [(set (match_operand:DI 0 "register_operand" "=r") 5504 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 5505 (match_operand:DI 2 "symbolic_operand" "") 5506 (match_operand 3 "const_int_operand" "")] 5507 UNSPEC_TLSGD))] 5508 "HAVE_AS_TLS" 5509{ 5510 if (INTVAL (operands[3]) == 0) 5511 return "lda %0,%2(%1)\t\t!tlsgd"; 5512 else 5513 return "lda %0,%2(%1)\t\t!tlsgd!%3"; 5514}) 5515 5516(define_insn "movdi_er_tlsldm" 5517 [(set (match_operand:DI 0 "register_operand" "=r") 5518 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 5519 (match_operand 2 "const_int_operand" "")] 5520 UNSPEC_TLSLDM))] 5521 "HAVE_AS_TLS" 5522{ 5523 if (INTVAL (operands[2]) == 0) 5524 return "lda %0,%&(%1)\t\t!tlsldm"; 5525 else 5526 return "lda %0,%&(%1)\t\t!tlsldm!%2"; 5527}) 5528 5529(define_insn "*movdi_er_gotdtp" 5530 [(set (match_operand:DI 0 "register_operand" "=r") 5531 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 5532 (match_operand:DI 2 "symbolic_operand" "")] 5533 UNSPEC_DTPREL))] 5534 "HAVE_AS_TLS" 5535 "ldq %0,%2(%1)\t\t!gotdtprel" 5536 [(set_attr "type" "ild") 5537 (set_attr "usegp" "yes")]) 5538 5539(define_split 5540 [(set (match_operand:DI 0 "register_operand" "") 5541 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))] 5542 "HAVE_AS_TLS && reload_completed" 5543 [(set (match_dup 0) 5544 (unspec:DI [(match_dup 2) 5545 (match_dup 1)] UNSPEC_DTPREL))] 5546{ 5547 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 5548 operands[2] = pic_offset_table_rtx; 5549}) 5550 5551(define_insn "*movdi_er_gottp" 5552 [(set (match_operand:DI 0 "register_operand" "=r") 5553 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 5554 (match_operand:DI 2 "symbolic_operand" "")] 5555 UNSPEC_TPREL))] 5556 "HAVE_AS_TLS" 5557 "ldq %0,%2(%1)\t\t!gottprel" 5558 [(set_attr "type" "ild") 5559 (set_attr "usegp" "yes")]) 5560 5561(define_split 5562 [(set (match_operand:DI 0 "register_operand" "") 5563 (match_operand:DI 1 "gottp_symbolic_operand" ""))] 5564 "HAVE_AS_TLS && reload_completed" 5565 [(set (match_dup 0) 5566 (unspec:DI [(match_dup 2) 5567 (match_dup 1)] UNSPEC_TPREL))] 5568{ 5569 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 5570 operands[2] = pic_offset_table_rtx; 5571}) 5572 5573(define_insn "*movdi_er_nofix" 5574 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q") 5575 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))] 5576 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX 5577 && (register_operand (operands[0], DImode) 5578 || reg_or_0_operand (operands[1], DImode))" 5579 "@ 5580 mov %r1,%0 5581 lda %0,%1($31) 5582 ldah %0,%h1($31) 5583 # 5584 # 5585 ldq%A1 %0,%1 5586 stq%A0 %r1,%0 5587 fmov %R1,%0 5588 ldt %0,%1 5589 stt %R1,%0" 5590 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst") 5591 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*")]) 5592 5593;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should 5594;; have been split up by the rules above but we shouldn't reject the 5595;; possibility of them getting through. 5596 5597(define_insn "*movdi_nofix" 5598 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q") 5599 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))] 5600 "! TARGET_FIX 5601 && (register_operand (operands[0], DImode) 5602 || reg_or_0_operand (operands[1], DImode))" 5603 "@ 5604 bis $31,%r1,%0 5605 lda %0,%1($31) 5606 ldah %0,%h1($31) 5607 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0) 5608 lda %0,%1 5609 ldq%A1 %0,%1 5610 stq%A0 %r1,%0 5611 cpys %R1,%R1,%0 5612 ldt %0,%1 5613 stt %R1,%0" 5614 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst") 5615 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")]) 5616 5617(define_insn "*movdi_er_fix" 5618 [(set (match_operand:DI 0 "nonimmediate_operand" 5619 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f") 5620 (match_operand:DI 1 "input_operand" 5621 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))] 5622 "TARGET_EXPLICIT_RELOCS && TARGET_FIX 5623 && (register_operand (operands[0], DImode) 5624 || reg_or_0_operand (operands[1], DImode))" 5625 "@ 5626 mov %r1,%0 5627 lda %0,%1($31) 5628 ldah %0,%h1($31) 5629 # 5630 # 5631 ldq%A1 %0,%1 5632 stq%A0 %r1,%0 5633 fmov %R1,%0 5634 ldt %0,%1 5635 stt %R1,%0 5636 ftoit %1,%0 5637 itoft %1,%0" 5638 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof") 5639 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*")]) 5640 5641(define_insn "*movdi_fix" 5642 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f") 5643 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))] 5644 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX 5645 && (register_operand (operands[0], DImode) 5646 || reg_or_0_operand (operands[1], DImode))" 5647 "@ 5648 bis $31,%r1,%0 5649 lda %0,%1($31) 5650 ldah %0,%h1($31) 5651 lda %0,%1 5652 ldq%A1 %0,%1 5653 stq%A0 %r1,%0 5654 cpys %R1,%R1,%0 5655 ldt %0,%1 5656 stt %R1,%0 5657 ftoit %1,%0 5658 itoft %1,%0" 5659 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")]) 5660 5661;; VMS needs to set up "vms_base_regno" for unwinding. This move 5662;; often appears dead to the life analysis code, at which point we 5663;; abort for emitting dead prologue instructions. Force this live. 5664 5665(define_insn "force_movdi" 5666 [(set (match_operand:DI 0 "register_operand" "=r") 5667 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")] 5668 UNSPECV_FORCE_MOV))] 5669 "" 5670 "mov %1,%0" 5671 [(set_attr "type" "ilog")]) 5672 5673;; We do three major things here: handle mem->mem, put 64-bit constants in 5674;; memory, and construct long 32-bit constants. 5675 5676(define_expand "movdi" 5677 [(set (match_operand:DI 0 "nonimmediate_operand" "") 5678 (match_operand:DI 1 "general_operand" ""))] 5679 "" 5680{ 5681 if (alpha_expand_mov (DImode, operands)) 5682 DONE; 5683}) 5684 5685;; Split a load of a large constant into the appropriate two-insn 5686;; sequence. 5687 5688(define_split 5689 [(set (match_operand:DI 0 "register_operand" "") 5690 (match_operand:DI 1 "const_int_operand" ""))] 5691 "! add_operand (operands[1], DImode)" 5692 [(set (match_dup 0) (match_dup 2)) 5693 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 5694{ 5695 rtx tem 5696 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2); 5697 5698 if (tem == operands[0]) 5699 DONE; 5700 else 5701 FAIL; 5702}) 5703 5704;; These are the partial-word cases. 5705;; 5706;; First we have the code to load an aligned word. Operand 0 is the register 5707;; in which to place the result. It's mode is QImode or HImode. Operand 1 5708;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the 5709;; number of bits within the word that the value is. Operand 3 is an SImode 5710;; scratch register. If operand 0 is a hard register, operand 3 may be the 5711;; same register. It is allowed to conflict with operand 1 as well. 5712 5713(define_expand "aligned_loadqi" 5714 [(set (match_operand:SI 3 "register_operand" "") 5715 (match_operand:SI 1 "memory_operand" "")) 5716 (set (match_operand:DI 0 "register_operand" "") 5717 (zero_extract:DI (subreg:DI (match_dup 3) 0) 5718 (const_int 8) 5719 (match_operand:DI 2 "const_int_operand" "")))] 5720 5721 "" 5722 "") 5723 5724(define_expand "aligned_loadhi" 5725 [(set (match_operand:SI 3 "register_operand" "") 5726 (match_operand:SI 1 "memory_operand" "")) 5727 (set (match_operand:DI 0 "register_operand" "") 5728 (zero_extract:DI (subreg:DI (match_dup 3) 0) 5729 (const_int 16) 5730 (match_operand:DI 2 "const_int_operand" "")))] 5731 5732 "" 5733 "") 5734 5735;; Similar for unaligned loads, where we use the sequence from the 5736;; Alpha Architecture manual. We have to distinguish between little-endian 5737;; and big-endian systems as the sequences are different. 5738;; 5739;; Operand 1 is the address. Operands 2 and 3 are temporaries, where 5740;; operand 3 can overlap the input and output registers. 5741 5742(define_expand "unaligned_loadqi" 5743 [(use (match_operand:DI 0 "register_operand" "")) 5744 (use (match_operand:DI 1 "address_operand" "")) 5745 (use (match_operand:DI 2 "register_operand" "")) 5746 (use (match_operand:DI 3 "register_operand" ""))] 5747 "" 5748{ 5749 if (WORDS_BIG_ENDIAN) 5750 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1], 5751 operands[2], operands[3])); 5752 else 5753 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1], 5754 operands[2], operands[3])); 5755 DONE; 5756}) 5757 5758(define_expand "unaligned_loadqi_le" 5759 [(set (match_operand:DI 2 "register_operand" "") 5760 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "") 5761 (const_int -8)))) 5762 (set (match_operand:DI 3 "register_operand" "") 5763 (match_dup 1)) 5764 (set (match_operand:DI 0 "register_operand" "") 5765 (zero_extract:DI (match_dup 2) 5766 (const_int 8) 5767 (ashift:DI (match_dup 3) (const_int 3))))] 5768 "! WORDS_BIG_ENDIAN" 5769 "") 5770 5771(define_expand "unaligned_loadqi_be" 5772 [(set (match_operand:DI 2 "register_operand" "") 5773 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "") 5774 (const_int -8)))) 5775 (set (match_operand:DI 3 "register_operand" "") 5776 (match_dup 1)) 5777 (set (match_operand:DI 0 "register_operand" "") 5778 (zero_extract:DI (match_dup 2) 5779 (const_int 8) 5780 (minus:DI 5781 (const_int 56) 5782 (ashift:DI (match_dup 3) (const_int 3)))))] 5783 "WORDS_BIG_ENDIAN" 5784 "") 5785 5786(define_expand "unaligned_loadhi" 5787 [(use (match_operand:DI 0 "register_operand" "")) 5788 (use (match_operand:DI 1 "address_operand" "")) 5789 (use (match_operand:DI 2 "register_operand" "")) 5790 (use (match_operand:DI 3 "register_operand" ""))] 5791 "" 5792{ 5793 if (WORDS_BIG_ENDIAN) 5794 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1], 5795 operands[2], operands[3])); 5796 else 5797 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1], 5798 operands[2], operands[3])); 5799 DONE; 5800}) 5801 5802(define_expand "unaligned_loadhi_le" 5803 [(set (match_operand:DI 2 "register_operand" "") 5804 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "") 5805 (const_int -8)))) 5806 (set (match_operand:DI 3 "register_operand" "") 5807 (match_dup 1)) 5808 (set (match_operand:DI 0 "register_operand" "") 5809 (zero_extract:DI (match_dup 2) 5810 (const_int 16) 5811 (ashift:DI (match_dup 3) (const_int 3))))] 5812 "! WORDS_BIG_ENDIAN" 5813 "") 5814 5815(define_expand "unaligned_loadhi_be" 5816 [(set (match_operand:DI 2 "register_operand" "") 5817 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "") 5818 (const_int -8)))) 5819 (set (match_operand:DI 3 "register_operand" "") 5820 (plus:DI (match_dup 1) (const_int 1))) 5821 (set (match_operand:DI 0 "register_operand" "") 5822 (zero_extract:DI (match_dup 2) 5823 (const_int 16) 5824 (minus:DI 5825 (const_int 56) 5826 (ashift:DI (match_dup 3) (const_int 3)))))] 5827 "WORDS_BIG_ENDIAN" 5828 "") 5829 5830;; Storing an aligned byte or word requires two temporaries. Operand 0 is the 5831;; aligned SImode MEM. Operand 1 is the register containing the 5832;; byte or word to store. Operand 2 is the number of bits within the word that 5833;; the value should be placed. Operands 3 and 4 are SImode temporaries. 5834 5835(define_expand "aligned_store" 5836 [(set (match_operand:SI 3 "register_operand" "") 5837 (match_operand:SI 0 "memory_operand" "")) 5838 (set (subreg:DI (match_dup 3) 0) 5839 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5))) 5840 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0) 5841 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" "")) 5842 (match_operand:DI 2 "const_int_operand" ""))) 5843 (set (subreg:DI (match_dup 4) 0) 5844 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0))) 5845 (set (match_dup 0) (match_dup 4))] 5846 "" 5847{ 5848 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1])) 5849 << INTVAL (operands[2]))); 5850}) 5851 5852;; For the unaligned byte and halfword cases, we use code similar to that 5853;; in the ;; Architecture book, but reordered to lower the number of registers 5854;; required. Operand 0 is the address. Operand 1 is the data to store. 5855;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may 5856;; be the same temporary, if desired. If the address is in a register, 5857;; operand 2 can be that register. 5858 5859(define_expand "unaligned_storeqi" 5860 [(use (match_operand:DI 0 "address_operand" "")) 5861 (use (match_operand:QI 1 "register_operand" "")) 5862 (use (match_operand:DI 2 "register_operand" "")) 5863 (use (match_operand:DI 3 "register_operand" "")) 5864 (use (match_operand:DI 4 "register_operand" ""))] 5865 "" 5866{ 5867 if (WORDS_BIG_ENDIAN) 5868 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1], 5869 operands[2], operands[3], 5870 operands[4])); 5871 else 5872 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1], 5873 operands[2], operands[3], 5874 operands[4])); 5875 DONE; 5876}) 5877 5878(define_expand "unaligned_storeqi_le" 5879 [(set (match_operand:DI 3 "register_operand" "") 5880 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "") 5881 (const_int -8)))) 5882 (set (match_operand:DI 2 "register_operand" "") 5883 (match_dup 0)) 5884 (set (match_dup 3) 5885 (and:DI (not:DI (ashift:DI (const_int 255) 5886 (ashift:DI (match_dup 2) (const_int 3)))) 5887 (match_dup 3))) 5888 (set (match_operand:DI 4 "register_operand" "") 5889 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "")) 5890 (ashift:DI (match_dup 2) (const_int 3)))) 5891 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) 5892 (set (mem:DI (and:DI (match_dup 0) (const_int -8))) 5893 (match_dup 4))] 5894 "! WORDS_BIG_ENDIAN" 5895 "") 5896 5897(define_expand "unaligned_storeqi_be" 5898 [(set (match_operand:DI 3 "register_operand" "") 5899 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "") 5900 (const_int -8)))) 5901 (set (match_operand:DI 2 "register_operand" "") 5902 (match_dup 0)) 5903 (set (match_dup 3) 5904 (and:DI (not:DI (ashift:DI (const_int 255) 5905 (minus:DI (const_int 56) 5906 (ashift:DI (match_dup 2) (const_int 3))))) 5907 (match_dup 3))) 5908 (set (match_operand:DI 4 "register_operand" "") 5909 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "")) 5910 (minus:DI (const_int 56) 5911 (ashift:DI (match_dup 2) (const_int 3))))) 5912 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) 5913 (set (mem:DI (and:DI (match_dup 0) (const_int -8))) 5914 (match_dup 4))] 5915 "WORDS_BIG_ENDIAN" 5916 "") 5917 5918(define_expand "unaligned_storehi" 5919 [(use (match_operand:DI 0 "address_operand" "")) 5920 (use (match_operand:HI 1 "register_operand" "")) 5921 (use (match_operand:DI 2 "register_operand" "")) 5922 (use (match_operand:DI 3 "register_operand" "")) 5923 (use (match_operand:DI 4 "register_operand" ""))] 5924 "" 5925{ 5926 if (WORDS_BIG_ENDIAN) 5927 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1], 5928 operands[2], operands[3], 5929 operands[4])); 5930 else 5931 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1], 5932 operands[2], operands[3], 5933 operands[4])); 5934 DONE; 5935}) 5936 5937(define_expand "unaligned_storehi_le" 5938 [(set (match_operand:DI 3 "register_operand" "") 5939 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "") 5940 (const_int -8)))) 5941 (set (match_operand:DI 2 "register_operand" "") 5942 (match_dup 0)) 5943 (set (match_dup 3) 5944 (and:DI (not:DI (ashift:DI (const_int 65535) 5945 (ashift:DI (match_dup 2) (const_int 3)))) 5946 (match_dup 3))) 5947 (set (match_operand:DI 4 "register_operand" "") 5948 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "")) 5949 (ashift:DI (match_dup 2) (const_int 3)))) 5950 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) 5951 (set (mem:DI (and:DI (match_dup 0) (const_int -8))) 5952 (match_dup 4))] 5953 "! WORDS_BIG_ENDIAN" 5954 "") 5955 5956(define_expand "unaligned_storehi_be" 5957 [(set (match_operand:DI 3 "register_operand" "") 5958 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "") 5959 (const_int -8)))) 5960 (set (match_operand:DI 2 "register_operand" "") 5961 (plus:DI (match_dup 0) (const_int 1))) 5962 (set (match_dup 3) 5963 (and:DI (not:DI (ashift:DI 5964 (const_int 65535) 5965 (minus:DI (const_int 56) 5966 (ashift:DI (match_dup 2) (const_int 3))))) 5967 (match_dup 3))) 5968 (set (match_operand:DI 4 "register_operand" "") 5969 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "")) 5970 (minus:DI (const_int 56) 5971 (ashift:DI (match_dup 2) (const_int 3))))) 5972 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) 5973 (set (mem:DI (and:DI (match_dup 0) (const_int -8))) 5974 (match_dup 4))] 5975 "WORDS_BIG_ENDIAN" 5976 "") 5977 5978;; Here are the define_expand's for QI and HI moves that use the above 5979;; patterns. We have the normal sets, plus the ones that need scratch 5980;; registers for reload. 5981 5982(define_expand "movqi" 5983 [(set (match_operand:QI 0 "nonimmediate_operand" "") 5984 (match_operand:QI 1 "general_operand" ""))] 5985 "" 5986{ 5987 if (TARGET_BWX 5988 ? alpha_expand_mov (QImode, operands) 5989 : alpha_expand_mov_nobwx (QImode, operands)) 5990 DONE; 5991}) 5992 5993(define_expand "movhi" 5994 [(set (match_operand:HI 0 "nonimmediate_operand" "") 5995 (match_operand:HI 1 "general_operand" ""))] 5996 "" 5997{ 5998 if (TARGET_BWX 5999 ? alpha_expand_mov (HImode, operands) 6000 : alpha_expand_mov_nobwx (HImode, operands)) 6001 DONE; 6002}) 6003 6004;; Here are the versions for reload. Note that in the unaligned cases 6005;; we know that the operand must not be a pseudo-register because stack 6006;; slots are always aligned references. 6007 6008(define_expand "reload_inqi" 6009 [(parallel [(match_operand:QI 0 "register_operand" "=r") 6010 (match_operand:QI 1 "any_memory_operand" "m") 6011 (match_operand:TI 2 "register_operand" "=&r")])] 6012 "! TARGET_BWX" 6013{ 6014 rtx scratch, seq; 6015 6016 if (aligned_memory_operand (operands[1], QImode)) 6017 { 6018 seq = gen_reload_inqi_help (operands[0], operands[1], 6019 gen_rtx_REG (SImode, REGNO (operands[2]))); 6020 } 6021 else 6022 { 6023 rtx addr; 6024 6025 /* It is possible that one of the registers we got for operands[2] 6026 might coincide with that of operands[0] (which is why we made 6027 it TImode). Pick the other one to use as our scratch. */ 6028 if (REGNO (operands[0]) == REGNO (operands[2])) 6029 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1); 6030 else 6031 scratch = gen_rtx_REG (DImode, REGNO (operands[2])); 6032 6033 addr = get_unaligned_address (operands[1], 0); 6034 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); 6035 seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]); 6036 alpha_set_memflags (seq, operands[1]); 6037 } 6038 emit_insn (seq); 6039 DONE; 6040}) 6041 6042(define_expand "reload_inhi" 6043 [(parallel [(match_operand:HI 0 "register_operand" "=r") 6044 (match_operand:HI 1 "any_memory_operand" "m") 6045 (match_operand:TI 2 "register_operand" "=&r")])] 6046 "! TARGET_BWX" 6047{ 6048 rtx scratch, seq; 6049 6050 if (aligned_memory_operand (operands[1], HImode)) 6051 { 6052 seq = gen_reload_inhi_help (operands[0], operands[1], 6053 gen_rtx_REG (SImode, REGNO (operands[2]))); 6054 } 6055 else 6056 { 6057 rtx addr; 6058 6059 /* It is possible that one of the registers we got for operands[2] 6060 might coincide with that of operands[0] (which is why we made 6061 it TImode). Pick the other one to use as our scratch. */ 6062 if (REGNO (operands[0]) == REGNO (operands[2])) 6063 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1); 6064 else 6065 scratch = gen_rtx_REG (DImode, REGNO (operands[2])); 6066 6067 addr = get_unaligned_address (operands[1], 0); 6068 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); 6069 seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]); 6070 alpha_set_memflags (seq, operands[1]); 6071 } 6072 emit_insn (seq); 6073 DONE; 6074}) 6075 6076(define_expand "reload_outqi" 6077 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m") 6078 (match_operand:QI 1 "register_operand" "r") 6079 (match_operand:TI 2 "register_operand" "=&r")])] 6080 "! TARGET_BWX" 6081{ 6082 if (aligned_memory_operand (operands[0], QImode)) 6083 { 6084 emit_insn (gen_reload_outqi_help 6085 (operands[0], operands[1], 6086 gen_rtx_REG (SImode, REGNO (operands[2])), 6087 gen_rtx_REG (SImode, REGNO (operands[2]) + 1))); 6088 } 6089 else 6090 { 6091 rtx addr = get_unaligned_address (operands[0], 0); 6092 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2])); 6093 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1); 6094 rtx scratch3 = scratch1; 6095 rtx seq; 6096 6097 if (GET_CODE (addr) == REG) 6098 scratch1 = addr; 6099 6100 seq = gen_unaligned_storeqi (addr, operands[1], scratch1, 6101 scratch2, scratch3); 6102 alpha_set_memflags (seq, operands[0]); 6103 emit_insn (seq); 6104 } 6105 DONE; 6106}) 6107 6108(define_expand "reload_outhi" 6109 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m") 6110 (match_operand:HI 1 "register_operand" "r") 6111 (match_operand:TI 2 "register_operand" "=&r")])] 6112 "! TARGET_BWX" 6113{ 6114 if (aligned_memory_operand (operands[0], HImode)) 6115 { 6116 emit_insn (gen_reload_outhi_help 6117 (operands[0], operands[1], 6118 gen_rtx_REG (SImode, REGNO (operands[2])), 6119 gen_rtx_REG (SImode, REGNO (operands[2]) + 1))); 6120 } 6121 else 6122 { 6123 rtx addr = get_unaligned_address (operands[0], 0); 6124 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2])); 6125 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1); 6126 rtx scratch3 = scratch1; 6127 rtx seq; 6128 6129 if (GET_CODE (addr) == REG) 6130 scratch1 = addr; 6131 6132 seq = gen_unaligned_storehi (addr, operands[1], scratch1, 6133 scratch2, scratch3); 6134 alpha_set_memflags (seq, operands[0]); 6135 emit_insn (seq); 6136 } 6137 DONE; 6138}) 6139 6140;; Helpers for the above. The way reload is structured, we can't 6141;; always get a proper address for a stack slot during reload_foo 6142;; expansion, so we must delay our address manipulations until after. 6143 6144(define_insn_and_split "reload_inqi_help" 6145 [(set (match_operand:QI 0 "register_operand" "=r") 6146 (match_operand:QI 1 "memory_operand" "m")) 6147 (clobber (match_operand:SI 2 "register_operand" "=r"))] 6148 "! TARGET_BWX && (reload_in_progress || reload_completed)" 6149 "#" 6150 "! TARGET_BWX && reload_completed" 6151 [(const_int 0)] 6152{ 6153 rtx aligned_mem, bitnum; 6154 get_aligned_mem (operands[1], &aligned_mem, &bitnum); 6155 operands[0] = gen_lowpart (DImode, operands[0]); 6156 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum, 6157 operands[2])); 6158 DONE; 6159}) 6160 6161(define_insn_and_split "reload_inhi_help" 6162 [(set (match_operand:HI 0 "register_operand" "=r") 6163 (match_operand:HI 1 "memory_operand" "m")) 6164 (clobber (match_operand:SI 2 "register_operand" "=r"))] 6165 "! TARGET_BWX && (reload_in_progress || reload_completed)" 6166 "#" 6167 "! TARGET_BWX && reload_completed" 6168 [(const_int 0)] 6169{ 6170 rtx aligned_mem, bitnum; 6171 get_aligned_mem (operands[1], &aligned_mem, &bitnum); 6172 operands[0] = gen_lowpart (DImode, operands[0]); 6173 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum, 6174 operands[2])); 6175 DONE; 6176}) 6177 6178(define_insn_and_split "reload_outqi_help" 6179 [(set (match_operand:QI 0 "memory_operand" "=m") 6180 (match_operand:QI 1 "register_operand" "r")) 6181 (clobber (match_operand:SI 2 "register_operand" "=r")) 6182 (clobber (match_operand:SI 3 "register_operand" "=r"))] 6183 "! TARGET_BWX && (reload_in_progress || reload_completed)" 6184 "#" 6185 "! TARGET_BWX && reload_completed" 6186 [(const_int 0)] 6187{ 6188 rtx aligned_mem, bitnum; 6189 get_aligned_mem (operands[0], &aligned_mem, &bitnum); 6190 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 6191 operands[2], operands[3])); 6192 DONE; 6193}) 6194 6195(define_insn_and_split "reload_outhi_help" 6196 [(set (match_operand:HI 0 "memory_operand" "=m") 6197 (match_operand:HI 1 "register_operand" "r")) 6198 (clobber (match_operand:SI 2 "register_operand" "=r")) 6199 (clobber (match_operand:SI 3 "register_operand" "=r"))] 6200 "! TARGET_BWX && (reload_in_progress || reload_completed)" 6201 "#" 6202 "! TARGET_BWX && reload_completed" 6203 [(const_int 0)] 6204{ 6205 rtx aligned_mem, bitnum; 6206 get_aligned_mem (operands[0], &aligned_mem, &bitnum); 6207 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 6208 operands[2], operands[3])); 6209 DONE; 6210}) 6211 6212;; Vector operations 6213 6214(define_expand "movv8qi" 6215 [(set (match_operand:V8QI 0 "nonimmediate_operand" "") 6216 (match_operand:V8QI 1 "general_operand" ""))] 6217 "" 6218{ 6219 if (alpha_expand_mov (V8QImode, operands)) 6220 DONE; 6221}) 6222 6223(define_insn "*movv8qi_fix" 6224 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f") 6225 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))] 6226 "TARGET_FIX 6227 && (register_operand (operands[0], V8QImode) 6228 || reg_or_0_operand (operands[1], V8QImode))" 6229 "@ 6230 bis $31,%r1,%0 6231 ldq %0,%1 6232 stq %r1,%0 6233 cpys %R1,%R1,%0 6234 ldt %0,%1 6235 stt %R1,%0 6236 ftoit %1,%0 6237 itoft %1,%0" 6238 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")]) 6239 6240(define_insn "*movv8qi_nofix" 6241 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m") 6242 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f"))] 6243 "! TARGET_FIX 6244 && (register_operand (operands[0], V8QImode) 6245 || reg_or_0_operand (operands[1], V8QImode))" 6246 "@ 6247 bis $31,%r1,%0 6248 ldq %0,%1 6249 stq %r1,%0 6250 cpys %R1,%R1,%0 6251 ldt %0,%1 6252 stt %R1,%0" 6253 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")]) 6254 6255(define_expand "movv4hi" 6256 [(set (match_operand:V4HI 0 "nonimmediate_operand" "") 6257 (match_operand:V4HI 1 "general_operand" ""))] 6258 "" 6259{ 6260 if (alpha_expand_mov (V4HImode, operands)) 6261 DONE; 6262}) 6263 6264(define_insn "*movv4hi_fix" 6265 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f") 6266 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))] 6267 "TARGET_FIX 6268 && (register_operand (operands[0], V4HImode) 6269 || reg_or_0_operand (operands[1], V4HImode))" 6270 "@ 6271 bis $31,%r1,%0 6272 ldq %0,%1 6273 stq %r1,%0 6274 cpys %R1,%R1,%0 6275 ldt %0,%1 6276 stt %R1,%0 6277 ftoit %1,%0 6278 itoft %1,%0" 6279 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")]) 6280 6281(define_insn "*movv4hi_nofix" 6282 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m") 6283 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f"))] 6284 "! TARGET_FIX 6285 && (register_operand (operands[0], V4HImode) 6286 || reg_or_0_operand (operands[1], V4HImode))" 6287 "@ 6288 bis $31,%r1,%0 6289 ldq %0,%1 6290 stq %r1,%0 6291 cpys %R1,%R1,%0 6292 ldt %0,%1 6293 stt %R1,%0" 6294 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")]) 6295 6296(define_expand "movv2si" 6297 [(set (match_operand:V2SI 0 "nonimmediate_operand" "") 6298 (match_operand:V2SI 1 "general_operand" ""))] 6299 "" 6300{ 6301 if (alpha_expand_mov (V2SImode, operands)) 6302 DONE; 6303}) 6304 6305(define_insn "*movv2si_fix" 6306 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f") 6307 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))] 6308 "TARGET_FIX 6309 && (register_operand (operands[0], V2SImode) 6310 || reg_or_0_operand (operands[1], V2SImode))" 6311 "@ 6312 bis $31,%r1,%0 6313 ldq %0,%1 6314 stq %r1,%0 6315 cpys %R1,%R1,%0 6316 ldt %0,%1 6317 stt %R1,%0 6318 ftoit %1,%0 6319 itoft %1,%0" 6320 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")]) 6321 6322(define_insn "*movv2si_nofix" 6323 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m") 6324 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f"))] 6325 "! TARGET_FIX 6326 && (register_operand (operands[0], V2SImode) 6327 || reg_or_0_operand (operands[1], V2SImode))" 6328 "@ 6329 bis $31,%r1,%0 6330 ldq %0,%1 6331 stq %r1,%0 6332 cpys %R1,%R1,%0 6333 ldt %0,%1 6334 stt %R1,%0" 6335 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")]) 6336 6337(define_insn "uminv8qi3" 6338 [(set (match_operand:V8QI 0 "register_operand" "=r") 6339 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 6340 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))] 6341 "TARGET_MAX" 6342 "minub8 %r1,%r2,%0" 6343 [(set_attr "type" "mvi")]) 6344 6345(define_insn "sminv8qi3" 6346 [(set (match_operand:V8QI 0 "register_operand" "=r") 6347 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 6348 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))] 6349 "TARGET_MAX" 6350 "minsb8 %r1,%r2,%0" 6351 [(set_attr "type" "mvi")]) 6352 6353(define_insn "uminv4hi3" 6354 [(set (match_operand:V4HI 0 "register_operand" "=r") 6355 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW") 6356 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))] 6357 "TARGET_MAX" 6358 "minuw4 %r1,%r2,%0" 6359 [(set_attr "type" "mvi")]) 6360 6361(define_insn "sminv4hi3" 6362 [(set (match_operand:V4HI 0 "register_operand" "=r") 6363 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW") 6364 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))] 6365 "TARGET_MAX" 6366 "minsw4 %r1,%r2,%0" 6367 [(set_attr "type" "mvi")]) 6368 6369(define_insn "umaxv8qi3" 6370 [(set (match_operand:V8QI 0 "register_operand" "=r") 6371 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 6372 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))] 6373 "TARGET_MAX" 6374 "maxub8 %r1,%r2,%0" 6375 [(set_attr "type" "mvi")]) 6376 6377(define_insn "smaxv8qi3" 6378 [(set (match_operand:V8QI 0 "register_operand" "=r") 6379 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 6380 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))] 6381 "TARGET_MAX" 6382 "maxsb8 %r1,%r2,%0" 6383 [(set_attr "type" "mvi")]) 6384 6385(define_insn "umaxv4hi3" 6386 [(set (match_operand:V4HI 0 "register_operand" "=r") 6387 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW") 6388 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))] 6389 "TARGET_MAX" 6390 "maxuw4 %r1,%r2,%0" 6391 [(set_attr "type" "mvi")]) 6392 6393(define_insn "smaxv4hi3" 6394 [(set (match_operand:V4HI 0 "register_operand" "=r") 6395 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW") 6396 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))] 6397 "TARGET_MAX" 6398 "maxsw4 %r1,%r2,%0" 6399 [(set_attr "type" "mvi")]) 6400 6401;; Bit field extract patterns which use ext[wlq][lh] 6402 6403(define_expand "extv" 6404 [(set (match_operand:DI 0 "register_operand" "") 6405 (sign_extract:DI (match_operand:QI 1 "memory_operand" "") 6406 (match_operand:DI 2 "immediate_operand" "") 6407 (match_operand:DI 3 "immediate_operand" "")))] 6408 "" 6409{ 6410 int ofs; 6411 6412 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 6413 if (INTVAL (operands[3]) % 8 != 0 6414 || (INTVAL (operands[2]) != 16 6415 && INTVAL (operands[2]) != 32 6416 && INTVAL (operands[2]) != 64)) 6417 FAIL; 6418 6419 /* From mips.md: extract_bit_field doesn't verify that our source 6420 matches the predicate, so we force it to be a MEM here. */ 6421 if (GET_CODE (operands[1]) != MEM) 6422 FAIL; 6423 6424 /* The bit number is relative to the mode of operand 1 which is 6425 usually QImode (this might actually be a bug in expmed.c). Note 6426 that the bit number is negative in big-endian mode in this case. 6427 We have to convert that to the offset. */ 6428 if (WORDS_BIG_ENDIAN) 6429 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1])) 6430 - INTVAL (operands[2]) - INTVAL (operands[3]); 6431 else 6432 ofs = INTVAL (operands[3]); 6433 6434 ofs = ofs / 8; 6435 6436 alpha_expand_unaligned_load (operands[0], operands[1], 6437 INTVAL (operands[2]) / 8, 6438 ofs, 1); 6439 DONE; 6440}) 6441 6442(define_expand "extzv" 6443 [(set (match_operand:DI 0 "register_operand" "") 6444 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "") 6445 (match_operand:DI 2 "immediate_operand" "") 6446 (match_operand:DI 3 "immediate_operand" "")))] 6447 "" 6448{ 6449 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 6450 if (INTVAL (operands[3]) % 8 != 0 6451 || (INTVAL (operands[2]) != 8 6452 && INTVAL (operands[2]) != 16 6453 && INTVAL (operands[2]) != 32 6454 && INTVAL (operands[2]) != 64)) 6455 FAIL; 6456 6457 if (GET_CODE (operands[1]) == MEM) 6458 { 6459 int ofs; 6460 6461 /* Fail 8 bit fields, falling back on a simple byte load. */ 6462 if (INTVAL (operands[2]) == 8) 6463 FAIL; 6464 6465 /* The bit number is relative to the mode of operand 1 which is 6466 usually QImode (this might actually be a bug in expmed.c). Note 6467 that the bit number is negative in big-endian mode in this case. 6468 We have to convert that to the offset. */ 6469 if (WORDS_BIG_ENDIAN) 6470 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1])) 6471 - INTVAL (operands[2]) - INTVAL (operands[3]); 6472 else 6473 ofs = INTVAL (operands[3]); 6474 6475 ofs = ofs / 8; 6476 6477 alpha_expand_unaligned_load (operands[0], operands[1], 6478 INTVAL (operands[2]) / 8, 6479 ofs, 0); 6480 DONE; 6481 } 6482}) 6483 6484(define_expand "insv" 6485 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "") 6486 (match_operand:DI 1 "immediate_operand" "") 6487 (match_operand:DI 2 "immediate_operand" "")) 6488 (match_operand:DI 3 "register_operand" ""))] 6489 "" 6490{ 6491 int ofs; 6492 6493 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 6494 if (INTVAL (operands[2]) % 8 != 0 6495 || (INTVAL (operands[1]) != 16 6496 && INTVAL (operands[1]) != 32 6497 && INTVAL (operands[1]) != 64)) 6498 FAIL; 6499 6500 /* From mips.md: store_bit_field doesn't verify that our source 6501 matches the predicate, so we force it to be a MEM here. */ 6502 if (GET_CODE (operands[0]) != MEM) 6503 FAIL; 6504 6505 /* The bit number is relative to the mode of operand 1 which is 6506 usually QImode (this might actually be a bug in expmed.c). Note 6507 that the bit number is negative in big-endian mode in this case. 6508 We have to convert that to the offset. */ 6509 if (WORDS_BIG_ENDIAN) 6510 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0])) 6511 - INTVAL (operands[1]) - INTVAL (operands[2]); 6512 else 6513 ofs = INTVAL (operands[2]); 6514 6515 ofs = ofs / 8; 6516 6517 alpha_expand_unaligned_store (operands[0], operands[3], 6518 INTVAL (operands[1]) / 8, ofs); 6519 DONE; 6520}) 6521 6522;; Block move/clear, see alpha.c for more details. 6523;; Argument 0 is the destination 6524;; Argument 1 is the source 6525;; Argument 2 is the length 6526;; Argument 3 is the alignment 6527 6528(define_expand "movstrqi" 6529 [(parallel [(set (match_operand:BLK 0 "memory_operand" "") 6530 (match_operand:BLK 1 "memory_operand" "")) 6531 (use (match_operand:DI 2 "immediate_operand" "")) 6532 (use (match_operand:DI 3 "immediate_operand" ""))])] 6533 "" 6534{ 6535 if (alpha_expand_block_move (operands)) 6536 DONE; 6537 else 6538 FAIL; 6539}) 6540 6541(define_expand "movstrdi" 6542 [(parallel [(set (match_operand:BLK 0 "memory_operand" "") 6543 (match_operand:BLK 1 "memory_operand" "")) 6544 (use (match_operand:DI 2 "immediate_operand" "")) 6545 (use (match_operand:DI 3 "immediate_operand" "")) 6546 (use (match_dup 4)) 6547 (clobber (reg:DI 25)) 6548 (clobber (reg:DI 16)) 6549 (clobber (reg:DI 17)) 6550 (clobber (reg:DI 18)) 6551 (clobber (reg:DI 19)) 6552 (clobber (reg:DI 20)) 6553 (clobber (reg:DI 26)) 6554 (clobber (reg:DI 27))])] 6555 "TARGET_ABI_OPEN_VMS" 6556{ 6557 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE"); 6558 alpha_need_linkage (XSTR (operands[4], 0), 0); 6559}) 6560 6561(define_insn "*movstrdi_1" 6562 [(set (match_operand:BLK 0 "memory_operand" "=m,=m") 6563 (match_operand:BLK 1 "memory_operand" "m,m")) 6564 (use (match_operand:DI 2 "nonmemory_operand" "r,i")) 6565 (use (match_operand:DI 3 "immediate_operand" "")) 6566 (use (match_operand:DI 4 "call_operand" "i,i")) 6567 (clobber (reg:DI 25)) 6568 (clobber (reg:DI 16)) 6569 (clobber (reg:DI 17)) 6570 (clobber (reg:DI 18)) 6571 (clobber (reg:DI 19)) 6572 (clobber (reg:DI 20)) 6573 (clobber (reg:DI 26)) 6574 (clobber (reg:DI 27))] 6575 "TARGET_ABI_OPEN_VMS" 6576{ 6577 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1); 6578 switch (which_alternative) 6579 { 6580 case 0: 6581 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 6582 case 1: 6583 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 6584 default: 6585 abort(); 6586 } 6587} 6588 [(set_attr "type" "multi") 6589 (set_attr "length" "28")]) 6590 6591(define_expand "clrstrqi" 6592 [(parallel [(set (match_operand:BLK 0 "memory_operand" "") 6593 (const_int 0)) 6594 (use (match_operand:DI 1 "immediate_operand" "")) 6595 (use (match_operand:DI 2 "immediate_operand" ""))])] 6596 "" 6597{ 6598 if (alpha_expand_block_clear (operands)) 6599 DONE; 6600 else 6601 FAIL; 6602}) 6603 6604(define_expand "clrstrdi" 6605 [(parallel [(set (match_operand:BLK 0 "memory_operand" "") 6606 (const_int 0)) 6607 (use (match_operand:DI 1 "immediate_operand" "")) 6608 (use (match_operand:DI 2 "immediate_operand" "")) 6609 (use (match_dup 3)) 6610 (clobber (reg:DI 25)) 6611 (clobber (reg:DI 16)) 6612 (clobber (reg:DI 17)) 6613 (clobber (reg:DI 26)) 6614 (clobber (reg:DI 27))])] 6615 "TARGET_ABI_OPEN_VMS" 6616{ 6617 operands[3] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO"); 6618 alpha_need_linkage (XSTR (operands[3], 0), 0); 6619}) 6620 6621(define_insn "*clrstrdi_1" 6622 [(set (match_operand:BLK 0 "memory_operand" "=m,=m") 6623 (const_int 0)) 6624 (use (match_operand:DI 1 "nonmemory_operand" "r,i")) 6625 (use (match_operand:DI 2 "immediate_operand" "")) 6626 (use (match_operand:DI 3 "call_operand" "i,i")) 6627 (clobber (reg:DI 25)) 6628 (clobber (reg:DI 16)) 6629 (clobber (reg:DI 17)) 6630 (clobber (reg:DI 26)) 6631 (clobber (reg:DI 27))] 6632 "TARGET_ABI_OPEN_VMS" 6633{ 6634 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1); 6635 switch (which_alternative) 6636 { 6637 case 0: 6638 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 6639 case 1: 6640 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 6641 default: 6642 abort(); 6643 } 6644} 6645 [(set_attr "type" "multi") 6646 (set_attr "length" "24")]) 6647 6648 6649;; Subroutine of stack space allocation. Perform a stack probe. 6650(define_expand "probe_stack" 6651 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))] 6652 "" 6653{ 6654 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 6655 INTVAL (operands[0]))); 6656 MEM_VOLATILE_P (operands[1]) = 1; 6657 6658 operands[0] = const0_rtx; 6659}) 6660 6661;; This is how we allocate stack space. If we are allocating a 6662;; constant amount of space and we know it is less than 4096 6663;; bytes, we need do nothing. 6664;; 6665;; If it is more than 4096 bytes, we need to probe the stack 6666;; periodically. 6667(define_expand "allocate_stack" 6668 [(set (reg:DI 30) 6669 (plus:DI (reg:DI 30) 6670 (match_operand:DI 1 "reg_or_cint_operand" ""))) 6671 (set (match_operand:DI 0 "register_operand" "=r") 6672 (match_dup 2))] 6673 "" 6674{ 6675 if (GET_CODE (operands[1]) == CONST_INT 6676 && INTVAL (operands[1]) < 32768) 6677 { 6678 if (INTVAL (operands[1]) >= 4096) 6679 { 6680 /* We do this the same way as in the prologue and generate explicit 6681 probes. Then we update the stack by the constant. */ 6682 6683 int probed = 4096; 6684 6685 emit_insn (gen_probe_stack (GEN_INT (- probed))); 6686 while (probed + 8192 < INTVAL (operands[1])) 6687 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192)))); 6688 6689 if (probed + 4096 < INTVAL (operands[1])) 6690 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1])))); 6691 } 6692 6693 operands[1] = GEN_INT (- INTVAL (operands[1])); 6694 operands[2] = virtual_stack_dynamic_rtx; 6695 } 6696 else 6697 { 6698 rtx out_label = 0; 6699 rtx loop_label = gen_label_rtx (); 6700 rtx want = gen_reg_rtx (Pmode); 6701 rtx tmp = gen_reg_rtx (Pmode); 6702 rtx memref; 6703 6704 emit_insn (gen_subdi3 (want, stack_pointer_rtx, 6705 force_reg (Pmode, operands[1]))); 6706 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096))); 6707 6708 if (GET_CODE (operands[1]) != CONST_INT) 6709 { 6710 out_label = gen_label_rtx (); 6711 emit_insn (gen_cmpdi (want, tmp)); 6712 emit_jump_insn (gen_bgeu (out_label)); 6713 } 6714 6715 emit_label (loop_label); 6716 memref = gen_rtx_MEM (DImode, tmp); 6717 MEM_VOLATILE_P (memref) = 1; 6718 emit_move_insn (memref, const0_rtx); 6719 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192))); 6720 emit_insn (gen_cmpdi (tmp, want)); 6721 emit_jump_insn (gen_bgtu (loop_label)); 6722 6723 memref = gen_rtx_MEM (DImode, want); 6724 MEM_VOLATILE_P (memref) = 1; 6725 emit_move_insn (memref, const0_rtx); 6726 6727 if (out_label) 6728 emit_label (out_label); 6729 6730 emit_move_insn (stack_pointer_rtx, want); 6731 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 6732 DONE; 6733 } 6734}) 6735 6736;; This is used by alpha_expand_prolog to do the same thing as above, 6737;; except we cannot at that time generate new basic blocks, so we hide 6738;; the loop in this one insn. 6739 6740(define_insn "prologue_stack_probe_loop" 6741 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r") 6742 (match_operand:DI 1 "register_operand" "r")] 6743 UNSPECV_PSPL)] 6744 "" 6745{ 6746 operands[2] = gen_label_rtx (); 6747 (*targetm.asm_out.internal_label) (asm_out_file, "L", 6748 CODE_LABEL_NUMBER (operands[2])); 6749 6750 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2"; 6751} 6752 [(set_attr "length" "16") 6753 (set_attr "type" "multi")]) 6754 6755(define_expand "prologue" 6756 [(clobber (const_int 0))] 6757 "" 6758{ 6759 alpha_expand_prologue (); 6760 DONE; 6761}) 6762 6763;; These take care of emitting the ldgp insn in the prologue. This will be 6764;; an lda/ldah pair and we want to align them properly. So we have two 6765;; unspec_volatile insns, the first of which emits the ldgp assembler macro 6766;; and the second of which emits nothing. However, both are marked as type 6767;; IADD (the default) so the alignment code in alpha.c does the right thing 6768;; with them. 6769 6770(define_expand "prologue_ldgp" 6771 [(set (match_dup 0) 6772 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 6773 (set (match_dup 0) 6774 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))] 6775 "" 6776{ 6777 operands[0] = pic_offset_table_rtx; 6778 operands[1] = gen_rtx_REG (Pmode, 27); 6779 operands[2] = (TARGET_EXPLICIT_RELOCS 6780 ? GEN_INT (alpha_next_sequence_number++) 6781 : const0_rtx); 6782}) 6783 6784(define_insn "*ldgp_er_1" 6785 [(set (match_operand:DI 0 "register_operand" "=r") 6786 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 6787 (match_operand 2 "const_int_operand" "")] 6788 UNSPECV_LDGP1))] 6789 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6790 "ldah %0,0(%1)\t\t!gpdisp!%2" 6791 [(set_attr "cannot_copy" "true")]) 6792 6793(define_insn "*ldgp_er_2" 6794 [(set (match_operand:DI 0 "register_operand" "=r") 6795 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 6796 (match_operand 2 "const_int_operand" "")] 6797 UNSPEC_LDGP2))] 6798 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6799 "lda %0,0(%1)\t\t!gpdisp!%2" 6800 [(set_attr "cannot_copy" "true")]) 6801 6802(define_insn "*prologue_ldgp_er_2" 6803 [(set (match_operand:DI 0 "register_operand" "=r") 6804 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 6805 (match_operand 2 "const_int_operand" "")] 6806 UNSPECV_PLDGP2))] 6807 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6808 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:" 6809 [(set_attr "cannot_copy" "true")]) 6810 6811(define_insn "*prologue_ldgp_1" 6812 [(set (match_operand:DI 0 "register_operand" "=r") 6813 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 6814 (match_operand 2 "const_int_operand" "")] 6815 UNSPECV_LDGP1))] 6816 "" 6817 "ldgp %0,0(%1)\n$%~..ng:" 6818 [(set_attr "cannot_copy" "true")]) 6819 6820(define_insn "*prologue_ldgp_2" 6821 [(set (match_operand:DI 0 "register_operand" "=r") 6822 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 6823 (match_operand 2 "const_int_operand" "")] 6824 UNSPECV_PLDGP2))] 6825 "" 6826 "") 6827 6828;; The _mcount profiling hook has special calling conventions, and 6829;; does not clobber all the registers that a normal call would. So 6830;; hide the fact this is a call at all. 6831 6832(define_insn "prologue_mcount" 6833 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)] 6834 "" 6835{ 6836 if (TARGET_EXPLICIT_RELOCS) 6837 /* Note that we cannot use a lituse_jsr reloc, since _mcount 6838 cannot be called via the PLT. */ 6839 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount"; 6840 else 6841 return "lda $28,_mcount\;jsr $28,($28),_mcount"; 6842} 6843 [(set_attr "type" "multi") 6844 (set_attr "length" "8")]) 6845 6846(define_insn "init_fp" 6847 [(set (match_operand:DI 0 "register_operand" "=r") 6848 (match_operand:DI 1 "register_operand" "r")) 6849 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))] 6850 "" 6851 "bis $31,%1,%0") 6852 6853(define_expand "epilogue" 6854 [(return)] 6855 "" 6856{ 6857 alpha_expand_epilogue (); 6858}) 6859 6860(define_expand "sibcall_epilogue" 6861 [(return)] 6862 "TARGET_ABI_OSF" 6863{ 6864 alpha_expand_epilogue (); 6865 DONE; 6866}) 6867 6868(define_expand "builtin_longjmp" 6869 [(use (match_operand:DI 0 "register_operand" "r"))] 6870 "TARGET_ABI_OSF" 6871{ 6872 /* The elements of the buffer are, in order: */ 6873 rtx fp = gen_rtx_MEM (Pmode, operands[0]); 6874 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)); 6875 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16)); 6876 rtx pv = gen_rtx_REG (Pmode, 27); 6877 6878 /* This bit is the same as expand_builtin_longjmp. */ 6879 emit_move_insn (hard_frame_pointer_rtx, fp); 6880 emit_move_insn (pv, lab); 6881 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX); 6882 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx)); 6883 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); 6884 6885 /* Load the label we are jumping through into $27 so that we know 6886 where to look for it when we get back to setjmp's function for 6887 restoring the gp. */ 6888 emit_jump_insn (gen_builtin_longjmp_internal (pv)); 6889 emit_barrier (); 6890 DONE; 6891}) 6892 6893;; This is effectively a copy of indirect_jump, but constrained such 6894;; that register renaming cannot foil our cunning plan with $27. 6895(define_insn "builtin_longjmp_internal" 6896 [(set (pc) 6897 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 6898 UNSPECV_LONGJMP))] 6899 "" 6900 "jmp $31,(%0),0" 6901 [(set_attr "type" "ibr")]) 6902 6903(define_insn "*builtin_setjmp_receiver_er_sl_1" 6904 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)] 6905 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS" 6906 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:") 6907 6908(define_insn "*builtin_setjmp_receiver_er_1" 6909 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)] 6910 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6911 "br $27,$LSJ%=\n$LSJ%=:" 6912 [(set_attr "type" "ibr")]) 6913 6914(define_split 6915 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)] 6916 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 6917 && prev_nonnote_insn (insn) == operands[0]" 6918 [(const_int 0)] 6919 " 6920{ 6921 emit_note (NOTE_INSN_DELETED); 6922 DONE; 6923}") 6924 6925(define_insn "*builtin_setjmp_receiver_1" 6926 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)] 6927 "TARGET_ABI_OSF" 6928 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)" 6929 [(set_attr "length" "12") 6930 (set_attr "type" "multi")]) 6931 6932(define_expand "builtin_setjmp_receiver_er" 6933 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR) 6934 (set (match_dup 1) 6935 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1)) 6936 (set (match_dup 1) 6937 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))] 6938 "" 6939{ 6940 operands[1] = pic_offset_table_rtx; 6941 operands[2] = gen_rtx_REG (Pmode, 27); 6942 operands[3] = GEN_INT (alpha_next_sequence_number++); 6943}) 6944 6945(define_expand "builtin_setjmp_receiver" 6946 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)] 6947 "TARGET_ABI_OSF" 6948{ 6949 if (TARGET_EXPLICIT_RELOCS) 6950 { 6951 emit_insn (gen_builtin_setjmp_receiver_er (operands[0])); 6952 DONE; 6953 } 6954}) 6955 6956(define_expand "exception_receiver_er" 6957 [(set (match_dup 0) 6958 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 6959 (set (match_dup 0) 6960 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))] 6961 "" 6962{ 6963 operands[0] = pic_offset_table_rtx; 6964 operands[1] = gen_rtx_REG (Pmode, 26); 6965 operands[2] = GEN_INT (alpha_next_sequence_number++); 6966}) 6967 6968(define_expand "exception_receiver" 6969 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)] 6970 "TARGET_ABI_OSF" 6971{ 6972 if (TARGET_LD_BUGGY_LDGP) 6973 operands[0] = alpha_gp_save_rtx (); 6974 else if (TARGET_EXPLICIT_RELOCS) 6975 { 6976 emit_insn (gen_exception_receiver_er ()); 6977 DONE; 6978 } 6979 else 6980 operands[0] = const0_rtx; 6981}) 6982 6983(define_insn "*exception_receiver_1" 6984 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)] 6985 "! TARGET_LD_BUGGY_LDGP" 6986 "ldgp $29,0($26)" 6987 [(set_attr "length" "8") 6988 (set_attr "type" "multi")]) 6989 6990(define_insn "*exception_receiver_2" 6991 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)] 6992 "TARGET_LD_BUGGY_LDGP" 6993 "ldq $29,%0" 6994 [(set_attr "type" "ild")]) 6995 6996(define_expand "nonlocal_goto_receiver" 6997 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 6998 (set (reg:DI 27) (mem:DI (reg:DI 29))) 6999 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 7000 (use (reg:DI 27))] 7001 "TARGET_ABI_OPEN_VMS" 7002 "") 7003 7004(define_insn "arg_home" 7005 [(unspec [(const_int 0)] UNSPEC_ARG_HOME) 7006 (use (reg:DI 1)) 7007 (use (reg:DI 25)) 7008 (use (reg:DI 16)) 7009 (use (reg:DI 17)) 7010 (use (reg:DI 18)) 7011 (use (reg:DI 19)) 7012 (use (reg:DI 20)) 7013 (use (reg:DI 21)) 7014 (use (reg:DI 48)) 7015 (use (reg:DI 49)) 7016 (use (reg:DI 50)) 7017 (use (reg:DI 51)) 7018 (use (reg:DI 52)) 7019 (use (reg:DI 53)) 7020 (clobber (mem:BLK (const_int 0))) 7021 (clobber (reg:DI 24)) 7022 (clobber (reg:DI 25)) 7023 (clobber (reg:DI 0))] 7024 "TARGET_ABI_OPEN_VMS" 7025 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS" 7026 [(set_attr "length" "16") 7027 (set_attr "type" "multi")]) 7028 7029;; Load the CIW into r2 for calling __T3E_MISMATCH 7030 7031(define_expand "umk_mismatch_args" 7032 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16)))) 7033 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32)))) 7034 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" "")) 7035 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25) 7036 (const_int 8)) 7037 (match_dup 2))) 7038 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))] 7039 "TARGET_ABI_UNICOSMK" 7040{ 7041 operands[1] = gen_reg_rtx (DImode); 7042 operands[2] = gen_reg_rtx (DImode); 7043 operands[3] = gen_reg_rtx (DImode); 7044}) 7045 7046(define_insn "arg_home_umk" 7047 [(unspec [(const_int 0)] UNSPEC_ARG_HOME) 7048 (use (reg:DI 1)) 7049 (use (reg:DI 2)) 7050 (use (reg:DI 16)) 7051 (use (reg:DI 17)) 7052 (use (reg:DI 18)) 7053 (use (reg:DI 19)) 7054 (use (reg:DI 20)) 7055 (use (reg:DI 21)) 7056 (use (reg:DI 48)) 7057 (use (reg:DI 49)) 7058 (use (reg:DI 50)) 7059 (use (reg:DI 51)) 7060 (use (reg:DI 52)) 7061 (use (reg:DI 53)) 7062 (clobber (mem:BLK (const_int 0))) 7063 (parallel [ 7064 (clobber (reg:DI 22)) 7065 (clobber (reg:DI 23)) 7066 (clobber (reg:DI 24)) 7067 (clobber (reg:DI 0)) 7068 (clobber (reg:DI 1)) 7069 (clobber (reg:DI 2)) 7070 (clobber (reg:DI 3)) 7071 (clobber (reg:DI 4)) 7072 (clobber (reg:DI 5)) 7073 (clobber (reg:DI 6)) 7074 (clobber (reg:DI 7)) 7075 (clobber (reg:DI 8))])] 7076 "TARGET_ABI_UNICOSMK" 7077 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)" 7078 [(set_attr "length" "16") 7079 (set_attr "type" "multi")]) 7080 7081;; Prefetch data. 7082;; 7083;; On EV4, these instructions are nops -- no load occurs. 7084;; 7085;; On EV5, these instructions act as a normal load, and thus can trap 7086;; if the address is invalid. The OS may (or may not) handle this in 7087;; the entMM fault handler and suppress the fault. If so, then this 7088;; has the effect of a read prefetch instruction. 7089;; 7090;; On EV6, these become official prefetch instructions. 7091 7092(define_insn "prefetch" 7093 [(prefetch (match_operand:DI 0 "address_operand" "p") 7094 (match_operand:DI 1 "const_int_operand" "n") 7095 (match_operand:DI 2 "const_int_operand" "n"))] 7096 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6" 7097{ 7098 /* Interpret "no temporal locality" as this data should be evicted once 7099 it is used. The "evict next" alternatives load the data into the cache 7100 and leave the LRU eviction counter pointing to that block. */ 7101 static const char * const alt[2][2] = { 7102 { 7103 "ldq $31,%a0", /* read, evict next */ 7104 "ldl $31,%a0", /* read, evict last */ 7105 }, 7106 { 7107 "ldt $f31,%a0", /* write, evict next */ 7108 "lds $f31,%a0", /* write, evict last */ 7109 } 7110 }; 7111 7112 bool write = INTVAL (operands[1]) != 0; 7113 bool lru = INTVAL (operands[2]) != 0; 7114 7115 return alt[write][lru]; 7116} 7117 [(set_attr "type" "ild")]) 7118 7119;; Close the trap shadow of preceding instructions. This is generated 7120;; by alpha_reorg. 7121 7122(define_insn "trapb" 7123 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)] 7124 "" 7125 "trapb" 7126 [(set_attr "type" "misc")]) 7127 7128;; No-op instructions used by machine-dependent reorg to preserve 7129;; alignment for instruction issue. 7130;; The Unicos/Mk assembler does not support these opcodes. 7131 7132(define_insn "nop" 7133 [(const_int 0)] 7134 "" 7135 "bis $31,$31,$31" 7136 [(set_attr "type" "ilog")]) 7137 7138(define_insn "fnop" 7139 [(const_int 1)] 7140 "TARGET_FP" 7141 "cpys $f31,$f31,$f31" 7142 [(set_attr "type" "fcpys")]) 7143 7144(define_insn "unop" 7145 [(const_int 2)] 7146 "" 7147 "ldq_u $31,0($30)") 7148 7149;; On Unicos/Mk we use a macro for aligning code. 7150 7151(define_insn "realign" 7152 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 7153 UNSPECV_REALIGN)] 7154 "" 7155{ 7156 if (TARGET_ABI_UNICOSMK) 7157 return "gcc@code@align %0"; 7158 else 7159 return ".align %0 #realign"; 7160}) 7161 7162;; Instructions to be emitted from __builtins. 7163 7164(define_insn "builtin_cmpbge" 7165 [(set (match_operand:DI 0 "register_operand" "=r") 7166 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ") 7167 (match_operand:DI 2 "reg_or_8bit_operand" "rI")] 7168 UNSPEC_CMPBGE))] 7169 "" 7170 "cmpbge %r1,%2,%0" 7171 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't 7172 ;; actually differentiate between ILOG and ICMP in the schedule. 7173 [(set_attr "type" "icmp")]) 7174 7175(define_expand "builtin_extbl" 7176 [(match_operand:DI 0 "register_operand" "") 7177 (match_operand:DI 1 "reg_or_0_operand" "") 7178 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7179 "" 7180{ 7181 rtx (*gen) (rtx, rtx, rtx, rtx); 7182 if (WORDS_BIG_ENDIAN) 7183 gen = gen_extxl_be; 7184 else 7185 gen = gen_extxl_le; 7186 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2])); 7187 DONE; 7188}) 7189 7190(define_expand "builtin_extwl" 7191 [(match_operand:DI 0 "register_operand" "") 7192 (match_operand:DI 1 "reg_or_0_operand" "") 7193 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7194 "" 7195{ 7196 rtx (*gen) (rtx, rtx, rtx, rtx); 7197 if (WORDS_BIG_ENDIAN) 7198 gen = gen_extxl_be; 7199 else 7200 gen = gen_extxl_le; 7201 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2])); 7202 DONE; 7203}) 7204 7205(define_expand "builtin_extll" 7206 [(match_operand:DI 0 "register_operand" "") 7207 (match_operand:DI 1 "reg_or_0_operand" "") 7208 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7209 "" 7210{ 7211 rtx (*gen) (rtx, rtx, rtx, rtx); 7212 if (WORDS_BIG_ENDIAN) 7213 gen = gen_extxl_be; 7214 else 7215 gen = gen_extxl_le; 7216 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2])); 7217 DONE; 7218}) 7219 7220(define_expand "builtin_extql" 7221 [(match_operand:DI 0 "register_operand" "") 7222 (match_operand:DI 1 "reg_or_0_operand" "") 7223 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7224 "" 7225{ 7226 rtx (*gen) (rtx, rtx, rtx, rtx); 7227 if (WORDS_BIG_ENDIAN) 7228 gen = gen_extxl_be; 7229 else 7230 gen = gen_extxl_le; 7231 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2])); 7232 DONE; 7233}) 7234 7235(define_expand "builtin_extwh" 7236 [(match_operand:DI 0 "register_operand" "") 7237 (match_operand:DI 1 "reg_or_0_operand" "") 7238 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7239 "" 7240{ 7241 rtx (*gen) (rtx, rtx, rtx); 7242 if (WORDS_BIG_ENDIAN) 7243 gen = gen_extwh_be; 7244 else 7245 gen = gen_extwh_le; 7246 emit_insn ((*gen) (operands[0], operands[1], operands[2])); 7247 DONE; 7248}) 7249 7250(define_expand "builtin_extlh" 7251 [(match_operand:DI 0 "register_operand" "") 7252 (match_operand:DI 1 "reg_or_0_operand" "") 7253 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7254 "" 7255{ 7256 rtx (*gen) (rtx, rtx, rtx); 7257 if (WORDS_BIG_ENDIAN) 7258 gen = gen_extlh_be; 7259 else 7260 gen = gen_extlh_le; 7261 emit_insn ((*gen) (operands[0], operands[1], operands[2])); 7262 DONE; 7263}) 7264 7265(define_expand "builtin_extqh" 7266 [(match_operand:DI 0 "register_operand" "") 7267 (match_operand:DI 1 "reg_or_0_operand" "") 7268 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7269 "" 7270{ 7271 rtx (*gen) (rtx, rtx, rtx); 7272 if (WORDS_BIG_ENDIAN) 7273 gen = gen_extqh_be; 7274 else 7275 gen = gen_extqh_le; 7276 emit_insn ((*gen) (operands[0], operands[1], operands[2])); 7277 DONE; 7278}) 7279 7280(define_expand "builtin_insbl" 7281 [(match_operand:DI 0 "register_operand" "") 7282 (match_operand:DI 1 "reg_or_0_operand" "") 7283 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7284 "" 7285{ 7286 rtx (*gen) (rtx, rtx, rtx); 7287 if (WORDS_BIG_ENDIAN) 7288 gen = gen_insbl_be; 7289 else 7290 gen = gen_insbl_le; 7291 operands[1] = gen_lowpart (QImode, operands[1]); 7292 emit_insn ((*gen) (operands[0], operands[1], operands[2])); 7293 DONE; 7294}) 7295 7296(define_expand "builtin_inswl" 7297 [(match_operand:DI 0 "register_operand" "") 7298 (match_operand:DI 1 "reg_or_0_operand" "") 7299 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7300 "" 7301{ 7302 rtx (*gen) (rtx, rtx, rtx); 7303 if (WORDS_BIG_ENDIAN) 7304 gen = gen_inswl_be; 7305 else 7306 gen = gen_inswl_le; 7307 operands[1] = gen_lowpart (HImode, operands[1]); 7308 emit_insn ((*gen) (operands[0], operands[1], operands[2])); 7309 DONE; 7310}) 7311 7312(define_expand "builtin_insll" 7313 [(match_operand:DI 0 "register_operand" "") 7314 (match_operand:DI 1 "reg_or_0_operand" "") 7315 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7316 "" 7317{ 7318 rtx (*gen) (rtx, rtx, rtx); 7319 if (WORDS_BIG_ENDIAN) 7320 gen = gen_insll_be; 7321 else 7322 gen = gen_insll_le; 7323 operands[1] = gen_lowpart (SImode, operands[1]); 7324 emit_insn ((*gen) (operands[0], operands[1], operands[2])); 7325 emit_insn ((*gen) (operands[0], operands[1], operands[2])); 7326 DONE; 7327}) 7328 7329(define_expand "builtin_insql" 7330 [(match_operand:DI 0 "register_operand" "") 7331 (match_operand:DI 1 "reg_or_0_operand" "") 7332 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7333 "" 7334{ 7335 rtx (*gen) (rtx, rtx, rtx); 7336 if (WORDS_BIG_ENDIAN) 7337 gen = gen_insql_be; 7338 else 7339 gen = gen_insql_le; 7340 emit_insn ((*gen) (operands[0], operands[1], operands[2])); 7341 DONE; 7342}) 7343 7344(define_expand "builtin_inswh" 7345 [(match_operand:DI 0 "register_operand" "") 7346 (match_operand:DI 1 "register_operand" "") 7347 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7348 "" 7349{ 7350 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2])); 7351 DONE; 7352}) 7353 7354(define_expand "builtin_inslh" 7355 [(match_operand:DI 0 "register_operand" "") 7356 (match_operand:DI 1 "register_operand" "") 7357 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7358 "" 7359{ 7360 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2])); 7361 DONE; 7362}) 7363 7364(define_expand "builtin_insqh" 7365 [(match_operand:DI 0 "register_operand" "") 7366 (match_operand:DI 1 "register_operand" "") 7367 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7368 "" 7369{ 7370 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2])); 7371 DONE; 7372}) 7373 7374(define_expand "builtin_mskbl" 7375 [(match_operand:DI 0 "register_operand" "") 7376 (match_operand:DI 1 "reg_or_0_operand" "") 7377 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7378 "" 7379{ 7380 rtx (*gen) (rtx, rtx, rtx, rtx); 7381 rtx mask; 7382 if (WORDS_BIG_ENDIAN) 7383 gen = gen_mskxl_be; 7384 else 7385 gen = gen_mskxl_le; 7386 mask = GEN_INT (0xff); 7387 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2])); 7388 DONE; 7389}) 7390 7391(define_expand "builtin_mskwl" 7392 [(match_operand:DI 0 "register_operand" "") 7393 (match_operand:DI 1 "reg_or_0_operand" "") 7394 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7395 "" 7396{ 7397 rtx (*gen) (rtx, rtx, rtx, rtx); 7398 rtx mask; 7399 if (WORDS_BIG_ENDIAN) 7400 gen = gen_mskxl_be; 7401 else 7402 gen = gen_mskxl_le; 7403 mask = GEN_INT (0xffff); 7404 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2])); 7405 DONE; 7406}) 7407 7408(define_expand "builtin_mskll" 7409 [(match_operand:DI 0 "register_operand" "") 7410 (match_operand:DI 1 "reg_or_0_operand" "") 7411 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7412 "" 7413{ 7414 rtx (*gen) (rtx, rtx, rtx, rtx); 7415 rtx mask; 7416 if (WORDS_BIG_ENDIAN) 7417 gen = gen_mskxl_be; 7418 else 7419 gen = gen_mskxl_le; 7420 mask = immed_double_const (0xffffffff, 0, DImode); 7421 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2])); 7422 DONE; 7423}) 7424 7425(define_expand "builtin_mskql" 7426 [(match_operand:DI 0 "register_operand" "") 7427 (match_operand:DI 1 "reg_or_0_operand" "") 7428 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7429 "" 7430{ 7431 rtx (*gen) (rtx, rtx, rtx, rtx); 7432 rtx mask; 7433 if (WORDS_BIG_ENDIAN) 7434 gen = gen_mskxl_be; 7435 else 7436 gen = gen_mskxl_le; 7437 mask = constm1_rtx; 7438 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2])); 7439 DONE; 7440}) 7441 7442(define_expand "builtin_mskwh" 7443 [(match_operand:DI 0 "register_operand" "") 7444 (match_operand:DI 1 "register_operand" "") 7445 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7446 "" 7447{ 7448 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2])); 7449 DONE; 7450}) 7451 7452(define_expand "builtin_msklh" 7453 [(match_operand:DI 0 "register_operand" "") 7454 (match_operand:DI 1 "register_operand" "") 7455 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7456 "" 7457{ 7458 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2])); 7459 DONE; 7460}) 7461 7462(define_expand "builtin_mskqh" 7463 [(match_operand:DI 0 "register_operand" "") 7464 (match_operand:DI 1 "register_operand" "") 7465 (match_operand:DI 2 "reg_or_8bit_operand" "")] 7466 "" 7467{ 7468 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2])); 7469 DONE; 7470}) 7471 7472(define_expand "builtin_zap" 7473 [(set (match_operand:DI 0 "register_operand" "") 7474 (and:DI (unspec:DI 7475 [(match_operand:DI 2 "reg_or_const_int_operand" "")] 7476 UNSPEC_ZAP) 7477 (match_operand:DI 1 "reg_or_const_int_operand" "")))] 7478 "" 7479{ 7480 if (GET_CODE (operands[2]) == CONST_INT) 7481 { 7482 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 7483 7484 if (mask == const0_rtx) 7485 { 7486 emit_move_insn (operands[0], const0_rtx); 7487 DONE; 7488 } 7489 if (mask == constm1_rtx) 7490 { 7491 emit_move_insn (operands[0], operands[1]); 7492 DONE; 7493 } 7494 7495 operands[1] = force_reg (DImode, operands[1]); 7496 emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 7497 DONE; 7498 } 7499 7500 operands[1] = force_reg (DImode, operands[1]); 7501 operands[2] = gen_lowpart (QImode, operands[2]); 7502}) 7503 7504(define_insn "*builtin_zap_1" 7505 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") 7506 (and:DI (unspec:DI 7507 [(match_operand:QI 2 "reg_or_const_int_operand" "n,n,r,r")] 7508 UNSPEC_ZAP) 7509 (match_operand:DI 1 "reg_or_const_int_operand" "n,r,J,r")))] 7510 "" 7511 "@ 7512 # 7513 # 7514 bis $31,$31,%0 7515 zap %r1,%2,%0" 7516 [(set_attr "type" "shift,shift,ilog,shift")]) 7517 7518(define_split 7519 [(set (match_operand:DI 0 "register_operand" "") 7520 (and:DI (unspec:DI 7521 [(match_operand:QI 2 "const_int_operand" "")] 7522 UNSPEC_ZAP) 7523 (match_operand:DI 1 "const_int_operand" "")))] 7524 "" 7525 [(const_int 0)] 7526{ 7527 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 7528 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT) 7529 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode); 7530 else 7531 { 7532 HOST_WIDE_INT c_lo = INTVAL (operands[1]); 7533 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0); 7534 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask), 7535 c_hi & CONST_DOUBLE_HIGH (mask), 7536 DImode); 7537 } 7538 emit_move_insn (operands[0], operands[1]); 7539 DONE; 7540}) 7541 7542(define_split 7543 [(set (match_operand:DI 0 "register_operand" "") 7544 (and:DI (unspec:DI 7545 [(match_operand:QI 2 "const_int_operand" "")] 7546 UNSPEC_ZAP) 7547 (match_operand:DI 1 "register_operand" "")))] 7548 "" 7549 [(set (match_dup 0) 7550 (and:DI (match_dup 1) (match_dup 2)))] 7551{ 7552 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2])); 7553 if (operands[2] == const0_rtx) 7554 { 7555 emit_move_insn (operands[0], const0_rtx); 7556 DONE; 7557 } 7558 if (operands[2] == constm1_rtx) 7559 { 7560 emit_move_insn (operands[0], operands[1]); 7561 DONE; 7562 } 7563}) 7564 7565(define_expand "builtin_zapnot" 7566 [(set (match_operand:DI 0 "register_operand" "") 7567 (and:DI (unspec:DI 7568 [(not:QI (match_operand:DI 2 "reg_or_const_int_operand" ""))] 7569 UNSPEC_ZAP) 7570 (match_operand:DI 1 "reg_or_const_int_operand" "")))] 7571 "" 7572{ 7573 if (GET_CODE (operands[2]) == CONST_INT) 7574 { 7575 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2])); 7576 7577 if (mask == const0_rtx) 7578 { 7579 emit_move_insn (operands[0], const0_rtx); 7580 DONE; 7581 } 7582 if (mask == constm1_rtx) 7583 { 7584 emit_move_insn (operands[0], operands[1]); 7585 DONE; 7586 } 7587 7588 operands[1] = force_reg (DImode, operands[1]); 7589 emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 7590 DONE; 7591 } 7592 7593 operands[1] = force_reg (DImode, operands[1]); 7594 operands[2] = gen_lowpart (QImode, operands[2]); 7595}) 7596 7597(define_insn "*builtin_zapnot_1" 7598 [(set (match_operand:DI 0 "register_operand" "=r") 7599 (and:DI (unspec:DI 7600 [(not:QI (match_operand:QI 2 "register_operand" "r"))] 7601 UNSPEC_ZAP) 7602 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 7603 "" 7604 "zapnot %r1,%2,%0" 7605 [(set_attr "type" "shift")]) 7606 7607(define_insn "builtin_amask" 7608 [(set (match_operand:DI 0 "register_operand" "=r") 7609 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")] 7610 UNSPEC_AMASK))] 7611 "" 7612 "amask %1,%0" 7613 [(set_attr "type" "ilog")]) 7614 7615(define_insn "builtin_implver" 7616 [(set (match_operand:DI 0 "register_operand" "=r") 7617 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))] 7618 "" 7619 "implver %0" 7620 [(set_attr "type" "ilog")]) 7621 7622(define_insn "builtin_rpcc" 7623 [(set (match_operand:DI 0 "register_operand" "=r") 7624 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))] 7625 "" 7626 "rpcc %0" 7627 [(set_attr "type" "ilog")]) 7628 7629(define_expand "builtin_minub8" 7630 [(match_operand:DI 0 "register_operand" "") 7631 (match_operand:DI 1 "reg_or_0_operand" "") 7632 (match_operand:DI 2 "reg_or_0_operand" "")] 7633 "TARGET_MAX" 7634{ 7635 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0], 7636 operands[1], operands[2]); 7637 DONE; 7638}) 7639 7640(define_expand "builtin_minsb8" 7641 [(match_operand:DI 0 "register_operand" "") 7642 (match_operand:DI 1 "reg_or_0_operand" "") 7643 (match_operand:DI 2 "reg_or_0_operand" "")] 7644 "TARGET_MAX" 7645{ 7646 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0], 7647 operands[1], operands[2]); 7648 DONE; 7649}) 7650 7651(define_expand "builtin_minuw4" 7652 [(match_operand:DI 0 "register_operand" "") 7653 (match_operand:DI 1 "reg_or_0_operand" "") 7654 (match_operand:DI 2 "reg_or_0_operand" "")] 7655 "TARGET_MAX" 7656{ 7657 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0], 7658 operands[1], operands[2]); 7659 DONE; 7660}) 7661 7662(define_expand "builtin_minsw4" 7663 [(match_operand:DI 0 "register_operand" "") 7664 (match_operand:DI 1 "reg_or_0_operand" "") 7665 (match_operand:DI 2 "reg_or_0_operand" "")] 7666 "TARGET_MAX" 7667{ 7668 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0], 7669 operands[1], operands[2]); 7670 DONE; 7671}) 7672 7673(define_expand "builtin_maxub8" 7674 [(match_operand:DI 0 "register_operand" "") 7675 (match_operand:DI 1 "reg_or_0_operand" "") 7676 (match_operand:DI 2 "reg_or_0_operand" "")] 7677 "TARGET_MAX" 7678{ 7679 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0], 7680 operands[1], operands[2]); 7681 DONE; 7682}) 7683 7684(define_expand "builtin_maxsb8" 7685 [(match_operand:DI 0 "register_operand" "") 7686 (match_operand:DI 1 "reg_or_0_operand" "") 7687 (match_operand:DI 2 "reg_or_0_operand" "")] 7688 "TARGET_MAX" 7689{ 7690 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0], 7691 operands[1], operands[2]); 7692 DONE; 7693}) 7694 7695(define_expand "builtin_maxuw4" 7696 [(match_operand:DI 0 "register_operand" "") 7697 (match_operand:DI 1 "reg_or_0_operand" "") 7698 (match_operand:DI 2 "reg_or_0_operand" "")] 7699 "TARGET_MAX" 7700{ 7701 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0], 7702 operands[1], operands[2]); 7703 DONE; 7704}) 7705 7706(define_expand "builtin_maxsw4" 7707 [(match_operand:DI 0 "register_operand" "") 7708 (match_operand:DI 1 "reg_or_0_operand" "") 7709 (match_operand:DI 2 "reg_or_0_operand" "")] 7710 "TARGET_MAX" 7711{ 7712 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0], 7713 operands[1], operands[2]); 7714 DONE; 7715}) 7716 7717(define_insn "builtin_perr" 7718 [(set (match_operand:DI 0 "register_operand" "=r") 7719 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ") 7720 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")] 7721 UNSPEC_PERR))] 7722 "TARGET_MAX" 7723 "perr %r1,%r2,%0" 7724 [(set_attr "type" "mvi")]) 7725 7726(define_expand "builtin_pklb" 7727 [(set (match_operand:DI 0 "register_operand" "") 7728 (vec_concat:V8QI 7729 (vec_concat:V4QI 7730 (truncate:V2QI (match_operand:DI 1 "register_operand" "")) 7731 (match_dup 2)) 7732 (match_dup 3)))] 7733 "TARGET_MAX" 7734{ 7735 operands[0] = gen_lowpart (V8QImode, operands[0]); 7736 operands[1] = gen_lowpart (V2SImode, operands[1]); 7737 operands[2] = CONST0_RTX (V2QImode); 7738 operands[3] = CONST0_RTX (V4QImode); 7739}) 7740 7741(define_insn "*pklb" 7742 [(set (match_operand:V8QI 0 "register_operand" "=r") 7743 (vec_concat:V8QI 7744 (vec_concat:V4QI 7745 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r")) 7746 (match_operand:V2QI 2 "const0_operand" "")) 7747 (match_operand:V4QI 3 "const0_operand" "")))] 7748 "TARGET_MAX" 7749 "pklb %r1,%0" 7750 [(set_attr "type" "mvi")]) 7751 7752(define_expand "builtin_pkwb" 7753 [(set (match_operand:DI 0 "register_operand" "") 7754 (vec_concat:V8QI 7755 (truncate:V4QI (match_operand:DI 1 "register_operand" "")) 7756 (match_dup 2)))] 7757 "TARGET_MAX" 7758{ 7759 operands[0] = gen_lowpart (V8QImode, operands[0]); 7760 operands[1] = gen_lowpart (V4HImode, operands[1]); 7761 operands[2] = CONST0_RTX (V4QImode); 7762}) 7763 7764(define_insn "*pkwb" 7765 [(set (match_operand:V8QI 0 "register_operand" "=r") 7766 (vec_concat:V8QI 7767 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r")) 7768 (match_operand:V4QI 2 "const0_operand" "")))] 7769 "TARGET_MAX" 7770 "pkwb %r1,%0" 7771 [(set_attr "type" "mvi")]) 7772 7773(define_expand "builtin_unpkbl" 7774 [(set (match_operand:DI 0 "register_operand" "") 7775 (zero_extend:V2SI 7776 (vec_select:V2QI (match_operand:DI 1 "register_operand" "") 7777 (parallel [(const_int 0) (const_int 1)]))))] 7778 "TARGET_MAX" 7779{ 7780 operands[0] = gen_lowpart (V2SImode, operands[0]); 7781 operands[1] = gen_lowpart (V8QImode, operands[1]); 7782}) 7783 7784(define_insn "*unpkbl" 7785 [(set (match_operand:V2SI 0 "register_operand" "=r") 7786 (zero_extend:V2SI 7787 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 7788 (parallel [(const_int 0) (const_int 1)]))))] 7789 "TARGET_MAX" 7790 "unpkbl %r1,%0" 7791 [(set_attr "type" "mvi")]) 7792 7793(define_expand "builtin_unpkbw" 7794 [(set (match_operand:DI 0 "register_operand" "") 7795 (zero_extend:V4HI 7796 (vec_select:V4QI (match_operand:DI 1 "register_operand" "") 7797 (parallel [(const_int 0) 7798 (const_int 1) 7799 (const_int 2) 7800 (const_int 3)]))))] 7801 "TARGET_MAX" 7802{ 7803 operands[0] = gen_lowpart (V4HImode, operands[0]); 7804 operands[1] = gen_lowpart (V8QImode, operands[1]); 7805}) 7806 7807(define_insn "*unpkbw" 7808 [(set (match_operand:V4HI 0 "register_operand" "=r") 7809 (zero_extend:V4HI 7810 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 7811 (parallel [(const_int 0) 7812 (const_int 1) 7813 (const_int 2) 7814 (const_int 3)]))))] 7815 "TARGET_MAX" 7816 "unpkbw %r1,%0" 7817 [(set_attr "type" "mvi")]) 7818 7819(define_expand "builtin_cttz" 7820 [(set (match_operand:DI 0 "register_operand" "") 7821 (unspec:DI [(match_operand:DI 1 "register_operand" "")] 7822 UNSPEC_CTTZ))] 7823 "TARGET_CIX" 7824 "") 7825 7826(define_insn "builtin_ctlz" 7827 [(set (match_operand:DI 0 "register_operand" "=r") 7828 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 7829 UNSPEC_CTLZ))] 7830 "TARGET_CIX" 7831 "ctlz %1,%0" 7832 [(set_attr "type" "mvi")]) 7833 7834(define_insn "builtin_ctpop" 7835 [(set (match_operand:DI 0 "register_operand" "=r") 7836 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 7837 UNSPEC_CTPOP))] 7838 "TARGET_CIX" 7839 "ctpop %1,%0" 7840 [(set_attr "type" "mvi")]) 7841 7842;; The call patterns are at the end of the file because their 7843;; wildcard operand0 interferes with nice recognition. 7844 7845(define_insn "*call_value_osf_1_er" 7846 [(set (match_operand 0 "" "") 7847 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 7848 (match_operand 2 "" ""))) 7849 (use (reg:DI 29)) 7850 (clobber (reg:DI 26))] 7851 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 7852 "@ 7853 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 7854 bsr $26,%1\t\t!samegp 7855 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 7856 [(set_attr "type" "jsr") 7857 (set_attr "length" "12,*,16")]) 7858 7859;; We must use peep2 instead of a split because we need accurate life 7860;; information for $gp. Consider the case of { bar(); while (1); }. 7861(define_peephole2 7862 [(parallel [(set (match_operand 0 "" "") 7863 (call (mem:DI (match_operand:DI 1 "call_operand" "")) 7864 (match_operand 2 "" ""))) 7865 (use (reg:DI 29)) 7866 (clobber (reg:DI 26))])] 7867 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 7868 && ! samegp_function_operand (operands[1], Pmode) 7869 && (peep2_regno_dead_p (1, 29) 7870 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 7871 [(parallel [(set (match_dup 0) 7872 (call (mem:DI (match_dup 3)) 7873 (match_dup 2))) 7874 (set (reg:DI 26) (plus:DI (pc) (const_int 4))) 7875 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) 7876 (use (match_dup 1)) 7877 (use (match_dup 4))])] 7878{ 7879 if (CONSTANT_P (operands[1])) 7880 { 7881 operands[3] = gen_rtx_REG (Pmode, 27); 7882 operands[4] = GEN_INT (alpha_next_sequence_number++); 7883 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 7884 operands[1], operands[4])); 7885 } 7886 else 7887 { 7888 operands[3] = operands[1]; 7889 operands[1] = const0_rtx; 7890 operands[4] = const0_rtx; 7891 } 7892}) 7893 7894(define_peephole2 7895 [(parallel [(set (match_operand 0 "" "") 7896 (call (mem:DI (match_operand:DI 1 "call_operand" "")) 7897 (match_operand 2 "" ""))) 7898 (use (reg:DI 29)) 7899 (clobber (reg:DI 26))])] 7900 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 7901 && ! samegp_function_operand (operands[1], Pmode) 7902 && ! (peep2_regno_dead_p (1, 29) 7903 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 7904 [(parallel [(set (match_dup 0) 7905 (call (mem:DI (match_dup 3)) 7906 (match_dup 2))) 7907 (set (reg:DI 26) (plus:DI (pc) (const_int 4))) 7908 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) 7909 (use (match_dup 1)) 7910 (use (match_dup 5))]) 7911 (set (reg:DI 29) 7912 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1)) 7913 (set (reg:DI 29) 7914 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))] 7915{ 7916 if (CONSTANT_P (operands[1])) 7917 { 7918 operands[3] = gen_rtx_REG (Pmode, 27); 7919 operands[5] = GEN_INT (alpha_next_sequence_number++); 7920 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 7921 operands[1], operands[5])); 7922 } 7923 else 7924 { 7925 operands[3] = operands[1]; 7926 operands[1] = const0_rtx; 7927 operands[5] = const0_rtx; 7928 } 7929 operands[4] = GEN_INT (alpha_next_sequence_number++); 7930}) 7931 7932;; We add a blockage unspec_volatile to prevent insns from moving down 7933;; from above the call to in between the call and the ldah gpdisp. 7934(define_insn "*call_value_osf_2_er" 7935 [(set (match_operand 0 "" "") 7936 (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 7937 (match_operand 2 "" ""))) 7938 (set (reg:DI 26) 7939 (plus:DI (pc) (const_int 4))) 7940 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) 7941 (use (match_operand 3 "" "")) 7942 (use (match_operand 4 "" ""))] 7943 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 7944 "jsr $26,(%1),%3%J4" 7945 [(set_attr "type" "jsr") 7946 (set_attr "cannot_copy" "true")]) 7947 7948(define_insn "*call_value_osf_1_noreturn" 7949 [(set (match_operand 0 "" "") 7950 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 7951 (match_operand 2 "" ""))) 7952 (use (reg:DI 29)) 7953 (clobber (reg:DI 26))] 7954 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 7955 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 7956 "@ 7957 jsr $26,($27),0%+ 7958 bsr $26,$%1..ng%+ 7959 jsr $26,%1%+" 7960 [(set_attr "type" "jsr") 7961 (set_attr "length" "*,*,8")]) 7962 7963(define_insn_and_split "call_value_osf_tlsgd" 7964 [(set (match_operand 0 "" "") 7965 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "")) 7966 (const_int 0))) 7967 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL) 7968 (use (reg:DI 29)) 7969 (clobber (reg:DI 26))] 7970 "HAVE_AS_TLS" 7971 "#" 7972 "&& reload_completed" 7973 [(set (match_dup 3) 7974 (unspec:DI [(match_dup 5) 7975 (match_dup 1) 7976 (match_dup 2)] UNSPEC_LITERAL)) 7977 (parallel [(set (match_dup 0) 7978 (call (mem:DI (match_dup 3)) 7979 (const_int 0))) 7980 (set (reg:DI 26) (plus:DI (pc) (const_int 4))) 7981 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE) 7982 (use (match_dup 1)) 7983 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))]) 7984 (set (match_dup 5) 7985 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1)) 7986 (set (match_dup 5) 7987 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 7988{ 7989 operands[3] = gen_rtx_REG (Pmode, 27); 7990 operands[4] = GEN_INT (alpha_next_sequence_number++); 7991 operands[5] = pic_offset_table_rtx; 7992} 7993 [(set_attr "type" "multi")]) 7994 7995(define_insn_and_split "call_value_osf_tlsldm" 7996 [(set (match_operand 0 "" "") 7997 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "")) 7998 (const_int 0))) 7999 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL) 8000 (use (reg:DI 29)) 8001 (clobber (reg:DI 26))] 8002 "HAVE_AS_TLS" 8003 "#" 8004 "&& reload_completed" 8005 [(set (match_dup 3) 8006 (unspec:DI [(match_dup 5) 8007 (match_dup 1) 8008 (match_dup 2)] UNSPEC_LITERAL)) 8009 (parallel [(set (match_dup 0) 8010 (call (mem:DI (match_dup 3)) 8011 (const_int 0))) 8012 (set (reg:DI 26) (plus:DI (pc) (const_int 4))) 8013 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE) 8014 (use (match_dup 1)) 8015 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))]) 8016 (set (reg:DI 29) 8017 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1)) 8018 (set (reg:DI 29) 8019 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))] 8020{ 8021 operands[3] = gen_rtx_REG (Pmode, 27); 8022 operands[4] = GEN_INT (alpha_next_sequence_number++); 8023 operands[5] = pic_offset_table_rtx; 8024} 8025 [(set_attr "type" "multi")]) 8026 8027(define_insn "*call_value_osf_1" 8028 [(set (match_operand 0 "" "") 8029 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 8030 (match_operand 2 "" ""))) 8031 (use (reg:DI 29)) 8032 (clobber (reg:DI 26))] 8033 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 8034 "@ 8035 jsr $26,($27),0\;ldgp $29,0($26) 8036 bsr $26,$%1..ng 8037 jsr $26,%1\;ldgp $29,0($26)" 8038 [(set_attr "type" "jsr") 8039 (set_attr "length" "12,*,16")]) 8040 8041(define_insn "*sibcall_value_osf_1_er" 8042 [(set (match_operand 0 "" "") 8043 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 8044 (match_operand 2 "" ""))) 8045 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 8046 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 8047 "@ 8048 br $31,%1\t\t!samegp 8049 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#" 8050 [(set_attr "type" "jsr") 8051 (set_attr "length" "*,8")]) 8052 8053(define_insn "*sibcall_value_osf_1" 8054 [(set (match_operand 0 "" "") 8055 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 8056 (match_operand 2 "" ""))) 8057 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 8058 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 8059 "@ 8060 br $31,$%1..ng 8061 lda $27,%1\;jmp $31,($27),%1" 8062 [(set_attr "type" "jsr") 8063 (set_attr "length" "*,8")]) 8064 8065(define_insn "*call_value_nt_1" 8066 [(set (match_operand 0 "" "") 8067 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s")) 8068 (match_operand 2 "" ""))) 8069 (clobber (reg:DI 26))] 8070 "TARGET_ABI_WINDOWS_NT" 8071 "@ 8072 jsr $26,(%1) 8073 bsr $26,%1 8074 jsr $26,%1" 8075 [(set_attr "type" "jsr") 8076 (set_attr "length" "*,*,12")]) 8077 8078; GAS relies on the order and position of instructions output below in order 8079; to generate relocs for VMS link to potentially optimize the call. 8080; Please do not molest. 8081(define_insn "*call_value_vms_1" 8082 [(set (match_operand 0 "" "") 8083 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s")) 8084 (match_operand 2 "" ""))) 8085 (use (match_operand:DI 3 "nonmemory_operand" "r,n")) 8086 (use (reg:DI 25)) 8087 (use (reg:DI 26)) 8088 (clobber (reg:DI 27))] 8089 "TARGET_ABI_OPEN_VMS" 8090{ 8091 switch (which_alternative) 8092 { 8093 case 0: 8094 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)"; 8095 case 1: 8096 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0); 8097 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0); 8098 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"; 8099 default: 8100 abort(); 8101 } 8102} 8103 [(set_attr "type" "jsr") 8104 (set_attr "length" "12,16")]) 8105 8106(define_insn "*call_value_umk" 8107 [(set (match_operand 0 "" "") 8108 (call (mem:DI (match_operand:DI 1 "call_operand" "r")) 8109 (match_operand 2 "" ""))) 8110 (use (reg:DI 25)) 8111 (clobber (reg:DI 26))] 8112 "TARGET_ABI_UNICOSMK" 8113 "jsr $26,(%1)" 8114 [(set_attr "type" "jsr")]) 8115