1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu. 2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 3 Free Software Foundation, Inc. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 2, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING. If not, write to 19 the Free Software Foundation, 59 Temple Place - Suite 330, 20 Boston, MA 02111-1307, USA. */ 21 22 /* Things to do: 23 - longlong.h? 24 */ 25 26 #undef SWITCH_TAKES_ARG 27 #undef WORD_SWITCH_TAKES_ARG 28 #undef HANDLE_SYSV_PRAGMA 29 #undef SIZE_TYPE 30 #undef PTRDIFF_TYPE 31 #undef WCHAR_TYPE 32 #undef WCHAR_TYPE_SIZE 33 #undef ASM_OUTPUT_EXTERNAL_LIBCALL 34 #undef TARGET_VERSION 35 #undef CPP_SPEC 36 #undef ASM_SPEC 37 #undef LINK_SPEC 38 #undef STARTFILE_SPEC 39 #undef ENDFILE_SPEC 40 #undef SUBTARGET_SWITCHES 41 42 #undef ASM_APP_ON 43 #undef ASM_APP_OFF 44 45 46 /* M32R/X overrides. */ 47 /* Print subsidiary information on the compiler version in use. */ 48 #define TARGET_VERSION fprintf (stderr, " (m32r/x/2)"); 49 50 /* Additional flags for the preprocessor. */ 51 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \ 52 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \ 53 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \ 54 " 55 56 /* Assembler switches. */ 57 #define ASM_CPU_SPEC \ 58 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts" 59 60 /* Use m32rx specific crt0/crtinit/crtfini files. */ 61 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}" 62 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}" 63 64 /* Extra machine dependent switches. */ 65 #define SUBTARGET_SWITCHES \ 66 { "32rx", TARGET_M32RX_MASK, "Compile for the m32rx" }, \ 67 { "32r2", TARGET_M32R2_MASK, "Compile for the m32r2" }, \ 68 { "32r", -(TARGET_M32RX_MASK+TARGET_M32R2_MASK), "" }, 69 70 /* Define this macro as a C expression for the initializer of an array of 71 strings to tell the driver program which options are defaults for this 72 target and thus do not need to be handled specially when using 73 `MULTILIB_OPTIONS'. */ 74 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r" 75 76 /* Number of additional registers the subtarget defines. */ 77 #define SUBTARGET_NUM_REGISTERS 1 78 79 /* 1 for registers that cannot be allocated. */ 80 #define SUBTARGET_FIXED_REGISTERS , 1 81 82 /* 1 for registers that are not available across function calls. */ 83 #define SUBTARGET_CALL_USED_REGISTERS , 1 84 85 /* Order to allocate model specific registers. */ 86 #define SUBTARGET_REG_ALLOC_ORDER , 19 87 88 /* Registers which are accumulators. */ 89 #define SUBTARGET_REG_CLASS_ACCUM 0x80000 90 91 /* All registers added. */ 92 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM 93 94 /* Additional accumulator registers. */ 95 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19) 96 97 /* Define additional register names. */ 98 #define SUBTARGET_REGISTER_NAMES , "a1" 99 /* end M32R/X overrides. */ 100 101 /* Print subsidiary information on the compiler version in use. */ 102 #ifndef TARGET_VERSION 103 #define TARGET_VERSION fprintf (stderr, " (m32r)") 104 #endif 105 106 /* Switch Recognition by gcc.c. Add -G xx support. */ 107 108 #undef SWITCH_TAKES_ARG 109 #define SWITCH_TAKES_ARG(CHAR) \ 110 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') 111 112 /* Names to predefine in the preprocessor for this target machine. */ 113 /* __M32R__ is defined by the existing compiler so we use that. */ 114 #define TARGET_CPU_CPP_BUILTINS() \ 115 do \ 116 { \ 117 builtin_define ("__M32R__"); \ 118 builtin_define ("__m32r__"); \ 119 builtin_assert ("cpu=m32r"); \ 120 builtin_assert ("machine=m32r"); \ 121 builtin_define (TARGET_BIG_ENDIAN \ 122 ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \ 123 if (flag_pic) \ 124 { \ 125 builtin_define ("__pic__"); \ 126 builtin_define ("__PIC__"); \ 127 } \ 128 } \ 129 while (0) 130 131 /* This macro defines names of additional specifications to put in the specs 132 that can be used in various specifications like CC1_SPEC. Its definition 133 is an initializer with a subgrouping for each command option. 134 135 Each subgrouping contains a string constant, that defines the 136 specification name, and a string constant that used by the GCC driver 137 program. 138 139 Do not define this macro if it does not need to do anything. */ 140 141 #ifndef SUBTARGET_EXTRA_SPECS 142 #define SUBTARGET_EXTRA_SPECS 143 #endif 144 145 #ifndef ASM_CPU_SPEC 146 #define ASM_CPU_SPEC "" 147 #endif 148 149 #ifndef CPP_CPU_SPEC 150 #define CPP_CPU_SPEC "" 151 #endif 152 153 #ifndef CC1_CPU_SPEC 154 #define CC1_CPU_SPEC "" 155 #endif 156 157 #ifndef LINK_CPU_SPEC 158 #define LINK_CPU_SPEC "" 159 #endif 160 161 #ifndef STARTFILE_CPU_SPEC 162 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s" 163 #endif 164 165 #ifndef ENDFILE_CPU_SPEC 166 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s" 167 #endif 168 169 #ifndef RELAX_SPEC 170 #if 0 /* Not supported yet. */ 171 #define RELAX_SPEC "%{mrelax:-relax}" 172 #else 173 #define RELAX_SPEC "" 174 #endif 175 #endif 176 177 #define EXTRA_SPECS \ 178 { "asm_cpu", ASM_CPU_SPEC }, \ 179 { "cpp_cpu", CPP_CPU_SPEC }, \ 180 { "cc1_cpu", CC1_CPU_SPEC }, \ 181 { "link_cpu", LINK_CPU_SPEC }, \ 182 { "startfile_cpu", STARTFILE_CPU_SPEC }, \ 183 { "endfile_cpu", ENDFILE_CPU_SPEC }, \ 184 { "relax", RELAX_SPEC }, \ 185 SUBTARGET_EXTRA_SPECS 186 187 #define CPP_SPEC "%(cpp_cpu)" 188 189 #undef CC1_SPEC 190 #define CC1_SPEC "%{G*} %(cc1_cpu)" 191 192 /* Options to pass on to the assembler. */ 193 #undef ASM_SPEC 194 #define ASM_SPEC "%{v} %(asm_cpu) %(relax) %{fpic:-K PIC} %{fPIC:-K PIC}" 195 196 #define LINK_SPEC "%{v} %(link_cpu) %(relax)" 197 198 #undef STARTFILE_SPEC 199 #define STARTFILE_SPEC "%(startfile_cpu)" 200 201 #undef ENDFILE_SPEC 202 #define ENDFILE_SPEC "%(endfile_cpu)" 203 204 #undef LIB_SPEC 205 206 /* Run-time compilation parameters selecting different hardware subsets. */ 207 208 extern int target_flags; 209 210 /* If nonzero, tell the linker to do relaxing. 211 We don't do anything with the option, other than recognize it. 212 LINK_SPEC handles passing -relax to the linker. 213 This can cause incorrect debugging information as line numbers may 214 turn out wrong. This shouldn't be specified unless accompanied with -O2 215 [where the user expects debugging information to be less accurate]. */ 216 #define TARGET_RELAX_MASK (1 << 0) 217 218 /* For miscellaneous debugging purposes. */ 219 #define TARGET_DEBUG_MASK (1 << 1) 220 #define TARGET_DEBUG (target_flags & TARGET_DEBUG_MASK) 221 222 /* Align loops to 32 byte boundaries (cache line size). */ 223 /* ??? This option is experimental and is not documented. */ 224 #define TARGET_ALIGN_LOOPS_MASK (1 << 2) 225 #define TARGET_ALIGN_LOOPS (target_flags & TARGET_ALIGN_LOOPS_MASK) 226 227 /* Change issue rate. */ 228 #define TARGET_LOW_ISSUE_RATE_MASK (1 << 3) 229 #define TARGET_LOW_ISSUE_RATE (target_flags & TARGET_LOW_ISSUE_RATE_MASK) 230 231 /* Change branch cost */ 232 #define TARGET_BRANCH_COST_MASK (1 << 4) 233 #define TARGET_BRANCH_COST (target_flags & TARGET_BRANCH_COST_MASK) 234 235 /* Target machine to compile for. */ 236 #define TARGET_M32R 1 237 238 /* Support extended instruction set. */ 239 #define TARGET_M32RX_MASK (1 << 5) 240 #define TARGET_M32RX (target_flags & TARGET_M32RX_MASK) 241 #undef TARGET_M32R 242 #define TARGET_M32R (! TARGET_M32RX) 243 244 /* Support extended instruction set of m32r2. */ 245 #define TARGET_M32R2_MASK (1 << 6) 246 #define TARGET_M32R2 (target_flags & TARGET_M32R2_MASK) 247 #undef TARGET_M32R 248 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2) 249 250 /* Little Endian Flag. */ 251 #define LITTLE_ENDIAN_BIT (1 << 7) 252 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT) 253 #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) 254 255 /* This defaults us to big-endian. */ 256 #ifndef TARGET_ENDIAN_DEFAULT 257 #define TARGET_ENDIAN_DEFAULT 0 258 #endif 259 260 /* This defaults us to m32r. */ 261 #ifndef TARGET_CPU_DEFAULT 262 #define TARGET_CPU_DEFAULT 0 263 #endif 264 265 /* Macro to define tables used to set the flags. 266 This is a list in braces of pairs in braces, 267 each pair being { "NAME", VALUE } 268 where VALUE is the bits to set or minus the bits to clear. 269 An empty string NAME is used to identify the default VALUE. */ 270 271 #ifndef SUBTARGET_SWITCHES 272 #define SUBTARGET_SWITCHES 273 #endif 274 275 #ifndef TARGET_DEFAULT 276 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT) 277 #endif 278 279 #define TARGET_SWITCHES \ 280 { \ 281 /* { "relax", TARGET_RELAX_MASK, "" }, \ 282 { "no-relax", -TARGET_RELAX_MASK, "" },*/ \ 283 { "debug", TARGET_DEBUG_MASK, \ 284 N_("Display compile time statistics") }, \ 285 { "align-loops", TARGET_ALIGN_LOOPS_MASK, \ 286 N_("Align all loops to 32 byte boundary") }, \ 287 { "no-align-loops", -TARGET_ALIGN_LOOPS_MASK, "" }, \ 288 { "issue-rate=1", TARGET_LOW_ISSUE_RATE_MASK, \ 289 N_("Only issue one instruction per cycle") }, \ 290 { "issue-rate=2", -TARGET_LOW_ISSUE_RATE_MASK, "" }, \ 291 { "branch-cost=1", TARGET_BRANCH_COST_MASK, \ 292 N_("Prefer branches over conditional execution") }, \ 293 { "branch-cost=2", -TARGET_BRANCH_COST_MASK, "" }, \ 294 SUBTARGET_SWITCHES \ 295 { "", TARGET_DEFAULT, "" } \ 296 } 297 298 extern const char * m32r_model_string; 299 extern const char * m32r_sdata_string; 300 301 /* Cache-flush support. */ 302 extern const char * m32r_cache_flush_func; 303 extern const char * m32r_cache_flush_trap_string; 304 extern int m32r_cache_flush_trap; 305 306 #ifndef SUBTARGET_OPTIONS 307 #define SUBTARGET_OPTIONS 308 #endif 309 310 #define TARGET_OPTIONS \ 311 { \ 312 { "model=", & m32r_model_string, \ 313 N_("Code size: small, medium or large"), 0}, \ 314 { "sdata=", & m32r_sdata_string, \ 315 N_("Small data area: none, sdata, use"), 0}, \ 316 { "no-flush-func", & m32r_cache_flush_func, \ 317 N_("Don't call any cache flush functions") }, \ 318 { "flush-func=", & m32r_cache_flush_func, \ 319 N_("Specify cache flush function") }, \ 320 { "no-flush-trap", & m32r_cache_flush_trap_string, \ 321 N_("Don't call any cache flush trap") }, \ 322 { "flush-trap=", & m32r_cache_flush_trap_string, \ 323 N_("Specify cache flush trap number") } \ 324 SUBTARGET_OPTIONS \ 325 } 326 327 /* Code Models 328 329 Code models are used to select between two choices of two separate 330 possibilities (address space size, call insn to use): 331 332 small: addresses use 24 bits, use bl to make calls 333 medium: addresses use 32 bits, use bl to make calls (*1) 334 large: addresses use 32 bits, use seth/add3/jl to make calls (*2) 335 336 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but 337 using this one doesn't make much sense. 338 339 (*1) The linker may eventually be able to relax seth/add3 -> ld24. 340 (*2) The linker may eventually be able to relax seth/add3/jl -> bl. 341 342 Internally these are recorded as TARGET_ADDR{24,32} and 343 TARGET_CALL{26,32}. 344 345 The __model__ attribute can be used to select the code model to use when 346 accessing particular objects. */ 347 348 enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE }; 349 350 extern enum m32r_model m32r_model; 351 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL) 352 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM) 353 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE) 354 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL) 355 #define TARGET_ADDR32 (! TARGET_ADDR24) 356 #define TARGET_CALL26 (! TARGET_CALL32) 357 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE) 358 359 /* The default is the small model. */ 360 #ifndef M32R_MODEL_DEFAULT 361 #define M32R_MODEL_DEFAULT "small" 362 #endif 363 364 /* Small Data Area 365 366 The SDA consists of sections .sdata, .sbss, and .scommon. 367 .scommon isn't a real section, symbols in it have their section index 368 set to SHN_M32R_SCOMMON, though support for it exists in the linker script. 369 370 Two switches control the SDA: 371 372 -G NNN - specifies the maximum size of variable to go in the SDA 373 374 -msdata=foo - specifies how such variables are handled 375 376 -msdata=none - small data area is disabled 377 378 -msdata=sdata - small data goes in the SDA, special code isn't 379 generated to use it, and special relocs aren't 380 generated 381 382 -msdata=use - small data goes in the SDA, special code is generated 383 to use the SDA and special relocs are generated 384 385 The SDA is not multilib'd, it isn't necessary. 386 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd 387 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use 388 -msdata=use will successfully link with them (references in header files 389 will cause the compiler to emit code that refers to library objects in 390 .data). ??? There can be a problem if the user passes a -G value greater 391 than the default and a library object in a header file is that size. 392 The default is 8 so this should be rare - if it occurs the user 393 is required to rebuild the libraries or use a smaller value for -G. */ 394 395 /* Maximum size of variables that go in .sdata/.sbss. 396 The -msdata=foo switch also controls how small variables are handled. */ 397 #ifndef SDATA_DEFAULT_SIZE 398 #define SDATA_DEFAULT_SIZE 8 399 #endif 400 401 enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE }; 402 403 extern enum m32r_sdata m32r_sdata; 404 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE) 405 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA) 406 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE) 407 408 /* Default is to disable the SDA 409 [for upward compatibility with previous toolchains]. */ 410 #ifndef M32R_SDATA_DEFAULT 411 #define M32R_SDATA_DEFAULT "none" 412 #endif 413 414 /* Define this macro as a C expression for the initializer of an array of 415 strings to tell the driver program which options are defaults for this 416 target and thus do not need to be handled specially when using 417 `MULTILIB_OPTIONS'. */ 418 #ifndef SUBTARGET_MULTILIB_DEFAULTS 419 #define SUBTARGET_MULTILIB_DEFAULTS 420 #endif 421 422 #ifndef MULTILIB_DEFAULTS 423 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS } 424 #endif 425 426 /* Sometimes certain combinations of command options do not make 427 sense on a particular target machine. You can define a macro 428 `OVERRIDE_OPTIONS' to take account of this. This macro, if 429 defined, is executed once just after all the command options have 430 been parsed. 431 432 Don't use this macro to turn on various extra optimizations for 433 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 434 435 #ifndef SUBTARGET_OVERRIDE_OPTIONS 436 #define SUBTARGET_OVERRIDE_OPTIONS 437 #endif 438 439 #define OVERRIDE_OPTIONS \ 440 do \ 441 { \ 442 /* These need to be done at start up. \ 443 It's convenient to do them here. */ \ 444 m32r_init (); \ 445 SUBTARGET_OVERRIDE_OPTIONS \ 446 } \ 447 while (0) 448 449 #ifndef SUBTARGET_OPTIMIZATION_OPTIONS 450 #define SUBTARGET_OPTIMIZATION_OPTIONS 451 #endif 452 453 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 454 do \ 455 { \ 456 if (LEVEL == 1) \ 457 flag_regmove = TRUE; \ 458 \ 459 if (SIZE) \ 460 { \ 461 flag_omit_frame_pointer = TRUE; \ 462 flag_strength_reduce = FALSE; \ 463 } \ 464 \ 465 SUBTARGET_OPTIMIZATION_OPTIONS \ 466 } \ 467 while (0) 468 469 /* Define this macro if debugging can be performed even without a 470 frame pointer. If this macro is defined, GCC will turn on the 471 `-fomit-frame-pointer' option whenever `-O' is specified. */ 472 #define CAN_DEBUG_WITHOUT_FP 473 474 /* Target machine storage layout. */ 475 476 /* Define this if most significant bit is lowest numbered 477 in instructions that operate on numbered bit-fields. */ 478 #define BITS_BIG_ENDIAN 1 479 480 /* Define this if most significant byte of a word is the lowest numbered. */ 481 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 482 483 /* Define this if most significant word of a multiword number is the lowest 484 numbered. */ 485 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 486 487 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must 488 be a constant value with the same meaning as WORDS_BIG_ENDIAN, 489 which will be used only when compiling libgcc2.c. Typically the 490 value will be set based on preprocessor defines. */ 491 /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/ 492 493 /* Width of a word, in units (bytes). */ 494 #define UNITS_PER_WORD 4 495 496 /* Define this macro if it is advisable to hold scalars in registers 497 in a wider mode than that declared by the program. In such cases, 498 the value is constrained to be within the bounds of the declared 499 type, but kept valid in the wider mode. The signedness of the 500 extension may differ from that of the type. */ 501 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 502 if (GET_MODE_CLASS (MODE) == MODE_INT \ 503 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 504 { \ 505 (MODE) = SImode; \ 506 } 507 508 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 509 #define PARM_BOUNDARY 32 510 511 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 512 #define STACK_BOUNDARY 32 513 514 /* ALIGN FRAMES on word boundaries */ 515 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3) 516 517 /* Allocation boundary (in *bits*) for the code of a function. */ 518 #define FUNCTION_BOUNDARY 32 519 520 /* Alignment of field after `int : 0' in a structure. */ 521 #define EMPTY_FIELD_BOUNDARY 32 522 523 /* Every structure's size must be a multiple of this. */ 524 #define STRUCTURE_SIZE_BOUNDARY 8 525 526 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 527 #define PCC_BITFIELD_TYPE_MATTERS 1 528 529 /* No data type wants to be aligned rounder than this. */ 530 #define BIGGEST_ALIGNMENT 32 531 532 /* The best alignment to use in cases where we have a choice. */ 533 #define FASTEST_ALIGNMENT 32 534 535 /* Make strings word-aligned so strcpy from constants will be faster. */ 536 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 537 ((TREE_CODE (EXP) == STRING_CST \ 538 && (ALIGN) < FASTEST_ALIGNMENT) \ 539 ? FASTEST_ALIGNMENT : (ALIGN)) 540 541 /* Make arrays of chars word-aligned for the same reasons. */ 542 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 543 (TREE_CODE (TYPE) == ARRAY_TYPE \ 544 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 545 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 546 547 /* Set this nonzero if move instructions will actually fail to work 548 when given unaligned data. */ 549 #define STRICT_ALIGNMENT 1 550 551 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */ 552 #define LABEL_ALIGN(insn) 2 553 554 /* Layout of source language data types. */ 555 556 #define SHORT_TYPE_SIZE 16 557 #define INT_TYPE_SIZE 32 558 #define LONG_TYPE_SIZE 32 559 #define LONG_LONG_TYPE_SIZE 64 560 #define FLOAT_TYPE_SIZE 32 561 #define DOUBLE_TYPE_SIZE 64 562 #define LONG_DOUBLE_TYPE_SIZE 64 563 564 /* Define this as 1 if `char' should by default be signed; else as 0. */ 565 #define DEFAULT_SIGNED_CHAR 1 566 567 #define SIZE_TYPE "long unsigned int" 568 #define PTRDIFF_TYPE "long int" 569 #define WCHAR_TYPE "short unsigned int" 570 #define WCHAR_TYPE_SIZE 16 571 572 /* Standard register usage. */ 573 574 /* Number of actual hardware registers. 575 The hardware registers are assigned numbers for the compiler 576 from 0 to just below FIRST_PSEUDO_REGISTER. 577 All registers that the compiler knows about must be given numbers, 578 even those that are not normally considered general registers. */ 579 580 #define M32R_NUM_REGISTERS 19 581 582 #ifndef SUBTARGET_NUM_REGISTERS 583 #define SUBTARGET_NUM_REGISTERS 0 584 #endif 585 586 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS) 587 588 /* 1 for registers that have pervasive standard uses 589 and are not available for the register allocator. 590 591 0-3 - arguments/results 592 4-5 - call used [4 is used as a tmp during prologue/epilogue generation] 593 6 - call used, gptmp 594 7 - call used, static chain pointer 595 8-11 - call saved 596 12 - call saved [reserved for global pointer] 597 13 - frame pointer 598 14 - subroutine link register 599 15 - stack pointer 600 16 - arg pointer 601 17 - carry flag 602 18 - accumulator 603 19 - accumulator 1 in the m32r/x 604 By default, the extension registers are not available. */ 605 606 #ifndef SUBTARGET_FIXED_REGISTERS 607 #define SUBTARGET_FIXED_REGISTERS 608 #endif 609 610 #define FIXED_REGISTERS \ 611 { \ 612 0, 0, 0, 0, 0, 0, 0, 0, \ 613 0, 0, 0, 0, 0, 0, 0, 1, \ 614 1, 1, 1 \ 615 SUBTARGET_FIXED_REGISTERS \ 616 } 617 618 /* 1 for registers not available across function calls. 619 These must include the FIXED_REGISTERS and also any 620 registers that can be used without being saved. 621 The latter must include the registers where values are returned 622 and the register where structure-value addresses are passed. 623 Aside from that, you can include as many other registers as you like. */ 624 625 #ifndef SUBTARGET_CALL_USED_REGISTERS 626 #define SUBTARGET_CALL_USED_REGISTERS 627 #endif 628 629 #define CALL_USED_REGISTERS \ 630 { \ 631 1, 1, 1, 1, 1, 1, 1, 1, \ 632 0, 0, 0, 0, 0, 0, 1, 1, \ 633 1, 1, 1 \ 634 SUBTARGET_CALL_USED_REGISTERS \ 635 } 636 637 /* Zero or more C statements that may conditionally modify two variables 638 `fixed_regs' and `call_used_regs' (both of type `char []') after they 639 have been initialized from the two preceding macros. 640 641 This is necessary in case the fixed or call-clobbered registers depend 642 on target flags. 643 644 You need not define this macro if it has no work to do. */ 645 646 #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE 647 #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE 648 #else 649 #define CONDITIONAL_REGISTER_USAGE \ 650 do \ 651 { \ 652 if (flag_pic) \ 653 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 654 } \ 655 while (0) 656 #endif 657 658 /* If defined, an initializer for a vector of integers, containing the 659 numbers of hard registers in the order in which GCC should 660 prefer to use them (from most preferred to least). */ 661 662 #ifndef SUBTARGET_REG_ALLOC_ORDER 663 #define SUBTARGET_REG_ALLOC_ORDER 664 #endif 665 666 #if 1 /* Better for int code. */ 667 #define REG_ALLOC_ORDER \ 668 { \ 669 4, 5, 6, 7, 2, 3, 8, 9, 10, \ 670 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \ 671 SUBTARGET_REG_ALLOC_ORDER \ 672 } 673 674 #else /* Better for fp code at expense of int code. */ 675 #define REG_ALLOC_ORDER \ 676 { \ 677 0, 1, 2, 3, 4, 5, 6, 7, 8, \ 678 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \ 679 SUBTARGET_REG_ALLOC_ORDER \ 680 } 681 #endif 682 683 /* Return number of consecutive hard regs needed starting at reg REGNO 684 to hold something of mode MODE. 685 This is ordinarily the length in words of a value of mode MODE 686 but can be less for certain modes in special long registers. */ 687 #define HARD_REGNO_NREGS(REGNO, MODE) \ 688 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 689 690 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 691 extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER]; 692 extern unsigned int m32r_mode_class[]; 693 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 694 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0) 695 696 /* A C expression that is nonzero if it is desirable to choose 697 register allocation so as to avoid move instructions between a 698 value of mode MODE1 and a value of mode MODE2. 699 700 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, 701 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, 702 MODE2)' must be zero. */ 703 704 /* Tie QI/HI/SI modes together. */ 705 #define MODES_TIEABLE_P(MODE1, MODE2) \ 706 ( GET_MODE_CLASS (MODE1) == MODE_INT \ 707 && GET_MODE_CLASS (MODE2) == MODE_INT \ 708 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ 709 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD) 710 711 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 712 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG) 713 714 /* Register classes and constants. */ 715 716 /* Define the classes of registers for register constraints in the 717 machine description. Also define ranges of constants. 718 719 One of the classes must always be named ALL_REGS and include all hard regs. 720 If there is more than one class, another class must be named NO_REGS 721 and contain no registers. 722 723 The name GENERAL_REGS must be the name of a class (or an alias for 724 another name such as ALL_REGS). This is the class of registers 725 that is allowed by "g" or "r" in a register constraint. 726 Also, registers outside this class are allocated only when 727 instructions express preferences for them. 728 729 The classes must be numbered in nondecreasing order; that is, 730 a larger-numbered class must never be contained completely 731 in a smaller-numbered class. 732 733 For any two classes, it is very desirable that there be another 734 class that represents their union. 735 736 It is important that any condition codes have class NO_REGS. 737 See `register_operand'. */ 738 739 enum reg_class 740 { 741 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES 742 }; 743 744 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 745 746 /* Give names of register classes as strings for dump file. */ 747 #define REG_CLASS_NAMES \ 748 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" } 749 750 /* Define which registers fit in which classes. 751 This is an initializer for a vector of HARD_REG_SET 752 of length N_REG_CLASSES. */ 753 754 #ifndef SUBTARGET_REG_CLASS_CARRY 755 #define SUBTARGET_REG_CLASS_CARRY 0 756 #endif 757 758 #ifndef SUBTARGET_REG_CLASS_ACCUM 759 #define SUBTARGET_REG_CLASS_ACCUM 0 760 #endif 761 762 #ifndef SUBTARGET_REG_CLASS_GENERAL 763 #define SUBTARGET_REG_CLASS_GENERAL 0 764 #endif 765 766 #ifndef SUBTARGET_REG_CLASS_ALL 767 #define SUBTARGET_REG_CLASS_ALL 0 768 #endif 769 770 #define REG_CLASS_CONTENTS \ 771 { \ 772 { 0x00000 }, \ 773 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \ 774 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \ 775 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \ 776 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \ 777 } 778 779 /* The same information, inverted: 780 Return the class number of the smallest class containing 781 reg number REGNO. This could be a conditional expression 782 or could index an array. */ 783 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; 784 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO]) 785 786 /* The class value for index registers, and the one for base regs. */ 787 #define INDEX_REG_CLASS GENERAL_REGS 788 #define BASE_REG_CLASS GENERAL_REGS 789 790 #define REG_CLASS_FROM_LETTER(C) \ 791 ( (C) == 'c' ? CARRY_REG \ 792 : (C) == 'a' ? ACCUM_REGS \ 793 : NO_REGS) 794 795 /* These assume that REGNO is a hard or pseudo reg number. 796 They give nonzero only if REGNO is a hard reg of the suitable class 797 or a pseudo reg currently allocated to a suitable hard reg. 798 Since they use reg_renumber, they are safe only once reg_renumber 799 has been allocated, which happens in local-alloc.c. */ 800 #define REGNO_OK_FOR_BASE_P(REGNO) \ 801 ((REGNO) < FIRST_PSEUDO_REGISTER \ 802 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \ 803 : GPR_P (reg_renumber[REGNO])) 804 805 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) 806 807 /* Given an rtx X being reloaded into a reg required to be 808 in class CLASS, return the class of reg to actually use. 809 In general this is just CLASS; but on some machines 810 in some cases it is preferable to use a more restrictive class. */ 811 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS) 812 813 /* Return the maximum number of consecutive registers 814 needed to represent mode MODE in a register of class CLASS. */ 815 #define CLASS_MAX_NREGS(CLASS, MODE) \ 816 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 817 818 /* The letters I, J, K, L, M, N, O, P in a register constraint string 819 can be used to stand for particular ranges of immediate operands. 820 This macro defines what the ranges are. 821 C is the letter, and VALUE is a constant value. 822 Return 1 if VALUE is in the range specified by C. */ 823 /* 'I' is used for 8 bit signed immediates. 824 'J' is used for 16 bit signed immediates. 825 'K' is used for 16 bit unsigned immediates. 826 'L' is used for 16 bit immediates left shifted by 16 (sign ???). 827 'M' is used for 24 bit unsigned immediates. 828 'N' is used for any 32 bit non-symbolic value. 829 'O' is used for 5 bit unsigned immediates (shift count). 830 'P' is used for 16 bit signed immediates for compares 831 (values in the range -32767 to +32768). */ 832 833 /* Return true if a value is inside a range. */ 834 #define IN_RANGE_P(VALUE, LOW, HIGH) \ 835 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \ 836 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW)))) 837 838 /* Local to this file. */ 839 #define INT8_P(X) ((X) >= - 0x80 && (X) <= 0x7f) 840 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff) 841 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000) 842 #define UPPER16_P(X) (((X) & 0xffff) == 0 \ 843 && ((X) >> 16) >= - 0x8000 \ 844 && ((X) >> 16) <= 0x7fff) 845 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff) 846 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff) 847 #define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff) 848 #define UINT5_P(X) ((X) >= 0 && (X) < 32) 849 #define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128) 850 851 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 852 ( (C) == 'I' ? INT8_P (VALUE) \ 853 : (C) == 'J' ? INT16_P (VALUE) \ 854 : (C) == 'K' ? UINT16_P (VALUE) \ 855 : (C) == 'L' ? UPPER16_P (VALUE) \ 856 : (C) == 'M' ? UINT24_P (VALUE) \ 857 : (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE) \ 858 : (C) == 'O' ? UINT5_P (VALUE) \ 859 : (C) == 'P' ? CMP_INT16_P (VALUE) \ 860 : 0) 861 862 /* Similar, but for floating constants, and defining letters G and H. 863 Here VALUE is the CONST_DOUBLE rtx itself. 864 For the m32r, handle a few constants inline. 865 ??? We needn't treat DI and DF modes differently, but for now we do. */ 866 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 867 ( (C) == 'G' ? easy_di_const (VALUE) \ 868 : (C) == 'H' ? easy_df_const (VALUE) \ 869 : 0) 870 871 /* A C expression that defines the optional machine-dependent constraint 872 letters that can be used to segregate specific types of operands, 873 usually memory references, for the target machine. It should return 1 if 874 VALUE corresponds to the operand type represented by the constraint letter 875 C. If C is not defined as an extra constraint, the value returned should 876 be 0 regardless of VALUE. */ 877 /* Q is for symbolic addresses loadable with ld24. 878 R is for symbolic addresses when ld24 can't be used. 879 S is for stores with pre {inc,dec}rement 880 T is for indirect of a pointer. 881 U is for loads with post increment. */ 882 883 #define EXTRA_CONSTRAINT(VALUE, C) \ 884 ( (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \ 885 || addr24_operand (VALUE, VOIDmode)) \ 886 : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \ 887 || addr32_operand (VALUE, VOIDmode)) \ 888 : (C) == 'S' ? (GET_CODE (VALUE) == MEM \ 889 && STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \ 890 XEXP (VALUE, 0))) \ 891 : (C) == 'T' ? (GET_CODE (VALUE) == MEM \ 892 && memreg_operand (VALUE, GET_MODE (VALUE))) \ 893 : (C) == 'U' ? (GET_CODE (VALUE) == MEM \ 894 && LOAD_POSTINC_P (GET_MODE (VALUE), \ 895 XEXP (VALUE, 0))) \ 896 : 0) 897 898 /* Stack layout and stack pointer usage. */ 899 900 /* Define this macro if pushing a word onto the stack moves the stack 901 pointer to a smaller address. */ 902 #define STACK_GROWS_DOWNWARD 903 904 /* Offset from frame pointer to start allocating local variables at. 905 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 906 first local allocated. Otherwise, it is the offset to the BEGINNING 907 of the first local allocated. */ 908 /* The frame pointer points at the same place as the stack pointer, except if 909 alloca has been called. */ 910 #define STARTING_FRAME_OFFSET \ 911 M32R_STACK_ALIGN (current_function_outgoing_args_size) 912 913 /* Offset from the stack pointer register to the first location at which 914 outgoing arguments are placed. */ 915 #define STACK_POINTER_OFFSET 0 916 917 /* Offset of first parameter from the argument pointer register value. */ 918 #define FIRST_PARM_OFFSET(FNDECL) 0 919 920 /* Register to use for pushing function arguments. */ 921 #define STACK_POINTER_REGNUM 15 922 923 /* Base register for access to local variables of the function. */ 924 #define FRAME_POINTER_REGNUM 13 925 926 /* Base register for access to arguments of the function. */ 927 #define ARG_POINTER_REGNUM 16 928 929 /* Register in which static-chain is passed to a function. 930 This must not be a register used by the prologue. */ 931 #define STATIC_CHAIN_REGNUM 7 932 933 /* These aren't official macros. */ 934 #define PROLOGUE_TMP_REGNUM 4 935 #define RETURN_ADDR_REGNUM 14 936 /* #define GP_REGNUM 12 */ 937 #define CARRY_REGNUM 17 938 #define ACCUM_REGNUM 18 939 #define M32R_MAX_INT_REGS 16 940 941 #ifndef SUBTARGET_GPR_P 942 #define SUBTARGET_GPR_P(REGNO) 0 943 #endif 944 945 #ifndef SUBTARGET_ACCUM_P 946 #define SUBTARGET_ACCUM_P(REGNO) 0 947 #endif 948 949 #ifndef SUBTARGET_CARRY_P 950 #define SUBTARGET_CARRY_P(REGNO) 0 951 #endif 952 953 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO)) 954 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO)) 955 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO)) 956 957 /* Eliminating the frame and arg pointers. */ 958 959 /* A C expression which is nonzero if a function must have and use a 960 frame pointer. This expression is evaluated in the reload pass. 961 If its value is nonzero the function will have a frame pointer. */ 962 #define FRAME_POINTER_REQUIRED current_function_calls_alloca 963 964 #if 0 965 /* C statement to store the difference between the frame pointer 966 and the stack pointer values immediately after the function prologue. 967 If `ELIMINABLE_REGS' is defined, this macro will be not be used and 968 need not be defined. */ 969 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ 970 ((VAR) = m32r_compute_frame_size (get_frame_size ())) 971 #endif 972 973 /* If defined, this macro specifies a table of register pairs used to 974 eliminate unneeded registers that point into the stack frame. If 975 it is not defined, the only elimination attempted by the compiler 976 is to replace references to the frame pointer with references to 977 the stack pointer. 978 979 Note that the elimination of the argument pointer with the stack 980 pointer is specified first since that is the preferred elimination. */ 981 982 #define ELIMINABLE_REGS \ 983 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 984 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 985 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }} 986 987 /* A C expression that returns nonzero if the compiler is allowed to 988 try to replace register number FROM-REG with register number 989 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is 990 defined, and will usually be the constant 1, since most of the 991 cases preventing register elimination are things that the compiler 992 already knows about. */ 993 994 #define CAN_ELIMINATE(FROM, TO) \ 995 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ 996 ? ! frame_pointer_needed \ 997 : 1) 998 999 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It 1000 specifies the initial difference between the specified pair of 1001 registers. This macro must be defined if `ELIMINABLE_REGS' is 1002 defined. */ 1003 1004 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1005 do \ 1006 { \ 1007 int size = m32r_compute_frame_size (get_frame_size ()); \ 1008 \ 1009 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ 1010 (OFFSET) = 0; \ 1011 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ 1012 (OFFSET) = size - current_function_pretend_args_size; \ 1013 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ 1014 (OFFSET) = size - current_function_pretend_args_size; \ 1015 else \ 1016 abort (); \ 1017 } \ 1018 while (0) 1019 1020 /* Function argument passing. */ 1021 1022 /* When a prototype says `char' or `short', really pass an `int'. */ 1023 #define PROMOTE_PROTOTYPES 1 1024 1025 /* If defined, the maximum amount of space required for outgoing 1026 arguments will be computed and placed into the variable 1027 `current_function_outgoing_args_size'. No space will be pushed 1028 onto the stack for each call; instead, the function prologue should 1029 increase the stack frame size by this amount. */ 1030 #define ACCUMULATE_OUTGOING_ARGS 1 1031 1032 /* Value is the number of bytes of arguments automatically 1033 popped when returning from a subroutine call. 1034 FUNDECL is the declaration node of the function (as a tree), 1035 FUNTYPE is the data type of the function (as a tree), 1036 or for a library call it is an identifier node for the subroutine name. 1037 SIZE is the number of bytes of arguments passed on the stack. */ 1038 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0 1039 1040 /* Nonzero if we do not know how to pass TYPE solely in registers. */ 1041 #define MUST_PASS_IN_STACK(MODE, TYPE) \ 1042 ((TYPE) != 0 \ 1043 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 1044 || TREE_ADDRESSABLE (TYPE))) 1045 1046 /* Define a data type for recording info about an argument list 1047 during the scan of that argument list. This data type should 1048 hold all necessary information about the function itself 1049 and about the args processed so far, enough to enable macros 1050 such as FUNCTION_ARG to determine where the next arg should go. */ 1051 #define CUMULATIVE_ARGS int 1052 1053 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1054 for a call to a function whose data type is FNTYPE. 1055 For a library call, FNTYPE is 0. */ 1056 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 1057 ((CUM) = 0) 1058 1059 /* The number of registers used for parameter passing. Local to this file. */ 1060 #define M32R_MAX_PARM_REGS 4 1061 1062 /* 1 if N is a possible register number for function argument passing. */ 1063 #define FUNCTION_ARG_REGNO_P(N) \ 1064 ((unsigned) (N) < M32R_MAX_PARM_REGS) 1065 1066 /* The ROUND_ADVANCE* macros are local to this file. */ 1067 /* Round SIZE up to a word boundary. */ 1068 #define ROUND_ADVANCE(SIZE) \ 1069 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1070 1071 /* Round arg MODE/TYPE up to the next word boundary. */ 1072 #define ROUND_ADVANCE_ARG(MODE, TYPE) \ 1073 ((MODE) == BLKmode \ 1074 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \ 1075 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE))) 1076 1077 /* Round CUM up to the necessary point for argument MODE/TYPE. */ 1078 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM) 1079 1080 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in 1081 a reg. This includes arguments that have to be passed by reference as the 1082 pointer to them is passed in a reg if one is available (and that is what 1083 we're given). 1084 This macro is only used in this file. */ 1085 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 1086 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS) 1087 1088 /* Determine where to put an argument to a function. 1089 Value is zero to push the argument on the stack, 1090 or a hard register in which to store the argument. 1091 1092 MODE is the argument's machine mode. 1093 TYPE is the data type of the argument (as a tree). 1094 This is null for libcalls where that information may 1095 not be available. 1096 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1097 the preceding args and about the function being called. 1098 NAMED is nonzero if this argument is a named parameter 1099 (otherwise it is an extra parameter matching an ellipsis). */ 1100 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers 1101 and the rest are pushed. */ 1102 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1103 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 1104 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \ 1105 : 0) 1106 1107 /* A C expression for the number of words, at the beginning of an 1108 argument, must be put in registers. The value must be zero for 1109 arguments that are passed entirely in registers or that are entirely 1110 pushed on the stack. 1111 1112 On some machines, certain arguments must be passed partially in 1113 registers and partially in memory. On these machines, typically the 1114 first @var{n} words of arguments are passed in registers, and the rest 1115 on the stack. If a multi-word argument (a @code{double} or a 1116 structure) crosses that boundary, its first few words must be passed 1117 in registers and the rest must be pushed. This macro tells the 1118 compiler when this occurs, and how many of the words should go in 1119 registers. */ 1120 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1121 function_arg_partial_nregs (&CUM, (int)MODE, TYPE, NAMED) 1122 1123 /* A C expression that indicates when an argument must be passed by 1124 reference. If nonzero for an argument, a copy of that argument is 1125 made in memory and a pointer to the argument is passed instead of 1126 the argument itself. The pointer is passed in whatever way is 1127 appropriate for passing a pointer to that type. */ 1128 /* All arguments greater than 8 bytes are passed this way. */ 1129 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1130 ((TYPE) && m32r_pass_by_reference (TYPE)) 1131 1132 /* Update the data in CUM to advance over an argument 1133 of mode MODE and data type TYPE. 1134 (TYPE is null for libcalls where that information may not be available.) */ 1135 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1136 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \ 1137 + ROUND_ADVANCE_ARG ((MODE), (TYPE)))) 1138 1139 /* If defined, a C expression that gives the alignment boundary, in bits, 1140 of an argument with the specified mode and type. If it is not defined, 1141 PARM_BOUNDARY is used for all arguments. */ 1142 #if 0 1143 /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */ 1144 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1145 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \ 1146 ? PARM_BOUNDARY : 2 * PARM_BOUNDARY) 1147 #endif 1148 1149 /* This macro offers an alternative 1150 to using `__builtin_saveregs' and defining the macro 1151 `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register 1152 arguments into the stack so that all the arguments appear to have 1153 been passed consecutively on the stack. Once this is done, you 1154 can use the standard implementation of varargs that works for 1155 machines that pass all their arguments on the stack. 1156 1157 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure, 1158 containing the values that obtain after processing of the named 1159 arguments. The arguments MODE and TYPE describe the last named 1160 argument--its machine mode and its data type as a tree node. 1161 1162 The macro implementation should do two things: first, push onto the 1163 stack all the argument registers *not* used for the named 1164 arguments, and second, store the size of the data thus pushed into 1165 the `int'-valued variable whose name is supplied as the argument 1166 PRETEND_SIZE. The value that you store here will serve as 1167 additional offset for setting up the stack frame. 1168 1169 If the argument NO_RTL is nonzero, it means that the 1170 arguments of the function are being analyzed for the second time. 1171 This happens for an inline function, which is not actually 1172 compiled until the end of the source file. The macro 1173 `SETUP_INCOMING_VARARGS' should not generate any instructions in 1174 this case. */ 1175 1176 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1177 m32r_setup_incoming_varargs (& ARGS_SO_FAR, MODE, TYPE, & PRETEND_SIZE, NO_RTL) 1178 1179 /* Implement `va_arg'. */ 1180 #define EXPAND_BUILTIN_VA_ARG(valist, type) \ 1181 m32r_va_arg (valist, type) 1182 1183 /* Function results. */ 1184 1185 /* Define how to find the value returned by a function. 1186 VALTYPE is the data type of the value (as a tree). 1187 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1188 otherwise, FUNC is 0. */ 1189 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0) 1190 1191 /* Define how to find the value returned by a library function 1192 assuming the value has mode MODE. */ 1193 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) 1194 1195 /* 1 if N is a possible register number for a function value 1196 as seen by the caller. */ 1197 /* ??? What about r1 in DI/DF values. */ 1198 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) 1199 1200 /* A C expression which can inhibit the returning of certain function 1201 values in registers, based on the type of value. A nonzero value says 1202 to return the function value in memory, just as large structures are 1203 always returned. Here TYPE will be a C expression of type `tree', 1204 representing the data type of the value. */ 1205 #define RETURN_IN_MEMORY(TYPE) m32r_pass_by_reference (TYPE) 1206 1207 /* Tell GCC to use RETURN_IN_MEMORY. */ 1208 #define DEFAULT_PCC_STRUCT_RETURN 0 1209 1210 /* Register in which address to store a structure value 1211 is passed to a function, or 0 to use `invisible' first argument. */ 1212 #define STRUCT_VALUE 0 1213 1214 /* Function entry and exit. */ 1215 1216 /* Initialize data used by insn expanders. This is called from 1217 init_emit, once for each function, before code is generated. */ 1218 #define INIT_EXPANDERS m32r_init_expanders () 1219 1220 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1221 the stack pointer does not matter. The value is tested only in 1222 functions that have frame pointers. 1223 No definition is equivalent to always zero. */ 1224 #define EXIT_IGNORE_STACK 1 1225 1226 /* Output assembler code to FILE to increment profiler label # LABELNO 1227 for profiling a function entry. */ 1228 #undef FUNCTION_PROFILER 1229 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1230 do \ 1231 { \ 1232 if (flag_pic) \ 1233 { \ 1234 fprintf (FILE, "\tld24 r14,#mcount\n"); \ 1235 fprintf (FILE, "\tadd r14,r12\n"); \ 1236 fprintf (FILE, "\tld r14,@r14\n"); \ 1237 fprintf (FILE, "\tjl r14\n"); \ 1238 } \ 1239 else \ 1240 { \ 1241 if (TARGET_ADDR24) \ 1242 fprintf (FILE, "\tbl mcount\n"); \ 1243 else \ 1244 { \ 1245 fprintf (FILE, "\tseth r14,#high(mcount)\n"); \ 1246 fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \ 1247 fprintf (FILE, "\tjl r14\n"); \ 1248 } \ 1249 } \ 1250 fprintf (FILE, "\taddi sp,#4\n"); \ 1251 } \ 1252 while (0) 1253 1254 /* Trampolines. */ 1255 1256 /* On the M32R, the trampoline is: 1257 1258 mv r7, lr -> bl L1 ; 178e 7e01 1259 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12) 1260 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6 1261 ld r6, @r6 -> jmp r6 ; 26c6 1fc6 1262 L2: .word STATIC 1263 .word FUNCTION */ 1264 1265 #ifndef CACHE_FLUSH_FUNC 1266 #define CACHE_FLUSH_FUNC "_flush_cache" 1267 #endif 1268 #ifndef CACHE_FLUSH_TRAP 1269 #define CACHE_FLUSH_TRAP "12" 1270 #endif 1271 1272 /* Length in bytes of the trampoline for entering a nested function. */ 1273 #define TRAMPOLINE_SIZE 24 1274 1275 /* Emit RTL insns to initialize the variable parts of a trampoline. 1276 FNADDR is an RTX for the address of the function's pure code. 1277 CXT is an RTX for the static chain value for the function. */ 1278 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1279 do \ 1280 { \ 1281 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \ 1282 GEN_INT \ 1283 (TARGET_LITTLE_ENDIAN ? 0x017e8e17 : 0x178e7e01)); \ 1284 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \ 1285 GEN_INT \ 1286 (TARGET_LITTLE_ENDIAN ? 0x0c00ae86 : 0x86ae000c)); \ 1287 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \ 1288 GEN_INT \ 1289 (TARGET_LITTLE_ENDIAN ? 0xe627871e : 0x1e8727e6)); \ 1290 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), \ 1291 GEN_INT \ 1292 (TARGET_LITTLE_ENDIAN ? 0xc616c626 : 0x26c61fc6)); \ 1293 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 16)), \ 1294 (CXT)); \ 1295 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 20)), \ 1296 (FNADDR)); \ 1297 if (m32r_cache_flush_trap_string && m32r_cache_flush_trap_string[0]) \ 1298 emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)),\ 1299 GEN_INT (m32r_cache_flush_trap) )); \ 1300 else if (m32r_cache_flush_func && m32r_cache_flush_func[0]) \ 1301 emit_library_call (m32r_function_symbol (m32r_cache_flush_func), \ 1302 0, VOIDmode, 3, TRAMP, Pmode, \ 1303 GEN_INT (TRAMPOLINE_SIZE), SImode, \ 1304 GEN_INT (3), SImode); \ 1305 } \ 1306 while (0) 1307 1308 /* Library calls. */ 1309 1310 /* Generate calls to memcpy, memcmp and memset. */ 1311 #define TARGET_MEM_FUNCTIONS 1312 1313 #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT) 1314 1315 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) 1316 1317 /* Addressing modes, and classification of registers for them. */ 1318 1319 /* Maximum number of registers that can appear in a valid memory address. */ 1320 #define MAX_REGS_PER_ADDRESS 1 1321 1322 /* We have post-inc load and pre-dec,pre-inc store, 1323 but only for 4 byte vals. */ 1324 #define HAVE_PRE_DECREMENT 1 1325 #define HAVE_PRE_INCREMENT 1 1326 #define HAVE_POST_INCREMENT 1 1327 1328 /* Recognize any constant value that is a valid address. */ 1329 #define CONSTANT_ADDRESS_P(X) \ 1330 ( GET_CODE (X) == LABEL_REF \ 1331 || GET_CODE (X) == SYMBOL_REF \ 1332 || GET_CODE (X) == CONST_INT \ 1333 || (GET_CODE (X) == CONST \ 1334 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X)))) 1335 1336 /* Nonzero if the constant value X is a legitimate general operand. 1337 We don't allow (plus symbol large-constant) as the relocations can't 1338 describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations. 1339 We allow all CONST_DOUBLE's as the md file patterns will force the 1340 constant to memory if they can't handle them. */ 1341 1342 #define LEGITIMATE_CONSTANT_P(X) \ 1343 (! (GET_CODE (X) == CONST \ 1344 && GET_CODE (XEXP (X, 0)) == PLUS \ 1345 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \ 1346 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ 1347 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767)) 1348 1349 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1350 and check its validity for a certain class. 1351 We have two alternate definitions for each of them. 1352 The usual definition accepts all pseudo regs; the other rejects 1353 them unless they have been allocated suitable hard regs. 1354 The symbol REG_OK_STRICT causes the latter definition to be used. 1355 1356 Most source files want to accept pseudo regs in the hope that 1357 they will get allocated to the class that the insn wants them to be in. 1358 Source files for reload pass need to be strict. 1359 After reload, it makes no difference, since pseudo regs have 1360 been eliminated by then. */ 1361 1362 #ifdef REG_OK_STRICT 1363 1364 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1365 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X)) 1366 /* Nonzero if X is a hard reg that can be used as an index. */ 1367 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) 1368 1369 #else 1370 1371 /* Nonzero if X is a hard reg that can be used as a base reg 1372 or if it is a pseudo reg. */ 1373 #define REG_OK_FOR_BASE_P(X) \ 1374 (GPR_P (REGNO (X)) \ 1375 || (REGNO (X)) == ARG_POINTER_REGNUM \ 1376 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1377 /* Nonzero if X is a hard reg that can be used as an index 1378 or if it is a pseudo reg. */ 1379 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) 1380 1381 #endif 1382 1383 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1384 that is a valid memory address for an instruction. 1385 The MODE argument is the machine mode for the MEM expression 1386 that wants to use this address. */ 1387 1388 /* Local to this file. */ 1389 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X)) 1390 1391 /* Local to this file. */ 1392 #define RTX_OK_FOR_OFFSET_P(X) \ 1393 (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X))) 1394 1395 /* Local to this file. */ 1396 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \ 1397 (GET_CODE (X) == PLUS \ 1398 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \ 1399 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1))) 1400 1401 /* Local to this file. */ 1402 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word, 1403 since more than one instruction will be required. */ 1404 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \ 1405 (GET_CODE (X) == LO_SUM \ 1406 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\ 1407 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \ 1408 && CONSTANT_P (XEXP (X, 1))) 1409 1410 /* Local to this file. */ 1411 /* Is this a load and increment operation. */ 1412 #define LOAD_POSTINC_P(MODE, X) \ 1413 (((MODE) == SImode || (MODE) == SFmode) \ 1414 && GET_CODE (X) == POST_INC \ 1415 && GET_CODE (XEXP (X, 0)) == REG \ 1416 && RTX_OK_FOR_BASE_P (XEXP (X, 0))) 1417 1418 /* Local to this file. */ 1419 /* Is this an increment/decrement and store operation. */ 1420 #define STORE_PREINC_PREDEC_P(MODE, X) \ 1421 (((MODE) == SImode || (MODE) == SFmode) \ 1422 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \ 1423 && GET_CODE (XEXP (X, 0)) == REG \ 1424 && RTX_OK_FOR_BASE_P (XEXP (X, 0))) 1425 1426 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1427 do \ 1428 { \ 1429 if (RTX_OK_FOR_BASE_P (X)) \ 1430 goto ADDR; \ 1431 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \ 1432 goto ADDR; \ 1433 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \ 1434 goto ADDR; \ 1435 if (LOAD_POSTINC_P ((MODE), (X))) \ 1436 goto ADDR; \ 1437 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \ 1438 goto ADDR; \ 1439 } \ 1440 while (0) 1441 1442 /* Try machine-dependent ways of modifying an illegitimate address 1443 to be legitimate. If we find one, return the new, valid address. 1444 This macro is used in only one place: `memory_address' in explow.c. 1445 1446 OLDX is the address as it was before break_out_memory_refs was called. 1447 In some cases it is useful to look at this to decide what needs to be done. 1448 1449 MODE and WIN are passed so that this macro can use 1450 GO_IF_LEGITIMATE_ADDRESS. 1451 1452 It is always safe for this macro to do nothing. It exists to recognize 1453 opportunities to optimize the output. */ 1454 1455 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 1456 do \ 1457 { \ 1458 if (flag_pic) \ 1459 (X) = m32r_legitimize_pic_address (X, NULL_RTX); \ 1460 if (memory_address_p (MODE, X)) \ 1461 goto WIN; \ 1462 } \ 1463 while (0) 1464 1465 /* Go to LABEL if ADDR (a legitimate address expression) 1466 has an effect that depends on the machine mode it is used for. */ 1467 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1468 do \ 1469 { \ 1470 if ( GET_CODE (ADDR) == PRE_DEC \ 1471 || GET_CODE (ADDR) == PRE_INC \ 1472 || GET_CODE (ADDR) == POST_INC \ 1473 || GET_CODE (ADDR) == LO_SUM) \ 1474 goto LABEL; \ 1475 } \ 1476 while (0) 1477 1478 /* Condition code usage. */ 1479 1480 /* Return nonzero if SELECT_CC_MODE will never return MODE for a 1481 floating point inequality comparison. */ 1482 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ 1483 1484 /* Costs. */ 1485 1486 /* Compute extra cost of moving data between one register class 1487 and another. */ 1488 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2 1489 1490 /* Compute the cost of moving data between registers and memory. */ 1491 /* Memory is 3 times as expensive as registers. 1492 ??? Is that the right way to look at it? */ 1493 #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \ 1494 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12) 1495 1496 /* The cost of a branch insn. */ 1497 /* A value of 2 here causes GCC to avoid using branches in comparisons like 1498 while (a < N && a). Branches aren't that expensive on the M32R so 1499 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */ 1500 #define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1) 1501 1502 /* Nonzero if access to memory by bytes is slow and undesirable. 1503 For RISC chips, it means that access to memory by bytes is no 1504 better than access by words when possible, so grab a whole word 1505 and maybe make use of that. */ 1506 #define SLOW_BYTE_ACCESS 1 1507 1508 /* Define this macro if it is as good or better to call a constant 1509 function address than to call an address kept in a register. */ 1510 #define NO_FUNCTION_CSE 1511 1512 /* Define this macro if it is as good or better for a function to call 1513 itself with an explicit address than to call an address kept in a 1514 register. */ 1515 #define NO_RECURSIVE_FUNCTION_CSE 1516 1517 /* Section selection. */ 1518 1519 #define TEXT_SECTION_ASM_OP "\t.section .text" 1520 #define DATA_SECTION_ASM_OP "\t.section .data" 1521 #define BSS_SECTION_ASM_OP "\t.section .bss" 1522 1523 /* Define this macro if jump tables (for tablejump insns) should be 1524 output in the text section, along with the assembler instructions. 1525 Otherwise, the readonly data section is used. 1526 This macro is irrelevant if there is no separate readonly data section. */ 1527 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) 1528 1529 /* Position Independent Code. */ 1530 1531 /* The register number of the register used to address a table of static 1532 data addresses in memory. In some cases this register is defined by a 1533 processor's ``application binary interface'' (ABI). When this macro 1534 is defined, RTL is generated for this register once, as with the stack 1535 pointer and frame pointer registers. If this macro is not defined, it 1536 is up to the machine-dependent files to allocate such a register (if 1537 necessary). */ 1538 #define PIC_OFFSET_TABLE_REGNUM 12 1539 1540 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is 1541 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM 1542 is not defined. */ 1543 /* This register is call-saved on the M32R. */ 1544 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ 1545 1546 /* By generating position-independent code, when two different programs (A 1547 and B) share a common library (libC.a), the text of the library can be 1548 shared whether or not the library is linked at the same address for both 1549 programs. In some of these environments, position-independent code 1550 requires not only the use of different addressing modes, but also 1551 special code to enable the use of these addressing modes. 1552 1553 The FINALIZE_PIC macro serves as a hook to emit these special 1554 codes once the function is being compiled into assembly code, but not 1555 before. (It is not done before, because in the case of compiling an 1556 inline function, it would lead to multiple PIC prologues being 1557 included in functions which used inline functions and were compiled to 1558 assembly language.) */ 1559 1560 #define FINALIZE_PIC m32r_finalize_pic () 1561 1562 /* A C expression that is nonzero if X is a legitimate immediate 1563 operand on the target machine when generating position independent code. 1564 You can assume that X satisfies CONSTANT_P, so you need not 1565 check this. You can also assume `flag_pic' is true, so you need not 1566 check it either. You need not define this macro if all constants 1567 (including SYMBOL_REF) can be immediate operands when generating 1568 position independent code. */ 1569 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X) 1570 1571 /* Control the assembler format that we output. */ 1572 1573 /* A C string constant describing how to begin a comment in the target 1574 assembler language. The compiler assumes that the comment will 1575 end at the end of the line. */ 1576 #define ASM_COMMENT_START ";" 1577 1578 /* Output to assembler file text saying following lines 1579 may contain character constants, extra white space, comments, etc. */ 1580 #define ASM_APP_ON "" 1581 1582 /* Output to assembler file text saying following lines 1583 no longer contain unusual constructs. */ 1584 #define ASM_APP_OFF "" 1585 1586 /* Globalizing directive for a label. */ 1587 #define GLOBAL_ASM_OP "\t.global\t" 1588 1589 /* If -Os, don't force line number labels to begin at the beginning of 1590 the word; we still want the assembler to try to put things in parallel, 1591 should that be possible. 1592 For m32r/d, instructions are never in parallel (other than with a nop) 1593 and the simulator and stub both handle a breakpoint in the middle of 1594 a word so don't ever force line number labels to begin at the beginning 1595 of a word. */ 1596 1597 #undef ASM_OUTPUT_SOURCE_LINE 1598 #define ASM_OUTPUT_SOURCE_LINE(file, line, counter) \ 1599 do \ 1600 { \ 1601 fprintf (file, ".stabn 68,0,%d,.LM%d-", \ 1602 line, counter); \ 1603 assemble_name \ 1604 (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ 1605 fprintf (file, (optimize_size || TARGET_M32R) \ 1606 ? "\n\t.debugsym .LM%d\n" \ 1607 : "\n.LM%d:\n", \ 1608 counter); \ 1609 } \ 1610 while (0) 1611 1612 /* How to refer to registers in assembler output. 1613 This sequence is indexed by compiler's hard-register-number (see above). */ 1614 #ifndef SUBTARGET_REGISTER_NAMES 1615 #define SUBTARGET_REGISTER_NAMES 1616 #endif 1617 1618 #define REGISTER_NAMES \ 1619 { \ 1620 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 1621 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \ 1622 "ap", "cbit", "a0" \ 1623 SUBTARGET_REGISTER_NAMES \ 1624 } 1625 1626 /* If defined, a C initializer for an array of structures containing 1627 a name and a register number. This macro defines additional names 1628 for hard registers, thus allowing the `asm' option in declarations 1629 to refer to registers using alternate names. */ 1630 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES 1631 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES 1632 #endif 1633 1634 #define ADDITIONAL_REGISTER_NAMES \ 1635 { \ 1636 /*{ "gp", GP_REGNUM },*/ \ 1637 { "r13", FRAME_POINTER_REGNUM }, \ 1638 { "r14", RETURN_ADDR_REGNUM }, \ 1639 { "r15", STACK_POINTER_REGNUM }, \ 1640 SUBTARGET_ADDITIONAL_REGISTER_NAMES \ 1641 } 1642 1643 /* A C expression which evaluates to true if CODE is a valid 1644 punctuation character for use in the `PRINT_OPERAND' macro. */ 1645 extern char m32r_punct_chars[256]; 1646 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 1647 m32r_punct_chars[(unsigned char) (CHAR)] 1648 1649 /* Print operand X (an rtx) in assembler syntax to file FILE. 1650 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1651 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 1652 #define PRINT_OPERAND(FILE, X, CODE) \ 1653 m32r_print_operand (FILE, X, CODE) 1654 1655 /* A C compound statement to output to stdio stream STREAM the 1656 assembler syntax for an instruction operand that is a memory 1657 reference whose address is ADDR. ADDR is an RTL expression. */ 1658 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1659 m32r_print_operand_address (FILE, ADDR) 1660 1661 /* If defined, C string expressions to be used for the `%R', `%L', 1662 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These 1663 are useful when a single `md' file must support multiple assembler 1664 formats. In that case, the various `tm.h' files can define these 1665 macros differently. */ 1666 #define REGISTER_PREFIX "" 1667 #define LOCAL_LABEL_PREFIX ".L" 1668 #define USER_LABEL_PREFIX "" 1669 #define IMMEDIATE_PREFIX "#" 1670 1671 /* This is how to output an element of a case-vector that is absolute. */ 1672 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1673 do \ 1674 { \ 1675 char label[30]; \ 1676 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1677 fprintf (FILE, "\t.word\t"); \ 1678 assemble_name (FILE, label); \ 1679 fprintf (FILE, "\n"); \ 1680 } \ 1681 while (0) 1682 1683 /* This is how to output an element of a case-vector that is relative. */ 1684 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\ 1685 do \ 1686 { \ 1687 char label[30]; \ 1688 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1689 fprintf (FILE, "\t.word\t"); \ 1690 assemble_name (FILE, label); \ 1691 fprintf (FILE, "-"); \ 1692 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ 1693 assemble_name (FILE, label); \ 1694 fprintf (FILE, "\n"); \ 1695 } \ 1696 while (0) 1697 1698 /* The desired alignment for the location counter at the beginning 1699 of a loop. */ 1700 /* On the M32R, align loops to 32 byte boundaries (cache line size) 1701 if -malign-loops. */ 1702 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0) 1703 1704 /* Define this to be the maximum number of insns to move around when moving 1705 a loop test from the top of a loop to the bottom 1706 and seeing whether to duplicate it. The default is thirty. 1707 1708 Loop unrolling currently doesn't like this optimization, so 1709 disable doing if we are unrolling loops and saving space. */ 1710 #define LOOP_TEST_THRESHOLD (optimize_size \ 1711 && !flag_unroll_loops \ 1712 && !flag_unroll_all_loops ? 2 : 30) 1713 1714 /* This is how to output an assembler line 1715 that says to advance the location counter 1716 to a multiple of 2**LOG bytes. */ 1717 /* .balign is used to avoid confusion. */ 1718 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1719 do \ 1720 { \ 1721 if ((LOG) != 0) \ 1722 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \ 1723 } \ 1724 while (0) 1725 1726 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a 1727 separate, explicit argument. If you define this macro, it is used in 1728 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in 1729 handling the required alignment of the variable. The alignment is 1730 specified as the number of bits. */ 1731 1732 #define SCOMMON_ASM_OP "\t.scomm\t" 1733 1734 #undef ASM_OUTPUT_ALIGNED_COMMON 1735 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ 1736 do \ 1737 { \ 1738 if (! TARGET_SDATA_NONE \ 1739 && (SIZE) > 0 && (SIZE) <= g_switch_value) \ 1740 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \ 1741 else \ 1742 fprintf ((FILE), "%s", COMMON_ASM_OP); \ 1743 assemble_name ((FILE), (NAME)); \ 1744 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ 1745 } \ 1746 while (0) 1747 1748 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 1749 do \ 1750 { \ 1751 if (! TARGET_SDATA_NONE \ 1752 && (SIZE) > 0 && (SIZE) <= g_switch_value) \ 1753 named_section (0, ".sbss", 0); \ 1754 else \ 1755 bss_section (); \ 1756 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \ 1757 last_assemble_variable_decl = DECL; \ 1758 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \ 1759 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \ 1760 } \ 1761 while (0) 1762 1763 /* Debugging information. */ 1764 1765 /* Generate DBX and DWARF debugging information. */ 1766 #define DBX_DEBUGGING_INFO 1 1767 #define DWARF2_DEBUGGING_INFO 1 1768 1769 /* Prefer STABS (for now). */ 1770 #undef PREFERRED_DEBUGGING_TYPE 1771 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG 1772 1773 /* Turn off splitting of long stabs. */ 1774 #define DBX_CONTIN_LENGTH 0 1775 1776 /* Miscellaneous. */ 1777 1778 /* Specify the machine mode that this machine uses 1779 for the index in the tablejump instruction. */ 1780 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode) 1781 1782 /* Define if operations between registers always perform the operation 1783 on the full register even if a narrower mode is specified. */ 1784 #define WORD_REGISTER_OPERATIONS 1785 1786 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1787 will either zero-extend or sign-extend. The value of this macro should 1788 be the code that says which one of the two operations is implicitly 1789 done, NIL if none. */ 1790 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1791 1792 /* Max number of bytes we can move from memory 1793 to memory in one reasonably fast instruction. */ 1794 #define MOVE_MAX 4 1795 1796 /* Define this to be nonzero if shift instructions ignore all but the low-order 1797 few bits. */ 1798 #define SHIFT_COUNT_TRUNCATED 1 1799 1800 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1801 is done just by pretending it is already truncated. */ 1802 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1803 1804 /* Specify the machine mode that pointers have. 1805 After generation of rtl, the compiler makes no further distinction 1806 between pointers and any other objects of this machine mode. */ 1807 /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has 1808 it's own problems (you have to add extendpsisi2 and truncsipsi2). 1809 Try to avoid it. */ 1810 #define Pmode SImode 1811 1812 /* A function address in a call instruction. */ 1813 #define FUNCTION_MODE SImode 1814 1815 /* Define the information needed to generate branch and scc insns. This is 1816 stored from the compare operation. Note that we can't use "rtx" here 1817 since it hasn't been defined! */ 1818 extern struct rtx_def * m32r_compare_op0; 1819 extern struct rtx_def * m32r_compare_op1; 1820 1821 /* M32R function types. */ 1822 enum m32r_function_type 1823 { 1824 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT 1825 }; 1826 1827 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT) 1828 1829 /* Define this if you have defined special-purpose predicates in the 1830 file `MACHINE.c'. This macro is called within an initializer of an 1831 array of structures. The first field in the structure is the name 1832 of a predicate and the second field is an array of rtl codes. For 1833 each predicate, list all rtl codes that can be in expressions 1834 matched by the predicate. The list should have a trailing comma. */ 1835 1836 #define PREDICATE_CODES \ 1837 { "reg_or_zero_operand", { REG, SUBREG, CONST_INT }}, \ 1838 { "conditional_move_operand", { REG, SUBREG, CONST_INT }}, \ 1839 { "carry_compare_operand", { EQ, NE }}, \ 1840 { "eqne_comparison_operator", { EQ, NE }}, \ 1841 { "signed_comparison_operator", { EQ, NE, LT, LE, GT, GE }}, \ 1842 { "move_dest_operand", { REG, SUBREG, MEM }}, \ 1843 { "move_src_operand", { REG, SUBREG, MEM, CONST_INT, \ 1844 CONST_DOUBLE, LABEL_REF, CONST, \ 1845 SYMBOL_REF }}, \ 1846 { "move_double_src_operand", { REG, SUBREG, MEM, CONST_INT, \ 1847 CONST_DOUBLE }}, \ 1848 { "two_insn_const_operand", { CONST_INT }}, \ 1849 { "symbolic_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \ 1850 { "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \ 1851 { "int8_operand", { CONST_INT }}, \ 1852 { "uint16_operand", { CONST_INT }}, \ 1853 { "reg_or_int16_operand", { REG, SUBREG, CONST_INT }}, \ 1854 { "reg_or_uint16_operand", { REG, SUBREG, CONST_INT }}, \ 1855 { "reg_or_cmp_int16_operand", { REG, SUBREG, CONST_INT }}, \ 1856 { "reg_or_eq_int16_operand", { REG, SUBREG, CONST_INT }}, \ 1857 { "cmp_int16_operand", { CONST_INT }}, \ 1858 { "call_address_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \ 1859 { "extend_operand", { REG, SUBREG, MEM }}, \ 1860 { "small_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \ 1861 { "m32r_block_immediate_operand",{ CONST_INT }}, \ 1862 { "large_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \ 1863 { "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }}, 1864 1865