1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26 #include "config.h"
27 #include "system.h"
28 #include "coretypes.h"
29 #include "tm.h"
30 #include <signal.h>
31 #include "rtl.h"
32 #include "regs.h"
33 #include "hard-reg-set.h"
34 #include "real.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
38 #include "recog.h"
39 #include "toplev.h"
40 #include "output.h"
41 #include "tree.h"
42 #include "function.h"
43 #include "expr.h"
44 #include "optabs.h"
45 #include "flags.h"
46 #include "reload.h"
47 #include "tm_p.h"
48 #include "ggc.h"
49 #include "gstab.h"
50 #include "hashtab.h"
51 #include "debug.h"
52 #include "target.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57
58 /* Enumeration for all of the relational tests, so that we can build
59 arrays indexed by the test type, and not worry about the order
60 of EQ, NE, etc. */
61
62 enum internal_test {
63 ITEST_EQ,
64 ITEST_NE,
65 ITEST_GT,
66 ITEST_GE,
67 ITEST_LT,
68 ITEST_LE,
69 ITEST_GTU,
70 ITEST_GEU,
71 ITEST_LTU,
72 ITEST_LEU,
73 ITEST_MAX
74 };
75
76 /* Return true if it is likely that the given mode will be accessed
77 using only a single instruction. */
78 #define SINGLE_WORD_MODE_P(MODE) \
79 ((MODE) != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
80
81 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
82 #define UNSPEC_ADDRESS_P(X) \
83 (GET_CODE (X) == UNSPEC \
84 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
85 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
86
87 /* Extract the symbol or label from UNSPEC wrapper X. */
88 #define UNSPEC_ADDRESS(X) \
89 XVECEXP (X, 0, 0)
90
91 /* Extract the symbol type from UNSPEC wrapper X. */
92 #define UNSPEC_ADDRESS_TYPE(X) \
93 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
94
95 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
96 to initialize the mips16 gp pseudo register. */
97 #define CONST_GP_P(X) \
98 (GET_CODE (X) == CONST \
99 && GET_CODE (XEXP (X, 0)) == UNSPEC \
100 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
101
102 /* The maximum distance between the top of the stack frame and the
103 value $sp has when we save & restore registers.
104
105 Use a maximum gap of 0x100 in the mips16 case. We can then use
106 unextended instructions to save and restore registers, and to
107 allocate and deallocate the top part of the frame.
108
109 The value in the !mips16 case must be a SMALL_OPERAND and must
110 preserve the maximum stack alignment. It could really be 0x7ff0,
111 but SGI's assemblers implement daddiu $sp,$sp,-0x7ff0 as a
112 multi-instruction addu sequence. Use 0x7fe0 to work around this. */
113 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7fe0)
114
115 /* Classifies a SYMBOL_REF, LABEL_REF or UNSPEC address.
116
117 SYMBOL_GENERAL
118 Used when none of the below apply.
119
120 SYMBOL_SMALL_DATA
121 The symbol refers to something in a small data section.
122
123 SYMBOL_CONSTANT_POOL
124 The symbol refers to something in the mips16 constant pool.
125
126 SYMBOL_GOT_LOCAL
127 The symbol refers to local data that will be found using
128 the global offset table.
129
130 SYMBOL_GOT_GLOBAL
131 Likewise non-local data.
132
133 SYMBOL_GOTOFF_PAGE
134 An UNSPEC wrapper around a SYMBOL_GOT_LOCAL. It represents the
135 offset from _gp of a GOT page entry.
136
137 SYMBOL_GOTOFF_GLOBAL
138 An UNSPEC wrapper around a SYMBOL_GOT_GLOBAL. It represents the
139 the offset from _gp of the symbol's GOT entry.
140
141 SYMBOL_GOTOFF_CALL
142 Like SYMBOL_GOTOFF_GLOBAL, but used when calling a global function.
143 The GOT entry is allowed to point to a stub rather than to the
144 function itself.
145
146 SYMBOL_GOTOFF_LOADGP
147 An UNSPEC wrapper around a function's address. It represents the
148 offset of _gp from the start of the function. */
149 enum mips_symbol_type {
150 SYMBOL_GENERAL,
151 SYMBOL_SMALL_DATA,
152 SYMBOL_CONSTANT_POOL,
153 SYMBOL_GOT_LOCAL,
154 SYMBOL_GOT_GLOBAL,
155 SYMBOL_GOTOFF_PAGE,
156 SYMBOL_GOTOFF_GLOBAL,
157 SYMBOL_GOTOFF_CALL,
158 SYMBOL_GOTOFF_LOADGP
159 };
160 #define NUM_SYMBOL_TYPES (SYMBOL_GOTOFF_LOADGP + 1)
161
162
163 /* Classifies an address.
164
165 ADDRESS_REG
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
168
169 ADDRESS_LO_SUM
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
172
173 ADDRESS_CONST_INT
174 A signed 16-bit constant address.
175
176 ADDRESS_SYMBOLIC:
177 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
178 enum mips_address_type {
179 ADDRESS_REG,
180 ADDRESS_LO_SUM,
181 ADDRESS_CONST_INT,
182 ADDRESS_SYMBOLIC
183 };
184
185 /* A function to save or store a register. The first argument is the
186 register and the second is the stack slot. */
187 typedef void (*mips_save_restore_fn) (rtx, rtx);
188
189 struct constant;
190 struct mips_arg_info;
191 struct mips_address_info;
192 struct mips_integer_op;
193
194 static enum mips_symbol_type mips_classify_symbol (rtx);
195 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
196 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
197 static bool mips_symbolic_constant_p (rtx, enum mips_symbol_type *);
198 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
199 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
200 static bool mips_classify_address (struct mips_address_info *, rtx,
201 enum machine_mode, int);
202 static int mips_symbol_insns (enum mips_symbol_type);
203 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
204 static rtx mips_force_temporary (rtx, rtx);
205 static rtx mips_split_symbol (rtx, rtx);
206 static rtx mips_unspec_address (rtx, enum mips_symbol_type);
207 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
208 static rtx mips_load_got (rtx, rtx, enum mips_symbol_type);
209 static rtx mips_add_offset (rtx, HOST_WIDE_INT);
210 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
211 static unsigned int mips_build_lower (struct mips_integer_op *,
212 unsigned HOST_WIDE_INT);
213 static unsigned int mips_build_integer (struct mips_integer_op *,
214 unsigned HOST_WIDE_INT);
215 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
216 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
217 static int m16_check_op (rtx, int, int, int);
218 static bool mips_rtx_costs (rtx, int, int, int *);
219 static int mips_address_cost (rtx);
220 static enum internal_test map_test_to_internal_test (enum rtx_code);
221 static void get_float_compare_codes (enum rtx_code, enum rtx_code *,
222 enum rtx_code *);
223 static void mips_load_call_address (rtx, rtx, int);
224 static bool mips_function_ok_for_sibcall (tree, tree);
225 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
226 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
227 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
228 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
229 tree, int, struct mips_arg_info *);
230 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
231 static void mips_set_architecture (const struct mips_cpu_info *);
232 static void mips_set_tune (const struct mips_cpu_info *);
233 static struct machine_function *mips_init_machine_status (void);
234 static void print_operand_reloc (FILE *, rtx, const char **);
235 static bool mips_assemble_integer (rtx, unsigned int, int);
236 static void mips_file_start (void);
237 static void mips_file_end (void);
238 static bool mips_rewrite_small_data_p (rtx);
239 static int small_data_pattern_1 (rtx *, void *);
240 static int mips_rewrite_small_data_1 (rtx *, void *);
241 static bool mips_function_has_gp_insn (void);
242 static unsigned int mips_global_pointer (void);
243 static bool mips_save_reg_p (unsigned int);
244 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
245 mips_save_restore_fn);
246 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
247 static void mips_output_cplocal (void);
248 static void mips_emit_loadgp (void);
249 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
250 static void mips_set_frame_expr (rtx);
251 static rtx mips_frame_set (rtx, rtx);
252 static void mips_save_reg (rtx, rtx);
253 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
254 static void mips_restore_reg (rtx, rtx);
255 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
256 HOST_WIDE_INT, tree);
257 static int symbolic_expression_p (rtx);
258 static void mips_select_rtx_section (enum machine_mode, rtx,
259 unsigned HOST_WIDE_INT);
260 static void mips_select_section (tree, int, unsigned HOST_WIDE_INT)
261 ATTRIBUTE_UNUSED;
262 static bool mips_in_small_data_p (tree);
263 static void mips_encode_section_info (tree, rtx, int);
264 static int mips_fpr_return_fields (tree, tree *);
265 static bool mips_return_in_msb (tree);
266 static rtx mips_return_fpr_pair (enum machine_mode mode,
267 enum machine_mode mode1, HOST_WIDE_INT,
268 enum machine_mode mode2, HOST_WIDE_INT);
269 static rtx mips16_gp_pseudo_reg (void);
270 static void mips16_fp_args (FILE *, int, int);
271 static void build_mips16_function_stub (FILE *);
272 static rtx add_constant (struct constant **, rtx, enum machine_mode);
273 static void dump_constants (struct constant *, rtx);
274 static rtx mips_find_symbol (rtx);
275 static void mips16_lay_out_constants (void);
276 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
277 static void mips_avoid_hazards (void);
278 static void mips_reorg (void);
279 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
280 static bool mips_matching_cpu_name_p (const char *, const char *);
281 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
282 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
283 static int mips_adjust_cost (rtx, rtx, rtx, int);
284 static int mips_issue_rate (void);
285 static int mips_use_dfa_pipeline_interface (void);
286 static void mips_init_libfuncs (void);
287 static tree mips_build_builtin_va_list (void);
288
289 #if TARGET_IRIX
290 static void irix_asm_named_section_1 (const char *, unsigned int,
291 unsigned int);
292 static void irix_asm_named_section (const char *, unsigned int);
293 static int irix_section_align_entry_eq (const void *, const void *);
294 static hashval_t irix_section_align_entry_hash (const void *);
295 static void irix_file_start (void);
296 static int irix_section_align_1 (void **, void *);
297 static void copy_file_data (FILE *, FILE *);
298 static void irix_file_end (void);
299 static unsigned int irix_section_type_flags (tree, const char *, int);
300 #endif
301
302 /* Structure to be filled in by compute_frame_size with register
303 save masks, and offsets for the current function. */
304
305 struct mips_frame_info GTY(())
306 {
307 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
308 HOST_WIDE_INT var_size; /* # bytes that variables take up */
309 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
310 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
311 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
312 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
313 unsigned int mask; /* mask of saved gp registers */
314 unsigned int fmask; /* mask of saved fp registers */
315 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
316 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
317 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
318 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
319 bool initialized; /* true if frame size already calculated */
320 int num_gp; /* number of gp registers saved */
321 int num_fp; /* number of fp registers saved */
322 };
323
324 struct machine_function GTY(()) {
325 /* Pseudo-reg holding the address of the current function when
326 generating embedded PIC code. */
327 rtx embedded_pic_fnaddr_rtx;
328
329 /* Pseudo-reg holding the value of $28 in a mips16 function which
330 refers to GP relative global variables. */
331 rtx mips16_gp_pseudo_rtx;
332
333 /* Current frame information, calculated by compute_frame_size. */
334 struct mips_frame_info frame;
335
336 /* Length of instructions in function; mips16 only. */
337 long insns_len;
338
339 /* The register to use as the global pointer within this function. */
340 unsigned int global_pointer;
341
342 /* True if mips_adjust_insn_length should ignore an instruction's
343 hazard attribute. */
344 bool ignore_hazard_length_p;
345
346 /* True if the whole function is suitable for .set noreorder and
347 .set nomacro. */
348 bool all_noreorder_p;
349
350 /* True if the function is known to have an instruction that needs $gp. */
351 bool has_gp_insn_p;
352 };
353
354 /* Information about a single argument. */
355 struct mips_arg_info
356 {
357 /* True if the argument is passed in a floating-point register, or
358 would have been if we hadn't run out of registers. */
359 bool fpr_p;
360
361 /* The argument's size, in bytes. */
362 unsigned int num_bytes;
363
364 /* The number of words passed in registers, rounded up. */
365 unsigned int reg_words;
366
367 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
368 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
369 on the stack. */
370 unsigned int reg_offset;
371
372 /* The number of words that must be passed on the stack, rounded up. */
373 unsigned int stack_words;
374
375 /* The offset from the start of the stack overflow area of the argument's
376 first stack word. Only meaningful when STACK_WORDS is nonzero. */
377 unsigned int stack_offset;
378 };
379
380
381 /* Information about an address described by mips_address_type.
382
383 ADDRESS_CONST_INT
384 No fields are used.
385
386 ADDRESS_REG
387 REG is the base register and OFFSET is the constant offset.
388
389 ADDRESS_LO_SUM
390 REG is the register that contains the high part of the address,
391 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
392 is the type of OFFSET's symbol.
393
394 ADDRESS_SYMBOLIC
395 SYMBOL_TYPE is the type of symbol being referenced. */
396
397 struct mips_address_info
398 {
399 enum mips_address_type type;
400 rtx reg;
401 rtx offset;
402 enum mips_symbol_type symbol_type;
403 };
404
405
406 /* One stage in a constant building sequence. These sequences have
407 the form:
408
409 A = VALUE[0]
410 A = A CODE[1] VALUE[1]
411 A = A CODE[2] VALUE[2]
412 ...
413
414 where A is an accumulator, each CODE[i] is a binary rtl operation
415 and each VALUE[i] is a constant integer. */
416 struct mips_integer_op {
417 enum rtx_code code;
418 unsigned HOST_WIDE_INT value;
419 };
420
421
422 /* The largest number of operations needed to load an integer constant.
423 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
424 When the lowest bit is clear, we can try, but reject a sequence with
425 an extra SLL at the end. */
426 #define MIPS_MAX_INTEGER_OPS 7
427
428
429 /* Global variables for machine-dependent things. */
430
431 /* Threshold for data being put into the small data/bss area, instead
432 of the normal data area. */
433 int mips_section_threshold = -1;
434
435 /* Count the number of .file directives, so that .loc is up to date. */
436 int num_source_filenames = 0;
437
438 /* Count the number of sdb related labels are generated (to find block
439 start and end boundaries). */
440 int sdb_label_count = 0;
441
442 /* Next label # for each statement for Silicon Graphics IRIS systems. */
443 int sym_lineno = 0;
444
445 /* Linked list of all externals that are to be emitted when optimizing
446 for the global pointer if they haven't been declared by the end of
447 the program with an appropriate .comm or initialization. */
448
449 struct extern_list GTY (())
450 {
451 struct extern_list *next; /* next external */
452 const char *name; /* name of the external */
453 int size; /* size in bytes */
454 };
455
456 static GTY (()) struct extern_list *extern_head = 0;
457
458 /* Name of the file containing the current function. */
459 const char *current_function_file = "";
460
461 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
462 int set_noreorder;
463 int set_noat;
464 int set_nomacro;
465 int set_volatile;
466
467 /* The next branch instruction is a branch likely, not branch normal. */
468 int mips_branch_likely;
469
470 /* Cached operands, and operator to compare for use in set/branch/trap
471 on condition codes. */
472 rtx branch_cmp[2];
473
474 /* what type of branch to use */
475 enum cmp_type branch_type;
476
477 /* The target cpu for code generation. */
478 enum processor_type mips_arch;
479 const struct mips_cpu_info *mips_arch_info;
480
481 /* The target cpu for optimization and scheduling. */
482 enum processor_type mips_tune;
483 const struct mips_cpu_info *mips_tune_info;
484
485 /* Which instruction set architecture to use. */
486 int mips_isa;
487
488 /* Which ABI to use. */
489 int mips_abi;
490
491 /* Strings to hold which cpu and instruction set architecture to use. */
492 const char *mips_arch_string; /* for -march=<xxx> */
493 const char *mips_tune_string; /* for -mtune=<xxx> */
494 const char *mips_isa_string; /* for -mips{1,2,3,4} */
495 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
496
497 /* Whether we are generating mips16 hard float code. In mips16 mode
498 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
499 -msoft-float was not specified by the user, which means that we
500 should arrange to call mips32 hard floating point code. */
501 int mips16_hard_float;
502
503 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
504
505 /* If TRUE, we split addresses into their high and low parts in the RTL. */
506 int mips_split_addresses;
507
508 /* Mode used for saving/restoring general purpose registers. */
509 static enum machine_mode gpr_mode;
510
511 /* Array giving truth value on whether or not a given hard register
512 can support a given mode. */
513 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
514
515 /* The length of all strings seen when compiling for the mips16. This
516 is used to tell how many strings are in the constant pool, so that
517 we can see if we may have an overflow. This is reset each time the
518 constant pool is output. */
519 int mips_string_length;
520
521 /* When generating mips16 code, a list of all strings that are to be
522 output after the current function. */
523
524 static GTY(()) rtx mips16_strings;
525
526 /* In mips16 mode, we build a list of all the string constants we see
527 in a particular function. */
528
529 struct string_constant
530 {
531 struct string_constant *next;
532 const char *label;
533 };
534
535 static struct string_constant *string_constants;
536
537 /* List of all MIPS punctuation characters used by print_operand. */
538 char mips_print_operand_punct[256];
539
540 /* Map GCC register number to debugger register number. */
541 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
542
543 /* An alias set for the GOT. */
544 static GTY(()) int mips_got_alias_set;
545
546 /* A copy of the original flag_delayed_branch: see override_options. */
547 static int mips_flag_delayed_branch;
548
549 static GTY (()) int mips_output_filename_first_time = 1;
550
551 /* mips_split_p[X] is true if symbols of type X can be split by
552 mips_split_symbol(). */
553 static bool mips_split_p[NUM_SYMBOL_TYPES];
554
555 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
556 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
557 if they are matched by a special .md file pattern. */
558 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
559
560 /* Likewise for HIGHs. */
561 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
562
563 /* Hardware names for the registers. If -mrnames is used, this
564 will be overwritten with mips_sw_reg_names. */
565
566 char mips_reg_names[][8] =
567 {
568 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
569 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
570 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
571 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
572 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
573 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
574 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
575 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
576 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
577 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec",
578 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
579 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
580 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
581 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
582 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
583 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
584 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
585 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
586 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
587 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
588 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
589 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
590 };
591
592 /* Mips software names for the registers, used to overwrite the
593 mips_reg_names array. */
594
595 char mips_sw_reg_names[][8] =
596 {
597 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
598 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
599 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
600 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
601 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
602 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
603 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
604 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
605 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
606 "$fcc5","$fcc6","$fcc7","$rap", "", "$arg", "$frame", "$fakec",
607 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
608 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
609 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
610 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
611 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
612 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
613 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
614 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
615 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
616 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
617 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
618 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
619 };
620
621 /* Map hard register number to register class */
622 const enum reg_class mips_regno_to_class[] =
623 {
624 LEA_REGS, LEA_REGS, M16_NA_REGS, M16_NA_REGS,
625 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
626 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
627 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
628 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
629 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
630 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
631 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
632 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
633 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
634 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
635 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
636 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
637 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
638 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
639 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
640 HI_REG, LO_REG, NO_REGS, ST_REGS,
641 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
642 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
643 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
644 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
645 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
646 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
647 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
648 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
649 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
650 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
651 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
652 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
653 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
654 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
655 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
656 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
657 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
658 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
659 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
660 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
661 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
662 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
663 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
664 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
665 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
666 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
667 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
668 };
669
670 /* Map register constraint character to register class. */
671 enum reg_class mips_char_to_class[256];
672
673 /* A table describing all the processors gcc knows about. Names are
674 matched in the order listed. The first mention of an ISA level is
675 taken as the canonical name for that ISA.
676
677 To ease comparison, please keep this table in the same order as
678 gas's mips_cpu_info_table[]. */
679 const struct mips_cpu_info mips_cpu_info_table[] = {
680 /* Entries for generic ISAs */
681 { "mips1", PROCESSOR_R3000, 1 },
682 { "mips2", PROCESSOR_R6000, 2 },
683 { "mips3", PROCESSOR_R4000, 3 },
684 { "mips4", PROCESSOR_R8000, 4 },
685 { "mips32", PROCESSOR_4KC, 32 },
686 { "mips32r2", PROCESSOR_M4K, 33 },
687 { "mips64", PROCESSOR_5KC, 64 },
688
689 /* MIPS I */
690 { "r3000", PROCESSOR_R3000, 1 },
691 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
692 { "r3900", PROCESSOR_R3900, 1 },
693
694 /* MIPS II */
695 { "r6000", PROCESSOR_R6000, 2 },
696
697 /* MIPS III */
698 { "r4000", PROCESSOR_R4000, 3 },
699 { "vr4100", PROCESSOR_R4100, 3 },
700 { "vr4111", PROCESSOR_R4111, 3 },
701 { "vr4120", PROCESSOR_R4120, 3 },
702 { "vr4300", PROCESSOR_R4300, 3 },
703 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
704 { "r4600", PROCESSOR_R4600, 3 },
705 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
706 { "r4650", PROCESSOR_R4650, 3 },
707
708 /* MIPS IV */
709 { "r8000", PROCESSOR_R8000, 4 },
710 { "vr5000", PROCESSOR_R5000, 4 },
711 { "vr5400", PROCESSOR_R5400, 4 },
712 { "vr5500", PROCESSOR_R5500, 4 },
713 { "rm7000", PROCESSOR_R7000, 4 },
714 { "rm9000", PROCESSOR_R9000, 4 },
715
716 /* MIPS32 */
717 { "4kc", PROCESSOR_4KC, 32 },
718 { "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */
719
720 /* MIPS32 Release 2 */
721 { "m4k", PROCESSOR_M4K, 33 },
722
723 /* MIPS64 */
724 { "5kc", PROCESSOR_5KC, 64 },
725 { "20kc", PROCESSOR_20KC, 64 },
726 { "sb1", PROCESSOR_SB1, 64 },
727 { "sr71000", PROCESSOR_SR71000, 64 },
728
729 /* End marker */
730 { 0, 0, 0 }
731 };
732
733 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
734 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
735 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
736 #endif
737
738 /* Initialize the GCC target structure. */
739 #undef TARGET_ASM_ALIGNED_HI_OP
740 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
741 #undef TARGET_ASM_ALIGNED_SI_OP
742 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
743 #undef TARGET_ASM_INTEGER
744 #define TARGET_ASM_INTEGER mips_assemble_integer
745
746 #undef TARGET_ASM_FUNCTION_PROLOGUE
747 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
748 #undef TARGET_ASM_FUNCTION_EPILOGUE
749 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
750 #undef TARGET_ASM_SELECT_RTX_SECTION
751 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
752
753 #undef TARGET_SCHED_ADJUST_COST
754 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
755 #undef TARGET_SCHED_ISSUE_RATE
756 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
757 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
758 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
759
760 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
761 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
762
763 #undef TARGET_VALID_POINTER_MODE
764 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
765 #undef TARGET_RTX_COSTS
766 #define TARGET_RTX_COSTS mips_rtx_costs
767 #undef TARGET_ADDRESS_COST
768 #define TARGET_ADDRESS_COST mips_address_cost
769
770 #undef TARGET_ENCODE_SECTION_INFO
771 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
772 #undef TARGET_IN_SMALL_DATA_P
773 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
774
775 #undef TARGET_MACHINE_DEPENDENT_REORG
776 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
777
778 #undef TARGET_ASM_FILE_START
779 #undef TARGET_ASM_FILE_END
780 #if TARGET_IRIX
781 #define TARGET_ASM_FILE_START irix_file_start
782 #define TARGET_ASM_FILE_END irix_file_end
783 #else
784 #define TARGET_ASM_FILE_START mips_file_start
785 #define TARGET_ASM_FILE_END mips_file_end
786 #endif
787 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
788 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
789
790 #if TARGET_IRIX
791 #undef TARGET_SECTION_TYPE_FLAGS
792 #define TARGET_SECTION_TYPE_FLAGS irix_section_type_flags
793 #endif
794
795 #undef TARGET_INIT_LIBFUNCS
796 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
797
798 #undef TARGET_BUILD_BUILTIN_VA_LIST
799 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
800 #undef TARGET_RETURN_IN_MSB
801 #define TARGET_RETURN_IN_MSB mips_return_in_msb
802
803 #undef TARGET_ASM_OUTPUT_MI_THUNK
804 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
805 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
806 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
807
808 struct gcc_target targetm = TARGET_INITIALIZER;
809
810 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
811
812 static enum mips_symbol_type
mips_classify_symbol(rtx x)813 mips_classify_symbol (rtx x)
814 {
815 if (GET_CODE (x) == LABEL_REF)
816 return (TARGET_ABICALLS ? SYMBOL_GOT_LOCAL : SYMBOL_GENERAL);
817
818 if (GET_CODE (x) != SYMBOL_REF)
819 abort ();
820
821 if (CONSTANT_POOL_ADDRESS_P (x))
822 {
823 if (TARGET_MIPS16)
824 return SYMBOL_CONSTANT_POOL;
825
826 if (TARGET_ABICALLS)
827 return SYMBOL_GOT_LOCAL;
828
829 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
830 return SYMBOL_SMALL_DATA;
831
832 return SYMBOL_GENERAL;
833 }
834
835 if (SYMBOL_REF_SMALL_P (x))
836 return SYMBOL_SMALL_DATA;
837
838 /* When generating mips16 code, SYMBOL_REF_FLAG indicates a string
839 in the current function's constant pool. */
840 if (TARGET_MIPS16 && SYMBOL_REF_FLAG (x))
841 return SYMBOL_CONSTANT_POOL;
842
843 if (TARGET_ABICALLS)
844 {
845 if (SYMBOL_REF_DECL (x) == 0)
846 return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
847
848 /* There are three cases to consider:
849
850 - o32 PIC (either with or without explicit relocs)
851 - n32/n64 PIC without explicit relocs
852 - n32/n64 PIC with explicit relocs
853
854 In the first case, both local and global accesses will use an
855 R_MIPS_GOT16 relocation. We must correctly predict which of
856 the two semantics (local or global) the assembler and linker
857 will apply. The choice doesn't depend on the symbol's
858 visibility, so we deliberately ignore decl_visibility and
859 binds_local_p here.
860
861 In the second case, the assembler will not use R_MIPS_GOT16
862 relocations, but it chooses between local and global accesses
863 in the same way as for o32 PIC.
864
865 In the third case we have more freedom since both forms of
866 access will work for any kind of symbol. However, there seems
867 little point in doing things differently. */
868 if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
869 return SYMBOL_GOT_GLOBAL;
870
871 return SYMBOL_GOT_LOCAL;
872 }
873
874 return SYMBOL_GENERAL;
875 }
876
877
878 /* Split X into a base and a constant offset, storing them in *BASE
879 and *OFFSET respectively. */
880
881 static void
mips_split_const(rtx x,rtx * base,HOST_WIDE_INT * offset)882 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
883 {
884 *offset = 0;
885
886 if (GET_CODE (x) == CONST)
887 x = XEXP (x, 0);
888
889 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
890 {
891 *offset += INTVAL (XEXP (x, 1));
892 x = XEXP (x, 0);
893 }
894 *base = x;
895 }
896
897
898 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
899 to the same object as SYMBOL. */
900
901 static bool
mips_offset_within_object_p(rtx symbol,HOST_WIDE_INT offset)902 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
903 {
904 if (GET_CODE (symbol) != SYMBOL_REF)
905 return false;
906
907 if (CONSTANT_POOL_ADDRESS_P (symbol)
908 && offset >= 0
909 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
910 return true;
911
912 if (SYMBOL_REF_DECL (symbol) != 0
913 && offset >= 0
914 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
915 return true;
916
917 return false;
918 }
919
920
921 /* Return true if X is a symbolic constant that can be calculated in
922 the same way as a bare symbol. If it is, store the type of the
923 symbol in *SYMBOL_TYPE. */
924
925 static bool
mips_symbolic_constant_p(rtx x,enum mips_symbol_type * symbol_type)926 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
927 {
928 HOST_WIDE_INT offset;
929
930 mips_split_const (x, &x, &offset);
931 if (UNSPEC_ADDRESS_P (x))
932 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
933 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
934 *symbol_type = mips_classify_symbol (x);
935 else
936 return false;
937
938 if (offset == 0)
939 return true;
940
941 /* Check whether a nonzero offset is valid for the underlying
942 relocations. */
943 switch (*symbol_type)
944 {
945 case SYMBOL_GENERAL:
946 /* If the target has 64-bit pointers and the object file only
947 supports 32-bit symbols, the values of those symbols will be
948 sign-extended. In this case we can't allow an arbitrary offset
949 in case the 32-bit value X + OFFSET has a different sign from X. */
950 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
951 return mips_offset_within_object_p (x, offset);
952
953 /* In other cases the relocations can handle any offset. */
954 return true;
955
956 case SYMBOL_SMALL_DATA:
957 case SYMBOL_CONSTANT_POOL:
958 /* Make sure that the offset refers to something within the
959 underlying object. This should guarantee that the final
960 PC- or GP-relative offset is within the 16-bit limit. */
961 return mips_offset_within_object_p (x, offset);
962
963 case SYMBOL_GOT_LOCAL:
964 case SYMBOL_GOTOFF_PAGE:
965 /* The linker should provide enough local GOT entries for a
966 16-bit offset. Larger offsets may lead to GOT overflow. */
967 return SMALL_OPERAND (offset);
968
969 case SYMBOL_GOT_GLOBAL:
970 case SYMBOL_GOTOFF_GLOBAL:
971 case SYMBOL_GOTOFF_CALL:
972 case SYMBOL_GOTOFF_LOADGP:
973 return false;
974 }
975 abort ();
976 }
977
978
979 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
980
981 int
mips_regno_mode_ok_for_base_p(int regno,enum machine_mode mode,int strict)982 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
983 {
984 if (regno >= FIRST_PSEUDO_REGISTER)
985 {
986 if (!strict)
987 return true;
988 regno = reg_renumber[regno];
989 }
990
991 /* These fake registers will be eliminated to either the stack or
992 hard frame pointer, both of which are usually valid base registers.
993 Reload deals with the cases where the eliminated form isn't valid. */
994 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
995 return true;
996
997 /* In mips16 mode, the stack pointer can only address word and doubleword
998 values, nothing smaller. There are two problems here:
999
1000 (a) Instantiating virtual registers can introduce new uses of the
1001 stack pointer. If these virtual registers are valid addresses,
1002 the stack pointer should be too.
1003
1004 (b) Most uses of the stack pointer are not made explicit until
1005 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1006 We don't know until that stage whether we'll be eliminating to the
1007 stack pointer (which needs the restriction) or the hard frame
1008 pointer (which doesn't).
1009
1010 All in all, it seems more consitent to only enforce this restriction
1011 during and after reload. */
1012 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1013 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1014
1015 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1016 }
1017
1018
1019 /* Return true if X is a valid base register for the given mode.
1020 Allow only hard registers if STRICT. */
1021
1022 static bool
mips_valid_base_register_p(rtx x,enum machine_mode mode,int strict)1023 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1024 {
1025 if (!strict && GET_CODE (x) == SUBREG)
1026 x = SUBREG_REG (x);
1027
1028 return (GET_CODE (x) == REG
1029 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1030 }
1031
1032
1033 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1034 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1035
1036 static bool
mips_symbolic_address_p(enum mips_symbol_type symbol_type,enum machine_mode mode)1037 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1038 enum machine_mode mode)
1039 {
1040 switch (symbol_type)
1041 {
1042 case SYMBOL_GENERAL:
1043 return !TARGET_MIPS16;
1044
1045 case SYMBOL_SMALL_DATA:
1046 return true;
1047
1048 case SYMBOL_CONSTANT_POOL:
1049 /* PC-relative addressing is only available for lw, sw, ld and sd. */
1050 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1051
1052 case SYMBOL_GOT_LOCAL:
1053 return true;
1054
1055 case SYMBOL_GOT_GLOBAL:
1056 /* The address will have to be loaded from the GOT first. */
1057 return false;
1058
1059 case SYMBOL_GOTOFF_PAGE:
1060 case SYMBOL_GOTOFF_GLOBAL:
1061 case SYMBOL_GOTOFF_CALL:
1062 case SYMBOL_GOTOFF_LOADGP:
1063 return true;
1064 }
1065 abort ();
1066 }
1067
1068
1069 /* Return true if X is a valid address for machine mode MODE. If it is,
1070 fill in INFO appropriately. STRICT is true if we should only accept
1071 hard base registers. */
1072
1073 static bool
mips_classify_address(struct mips_address_info * info,rtx x,enum machine_mode mode,int strict)1074 mips_classify_address (struct mips_address_info *info, rtx x,
1075 enum machine_mode mode, int strict)
1076 {
1077 switch (GET_CODE (x))
1078 {
1079 case REG:
1080 case SUBREG:
1081 info->type = ADDRESS_REG;
1082 info->reg = x;
1083 info->offset = const0_rtx;
1084 return mips_valid_base_register_p (info->reg, mode, strict);
1085
1086 case PLUS:
1087 info->type = ADDRESS_REG;
1088 info->reg = XEXP (x, 0);
1089 info->offset = XEXP (x, 1);
1090 return (mips_valid_base_register_p (info->reg, mode, strict)
1091 && const_arith_operand (info->offset, VOIDmode));
1092
1093 case LO_SUM:
1094 info->type = ADDRESS_LO_SUM;
1095 info->reg = XEXP (x, 0);
1096 info->offset = XEXP (x, 1);
1097 return (mips_valid_base_register_p (info->reg, mode, strict)
1098 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1099 && mips_symbolic_address_p (info->symbol_type, mode)
1100 && mips_lo_relocs[info->symbol_type] != 0);
1101
1102 case CONST_INT:
1103 /* Small-integer addresses don't occur very often, but they
1104 are legitimate if $0 is a valid base register. */
1105 info->type = ADDRESS_CONST_INT;
1106 return !TARGET_MIPS16 && SMALL_INT (x);
1107
1108 case CONST:
1109 case LABEL_REF:
1110 case SYMBOL_REF:
1111 info->type = ADDRESS_SYMBOLIC;
1112 return (mips_symbolic_constant_p (x, &info->symbol_type)
1113 && mips_symbolic_address_p (info->symbol_type, mode)
1114 && !mips_split_p[info->symbol_type]);
1115
1116 default:
1117 return false;
1118 }
1119 }
1120
1121 /* Return the number of instructions needed to load a symbol of the
1122 given type into a register. If valid in an address, the same number
1123 of instructions are needed for loads and stores. Treat extended
1124 mips16 instructions as two instructions. */
1125
1126 static int
mips_symbol_insns(enum mips_symbol_type type)1127 mips_symbol_insns (enum mips_symbol_type type)
1128 {
1129 switch (type)
1130 {
1131 case SYMBOL_GENERAL:
1132 /* In mips16 code, general symbols must be fetched from the
1133 constant pool. */
1134 if (TARGET_MIPS16)
1135 return 0;
1136
1137 /* When using 64-bit symbols, we need 5 preparatory instructions,
1138 such as:
1139
1140 lui $at,%highest(symbol)
1141 daddiu $at,$at,%higher(symbol)
1142 dsll $at,$at,16
1143 daddiu $at,$at,%hi(symbol)
1144 dsll $at,$at,16
1145
1146 The final address is then $at + %lo(symbol). With 32-bit
1147 symbols we just need a preparatory lui. */
1148 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1149
1150 case SYMBOL_SMALL_DATA:
1151 return 1;
1152
1153 case SYMBOL_CONSTANT_POOL:
1154 /* This case is for mips16 only. Assume we'll need an
1155 extended instruction. */
1156 return 2;
1157
1158 case SYMBOL_GOT_LOCAL:
1159 case SYMBOL_GOT_GLOBAL:
1160 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1161 the local/global classification is accurate. See override_options
1162 for details.
1163
1164 The worst cases are:
1165
1166 (1) For local symbols when generating o32 or o64 code. The assembler
1167 will use:
1168
1169 lw $at,%got(symbol)
1170 nop
1171
1172 ...and the final address will be $at + %lo(symbol).
1173
1174 (2) For global symbols when -mxgot. The assembler will use:
1175
1176 lui $at,%got_hi(symbol)
1177 (d)addu $at,$at,$gp
1178
1179 ...and the final address will be $at + %got_lo(symbol). */
1180 return 3;
1181
1182 case SYMBOL_GOTOFF_PAGE:
1183 case SYMBOL_GOTOFF_GLOBAL:
1184 case SYMBOL_GOTOFF_CALL:
1185 case SYMBOL_GOTOFF_LOADGP:
1186 /* Check whether the offset is a 16- or 32-bit value. */
1187 return mips_split_p[type] ? 2 : 1;
1188 }
1189 abort ();
1190 }
1191
1192
1193 /* Return true if a value at OFFSET bytes from BASE can be accessed
1194 using an unextended mips16 instruction. MODE is the mode of the
1195 value.
1196
1197 Usually the offset in an unextended instruction is a 5-bit field.
1198 The offset is unsigned and shifted left once for HIs, twice
1199 for SIs, and so on. An exception is SImode accesses off the
1200 stack pointer, which have an 8-bit immediate field. */
1201
1202 static bool
mips16_unextended_reference_p(enum machine_mode mode,rtx base,rtx offset)1203 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1204 {
1205 if (TARGET_MIPS16
1206 && GET_CODE (offset) == CONST_INT
1207 && INTVAL (offset) >= 0
1208 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1209 {
1210 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1211 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1212 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1213 }
1214 return false;
1215 }
1216
1217
1218 /* Return the number of instructions needed to load or store a value
1219 of mode MODE at X. Return 0 if X isn't valid for MODE.
1220
1221 For mips16 code, count extended instructions as two instructions. */
1222
1223 int
mips_address_insns(rtx x,enum machine_mode mode)1224 mips_address_insns (rtx x, enum machine_mode mode)
1225 {
1226 struct mips_address_info addr;
1227 int factor;
1228
1229 if (mode == BLKmode)
1230 /* BLKmode is used for single unaligned loads and stores. */
1231 factor = 1;
1232 else
1233 /* Each word of a multi-word value will be accessed individually. */
1234 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1235
1236 if (mips_classify_address (&addr, x, mode, false))
1237 switch (addr.type)
1238 {
1239 case ADDRESS_REG:
1240 if (TARGET_MIPS16
1241 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1242 return factor * 2;
1243 return factor;
1244
1245 case ADDRESS_LO_SUM:
1246 return (TARGET_MIPS16 ? factor * 2 : factor);
1247
1248 case ADDRESS_CONST_INT:
1249 return factor;
1250
1251 case ADDRESS_SYMBOLIC:
1252 return factor * mips_symbol_insns (addr.symbol_type);
1253 }
1254 return 0;
1255 }
1256
1257
1258 /* Likewise for constant X. */
1259
1260 int
mips_const_insns(rtx x)1261 mips_const_insns (rtx x)
1262 {
1263 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1264 enum mips_symbol_type symbol_type;
1265 HOST_WIDE_INT offset;
1266
1267 switch (GET_CODE (x))
1268 {
1269 case CONSTANT_P_RTX:
1270 return 1;
1271
1272 case HIGH:
1273 if (TARGET_MIPS16
1274 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1275 || !mips_split_p[symbol_type])
1276 return 0;
1277
1278 return 1;
1279
1280 case CONST_INT:
1281 if (TARGET_MIPS16)
1282 /* Unsigned 8-bit constants can be loaded using an unextended
1283 LI instruction. Unsigned 16-bit constants can be loaded
1284 using an extended LI. Negative constants must be loaded
1285 using LI and then negated. */
1286 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1287 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1288 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1289 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1290 : 0);
1291
1292 return mips_build_integer (codes, INTVAL (x));
1293
1294 case CONST_DOUBLE:
1295 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1296
1297 case CONST:
1298 if (CONST_GP_P (x))
1299 return 1;
1300
1301 /* See if we can refer to X directly. */
1302 if (mips_symbolic_constant_p (x, &symbol_type))
1303 return mips_symbol_insns (symbol_type);
1304
1305 /* Otherwise try splitting the constant into a base and offset.
1306 16-bit offsets can be added using an extra addiu. Larger offsets
1307 must be calculated separately and then added to the base. */
1308 mips_split_const (x, &x, &offset);
1309 if (offset != 0)
1310 {
1311 int n = mips_const_insns (x);
1312 if (n != 0)
1313 {
1314 if (SMALL_OPERAND (offset))
1315 return n + 1;
1316 else
1317 return n + 1 + mips_build_integer (codes, offset);
1318 }
1319 }
1320 return 0;
1321
1322 case SYMBOL_REF:
1323 case LABEL_REF:
1324 return mips_symbol_insns (mips_classify_symbol (x));
1325
1326 default:
1327 return 0;
1328 }
1329 }
1330
1331
1332 /* Return the number of instructions needed for memory reference X.
1333 Count extended mips16 instructions as two instructions. */
1334
1335 int
mips_fetch_insns(rtx x)1336 mips_fetch_insns (rtx x)
1337 {
1338 if (GET_CODE (x) != MEM)
1339 abort ();
1340
1341 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1342 }
1343
1344
1345 /* Return truth value of whether OP can be used as an operands
1346 where a register or 16 bit unsigned integer is needed. */
1347
1348 int
uns_arith_operand(rtx op,enum machine_mode mode)1349 uns_arith_operand (rtx op, enum machine_mode mode)
1350 {
1351 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
1352 return 1;
1353
1354 return register_operand (op, mode);
1355 }
1356
1357
1358 /* True if OP can be treated as a signed 16-bit constant. */
1359
1360 int
const_arith_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1361 const_arith_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1362 {
1363 return GET_CODE (op) == CONST_INT && SMALL_INT (op);
1364 }
1365
1366
1367 /* Return true if OP is a register operand or a signed 16-bit constant. */
1368
1369 int
arith_operand(rtx op,enum machine_mode mode)1370 arith_operand (rtx op, enum machine_mode mode)
1371 {
1372 return const_arith_operand (op, mode) || register_operand (op, mode);
1373 }
1374
1375 /* Return truth value of whether OP is an integer which fits in 16 bits. */
1376
1377 int
small_int(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1378 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1379 {
1380 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1381 }
1382
1383 /* Return truth value of whether OP is a register or the constant 0.
1384 Do not accept 0 in mips16 mode since $0 is not one of the core 8
1385 registers. */
1386
1387 int
reg_or_0_operand(rtx op,enum machine_mode mode)1388 reg_or_0_operand (rtx op, enum machine_mode mode)
1389 {
1390 switch (GET_CODE (op))
1391 {
1392 case CONST_INT:
1393 if (TARGET_MIPS16)
1394 return 0;
1395 return INTVAL (op) == 0;
1396
1397 case CONST_DOUBLE:
1398 if (TARGET_MIPS16)
1399 return 0;
1400 return op == CONST0_RTX (mode);
1401
1402 default:
1403 return register_operand (op, mode);
1404 }
1405 }
1406
1407 /* Accept a register or the floating point constant 1 in the appropriate mode. */
1408
1409 int
reg_or_const_float_1_operand(rtx op,enum machine_mode mode)1410 reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
1411 {
1412 REAL_VALUE_TYPE d;
1413
1414 switch (GET_CODE (op))
1415 {
1416 case CONST_DOUBLE:
1417 if (mode != GET_MODE (op)
1418 || (mode != DFmode && mode != SFmode))
1419 return 0;
1420
1421 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1422 return REAL_VALUES_EQUAL (d, dconst1);
1423
1424 default:
1425 return register_operand (op, mode);
1426 }
1427 }
1428
1429 /* Accept the floating point constant 1 in the appropriate mode. */
1430
1431 int
const_float_1_operand(rtx op,enum machine_mode mode)1432 const_float_1_operand (rtx op, enum machine_mode mode)
1433 {
1434 REAL_VALUE_TYPE d;
1435
1436 if (GET_CODE (op) != CONST_DOUBLE
1437 || mode != GET_MODE (op)
1438 || (mode != DFmode && mode != SFmode))
1439 return 0;
1440
1441 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1442
1443 return REAL_VALUES_EQUAL (d, dconst1);
1444 }
1445
1446 /* Return true if OP is either the HI or LO register. */
1447
1448 int
hilo_operand(rtx op,enum machine_mode mode)1449 hilo_operand (rtx op, enum machine_mode mode)
1450 {
1451 return ((mode == VOIDmode || mode == GET_MODE (op))
1452 && REG_P (op) && MD_REG_P (REGNO (op)));
1453 }
1454
1455 /* Return true if OP is an extension operator. */
1456
1457 int
extend_operator(rtx op,enum machine_mode mode)1458 extend_operator (rtx op, enum machine_mode mode)
1459 {
1460 return ((mode == VOIDmode || mode == GET_MODE (op))
1461 && (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND));
1462 }
1463
1464 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1465
1466 int
equality_op(rtx op,enum machine_mode mode)1467 equality_op (rtx op, enum machine_mode mode)
1468 {
1469 if (mode != GET_MODE (op))
1470 return 0;
1471
1472 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
1473 }
1474
1475 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1476
1477 int
cmp_op(rtx op,enum machine_mode mode)1478 cmp_op (rtx op, enum machine_mode mode)
1479 {
1480 if (mode != GET_MODE (op))
1481 return 0;
1482
1483 return GET_RTX_CLASS (GET_CODE (op)) == '<';
1484 }
1485
1486 /* Return nonzero if the code is a relational operation suitable for a
1487 conditional trap instruction (only EQ, NE, LT, LTU, GE, GEU).
1488 We need this in the insn that expands `trap_if' in order to prevent
1489 combine from erroneously altering the condition. */
1490
1491 int
trap_cmp_op(rtx op,enum machine_mode mode)1492 trap_cmp_op (rtx op, enum machine_mode mode)
1493 {
1494 if (mode != GET_MODE (op))
1495 return 0;
1496
1497 switch (GET_CODE (op))
1498 {
1499 case EQ:
1500 case NE:
1501 case LT:
1502 case LTU:
1503 case GE:
1504 case GEU:
1505 return 1;
1506
1507 default:
1508 return 0;
1509 }
1510 }
1511
1512 /* Return nonzero if the operand is either the PC or a label_ref. */
1513
1514 int
pc_or_label_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1515 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1516 {
1517 if (op == pc_rtx)
1518 return 1;
1519
1520 if (GET_CODE (op) == LABEL_REF)
1521 return 1;
1522
1523 return 0;
1524 }
1525
1526 /* Test for a valid call address. */
1527
1528 int
call_insn_operand(rtx op,enum machine_mode mode)1529 call_insn_operand (rtx op, enum machine_mode mode)
1530 {
1531 enum mips_symbol_type symbol_type;
1532
1533 if (mips_symbolic_constant_p (op, &symbol_type))
1534 switch (symbol_type)
1535 {
1536 case SYMBOL_GENERAL:
1537 /* If -mlong-calls, force all calls to use register addressing. */
1538 return !TARGET_LONG_CALLS;
1539
1540 case SYMBOL_GOT_GLOBAL:
1541 /* Without explicit relocs, there is no special syntax for
1542 loading the address of a call destination into a register.
1543 Using "la $25,foo; jal $25" would prevent the lazy binding
1544 of "foo", so keep the address of global symbols with the
1545 jal macro. */
1546 return !TARGET_EXPLICIT_RELOCS;
1547
1548 default:
1549 return false;
1550 }
1551 return register_operand (op, mode);
1552 }
1553
1554
1555 /* Return nonzero if OP is valid as a source operand for a move
1556 instruction. */
1557
1558 int
move_operand(rtx op,enum machine_mode mode)1559 move_operand (rtx op, enum machine_mode mode)
1560 {
1561 enum mips_symbol_type symbol_type;
1562
1563 if (!general_operand (op, mode))
1564 return false;
1565
1566 switch (GET_CODE (op))
1567 {
1568 case CONST_INT:
1569 /* When generating mips16 code, LEGITIMATE_CONSTANT_P rejects
1570 CONST_INTs that can't be loaded using simple insns. */
1571 if (TARGET_MIPS16)
1572 return true;
1573
1574 /* Otherwise check whether the constant can be loaded in a single
1575 instruction. */
1576 return LUI_INT (op) || SMALL_INT (op) || SMALL_INT_UNSIGNED (op);
1577
1578 case CONST:
1579 case SYMBOL_REF:
1580 case LABEL_REF:
1581 if (CONST_GP_P (op))
1582 return true;
1583
1584 return (mips_symbolic_constant_p (op, &symbol_type)
1585 && !mips_split_p[symbol_type]);
1586
1587 default:
1588 return true;
1589 }
1590 }
1591
1592
1593 /* Accept any operand that can appear in a mips16 constant table
1594 instruction. We can't use any of the standard operand functions
1595 because for these instructions we accept values that are not
1596 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1597
1598 int
consttable_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1599 consttable_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1600 {
1601 return CONSTANT_P (op);
1602 }
1603
1604 /* Return 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1605 possibly with an offset. */
1606
1607 int
symbolic_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1608 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1609 {
1610 enum mips_symbol_type symbol_type;
1611
1612 return mips_symbolic_constant_p (op, &symbol_type);
1613 }
1614
1615
1616 /* Return true if we're generating PIC and OP is a global symbol. */
1617
1618 int
global_got_operand(rtx op,enum machine_mode mode)1619 global_got_operand (rtx op, enum machine_mode mode)
1620 {
1621 enum mips_symbol_type symbol_type;
1622
1623 return ((mode == VOIDmode || mode == GET_MODE (op))
1624 && mips_symbolic_constant_p (op, &symbol_type)
1625 && symbol_type == SYMBOL_GOT_GLOBAL);
1626 }
1627
1628
1629 /* Likewise for local symbols. */
1630
1631 int
local_got_operand(rtx op,enum machine_mode mode)1632 local_got_operand (rtx op, enum machine_mode mode)
1633 {
1634 enum mips_symbol_type symbol_type;
1635
1636 return ((mode == VOIDmode || mode == GET_MODE (op))
1637 && mips_symbolic_constant_p (op, &symbol_type)
1638 && symbol_type == SYMBOL_GOT_LOCAL);
1639 }
1640
1641
1642 /* Return true if OP is a memory reference that uses the stack pointer
1643 as a base register. */
1644
1645 int
stack_operand(rtx op,enum machine_mode mode)1646 stack_operand (rtx op, enum machine_mode mode)
1647 {
1648 struct mips_address_info addr;
1649
1650 return ((mode == VOIDmode || mode == GET_MODE (op))
1651 && GET_CODE (op) == MEM
1652 && mips_classify_address (&addr, XEXP (op, 0), GET_MODE (op), false)
1653 && addr.type == ADDRESS_REG
1654 && addr.reg == stack_pointer_rtx);
1655 }
1656
1657
1658 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1659 returns a nonzero value if X is a legitimate address for a memory
1660 operand of the indicated MODE. STRICT is nonzero if this function
1661 is called during reload. */
1662
1663 bool
mips_legitimate_address_p(enum machine_mode mode,rtx x,int strict)1664 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1665 {
1666 struct mips_address_info addr;
1667
1668 return mips_classify_address (&addr, x, mode, strict);
1669 }
1670
1671
1672 /* Copy VALUE to a register and return that register. If new psuedos
1673 are allowed, copy it into a new register, otherwise use DEST. */
1674
1675 static rtx
mips_force_temporary(rtx dest,rtx value)1676 mips_force_temporary (rtx dest, rtx value)
1677 {
1678 if (!no_new_pseudos)
1679 return force_reg (Pmode, value);
1680 else
1681 {
1682 emit_move_insn (copy_rtx (dest), value);
1683 return dest;
1684 }
1685 }
1686
1687
1688 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1689 and is used to load the high part into a register. */
1690
1691 static rtx
mips_split_symbol(rtx temp,rtx addr)1692 mips_split_symbol (rtx temp, rtx addr)
1693 {
1694 rtx high;
1695
1696 if (TARGET_MIPS16)
1697 high = mips16_gp_pseudo_reg ();
1698 else
1699 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1700 return gen_rtx_LO_SUM (Pmode, high, addr);
1701 }
1702
1703
1704 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1705 type SYMBOL_TYPE. */
1706
1707 static rtx
mips_unspec_address(rtx address,enum mips_symbol_type symbol_type)1708 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1709 {
1710 rtx base;
1711 HOST_WIDE_INT offset;
1712
1713 mips_split_const (address, &base, &offset);
1714 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1715 UNSPEC_ADDRESS_FIRST + symbol_type);
1716 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1717 }
1718
1719
1720 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1721 high part to BASE and return the result. Just return BASE otherwise.
1722 TEMP is available as a temporary register if needed.
1723
1724 The returned expression can be used as the first operand to a LO_SUM. */
1725
1726 static rtx
mips_unspec_offset_high(rtx temp,rtx base,rtx addr,enum mips_symbol_type symbol_type)1727 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1728 enum mips_symbol_type symbol_type)
1729 {
1730 if (mips_split_p[symbol_type])
1731 {
1732 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1733 addr = mips_force_temporary (temp, addr);
1734 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1735 }
1736 return base;
1737 }
1738
1739
1740 /* Return a memory reference for the GOT slot whose offset is given by
1741 mips_unspec_address (ADDR, SYMBOL_TYPE). Register BASE contains the
1742 high part of the offset plus $gp. */
1743
1744 static rtx
mips_load_got(rtx base,rtx addr,enum mips_symbol_type symbol_type)1745 mips_load_got (rtx base, rtx addr, enum mips_symbol_type symbol_type)
1746 {
1747 rtx mem, offset;
1748
1749 offset = mips_unspec_address (addr, symbol_type);
1750 mem = gen_rtx_MEM (ptr_mode, gen_rtx_LO_SUM (Pmode, base, offset));
1751 set_mem_alias_set (mem, mips_got_alias_set);
1752
1753 /* GOT entries are constant and references to them can't trap. */
1754 RTX_UNCHANGING_P (mem) = 1;
1755 MEM_NOTRAP_P (mem) = 1;
1756
1757 return mem;
1758 }
1759
1760
1761 /* Return the offset of ADDR's GOT entry from _gp. ADDR is a
1762 global_got_operand. */
1763
1764 rtx
mips_gotoff_global(rtx addr)1765 mips_gotoff_global (rtx addr)
1766 {
1767 return mips_unspec_address (addr, SYMBOL_GOTOFF_GLOBAL);
1768 }
1769
1770
1771 /* Fetch the high part of local_got_operand ADDR from the GOT. */
1772
1773 rtx
mips_load_got_page(rtx addr)1774 mips_load_got_page (rtx addr)
1775 {
1776 return mips_load_got (pic_offset_table_rtx, addr, SYMBOL_GOTOFF_PAGE);
1777 }
1778
1779
1780 /* Fetch the address of global_got_operand ADDR from the GOT. BASE is a
1781 register that holds the address _gp + %got_hi(ADDR). */
1782
1783 rtx
mips_load_got_global(rtx base,rtx addr)1784 mips_load_got_global (rtx base, rtx addr)
1785 {
1786 return mips_load_got (base, addr, SYMBOL_GOTOFF_GLOBAL);
1787 }
1788
1789
1790 /* Return a legitimate address for REG + OFFSET. This function will
1791 create a temporary register if OFFSET is not a SMALL_OPERAND. */
1792
1793 static rtx
mips_add_offset(rtx reg,HOST_WIDE_INT offset)1794 mips_add_offset (rtx reg, HOST_WIDE_INT offset)
1795 {
1796 if (!SMALL_OPERAND (offset))
1797 reg = expand_simple_binop (GET_MODE (reg), PLUS,
1798 GEN_INT (CONST_HIGH_PART (offset)),
1799 reg, NULL, 0, OPTAB_WIDEN);
1800
1801 return plus_constant (reg, CONST_LOW_PART (offset));
1802 }
1803
1804
1805 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
1806 be legitimized in a way that the generic machinery might not expect,
1807 put the new address in *XLOC and return true. MODE is the mode of
1808 the memory being accessed. */
1809
1810 bool
mips_legitimize_address(rtx * xloc,enum machine_mode mode)1811 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
1812 {
1813 enum mips_symbol_type symbol_type;
1814
1815 /* See if the address can split into a high part and a LO_SUM. */
1816 if (mips_symbolic_constant_p (*xloc, &symbol_type)
1817 && mips_symbolic_address_p (symbol_type, mode)
1818 && mips_split_p[symbol_type])
1819 {
1820 *xloc = mips_split_symbol (0, *xloc);
1821 return true;
1822 }
1823
1824 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
1825 {
1826 /* Handle REG + CONSTANT using mips_add_offset. */
1827 rtx reg;
1828
1829 reg = XEXP (*xloc, 0);
1830 if (!mips_valid_base_register_p (reg, mode, 0))
1831 reg = copy_to_mode_reg (Pmode, reg);
1832 *xloc = mips_add_offset (reg, INTVAL (XEXP (*xloc, 1)));
1833 return true;
1834 }
1835
1836 return false;
1837 }
1838
1839
1840 /* Subroutine of mips_build_integer (with the same interface).
1841 Assume that the final action in the sequence should be a left shift. */
1842
1843 static unsigned int
mips_build_shift(struct mips_integer_op * codes,HOST_WIDE_INT value)1844 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1845 {
1846 unsigned int i, shift;
1847
1848 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1849 since signed numbers are easier to load than unsigned ones. */
1850 shift = 0;
1851 while ((value & 1) == 0)
1852 value /= 2, shift++;
1853
1854 i = mips_build_integer (codes, value);
1855 codes[i].code = ASHIFT;
1856 codes[i].value = shift;
1857 return i + 1;
1858 }
1859
1860
1861 /* As for mips_build_shift, but assume that the final action will be
1862 an IOR or PLUS operation. */
1863
1864 static unsigned int
mips_build_lower(struct mips_integer_op * codes,unsigned HOST_WIDE_INT value)1865 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1866 {
1867 unsigned HOST_WIDE_INT high;
1868 unsigned int i;
1869
1870 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1871 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1872 {
1873 /* The constant is too complex to load with a simple lui/ori pair
1874 so our goal is to clear as many trailing zeros as possible.
1875 In this case, we know bit 16 is set and that the low 16 bits
1876 form a negative number. If we subtract that number from VALUE,
1877 we will clear at least the lowest 17 bits, maybe more. */
1878 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1879 codes[i].code = PLUS;
1880 codes[i].value = CONST_LOW_PART (value);
1881 }
1882 else
1883 {
1884 i = mips_build_integer (codes, high);
1885 codes[i].code = IOR;
1886 codes[i].value = value & 0xffff;
1887 }
1888 return i + 1;
1889 }
1890
1891
1892 /* Fill CODES with a sequence of rtl operations to load VALUE.
1893 Return the number of operations needed. */
1894
1895 static unsigned int
mips_build_integer(struct mips_integer_op * codes,unsigned HOST_WIDE_INT value)1896 mips_build_integer (struct mips_integer_op *codes,
1897 unsigned HOST_WIDE_INT value)
1898 {
1899 if (SMALL_OPERAND (value)
1900 || SMALL_OPERAND_UNSIGNED (value)
1901 || LUI_OPERAND (value))
1902 {
1903 /* The value can be loaded with a single instruction. */
1904 codes[0].code = NIL;
1905 codes[0].value = value;
1906 return 1;
1907 }
1908 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1909 {
1910 /* Either the constant is a simple LUI/ORI combination or its
1911 lowest bit is set. We don't want to shift in this case. */
1912 return mips_build_lower (codes, value);
1913 }
1914 else if ((value & 0xffff) == 0)
1915 {
1916 /* The constant will need at least three actions. The lowest
1917 16 bits are clear, so the final action will be a shift. */
1918 return mips_build_shift (codes, value);
1919 }
1920 else
1921 {
1922 /* The final action could be a shift, add or inclusive OR.
1923 Rather than use a complex condition to select the best
1924 approach, try both mips_build_shift and mips_build_lower
1925 and pick the one that gives the shortest sequence.
1926 Note that this case is only used once per constant. */
1927 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1928 unsigned int cost, alt_cost;
1929
1930 cost = mips_build_shift (codes, value);
1931 alt_cost = mips_build_lower (alt_codes, value);
1932 if (alt_cost < cost)
1933 {
1934 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1935 cost = alt_cost;
1936 }
1937 return cost;
1938 }
1939 }
1940
1941
1942 /* Move VALUE into register DEST. */
1943
1944 static void
mips_move_integer(rtx dest,unsigned HOST_WIDE_INT value)1945 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
1946 {
1947 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1948 enum machine_mode mode;
1949 unsigned int i, cost;
1950 rtx x;
1951
1952 mode = GET_MODE (dest);
1953 cost = mips_build_integer (codes, value);
1954
1955 /* Apply each binary operation to X. Invariant: X is a legitimate
1956 source operand for a SET pattern. */
1957 x = GEN_INT (codes[0].value);
1958 for (i = 1; i < cost; i++)
1959 {
1960 if (no_new_pseudos)
1961 emit_move_insn (dest, x), x = dest;
1962 else
1963 x = force_reg (mode, x);
1964 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
1965 }
1966
1967 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1968 }
1969
1970
1971 /* Subroutine of mips_legitimize_move. Move constant SRC into register
1972 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1973 move_operand. */
1974
1975 static void
mips_legitimize_const_move(enum machine_mode mode,rtx dest,rtx src)1976 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
1977 {
1978 rtx base;
1979 HOST_WIDE_INT offset;
1980 enum mips_symbol_type symbol_type;
1981
1982 /* Split moves of big integers into smaller pieces. In mips16 code,
1983 it's better to force the constant into memory instead. */
1984 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
1985 {
1986 mips_move_integer (dest, INTVAL (src));
1987 return;
1988 }
1989
1990 /* See if the symbol can be split. For mips16, this is often worse than
1991 forcing it in the constant pool since it needs the single-register form
1992 of addiu or daddiu. */
1993 if (!TARGET_MIPS16
1994 && mips_symbolic_constant_p (src, &symbol_type)
1995 && mips_split_p[symbol_type])
1996 {
1997 emit_move_insn (dest, mips_split_symbol (dest, src));
1998 return;
1999 }
2000
2001 /* If we have (const (plus symbol offset)), load the symbol first
2002 and then add in the offset. This is usually better than forcing
2003 the constant into memory, at least in non-mips16 code. */
2004 mips_split_const (src, &base, &offset);
2005 if (!TARGET_MIPS16
2006 && offset != 0
2007 && (!no_new_pseudos || SMALL_OPERAND (offset)))
2008 {
2009 base = mips_force_temporary (dest, base);
2010 emit_move_insn (dest, mips_add_offset (base, offset));
2011 return;
2012 }
2013
2014 src = force_const_mem (mode, src);
2015
2016 /* When using explicit relocs, constant pool references are sometimes
2017 not legitimate addresses. */
2018 if (!memory_operand (src, VOIDmode))
2019 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2020 emit_move_insn (dest, src);
2021 }
2022
2023
2024 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2025 sequence that is valid. */
2026
2027 bool
mips_legitimize_move(enum machine_mode mode,rtx dest,rtx src)2028 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2029 {
2030 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2031 {
2032 emit_move_insn (dest, force_reg (mode, src));
2033 return true;
2034 }
2035
2036 /* The source of an SImode move must be a move_operand. Likewise
2037 DImode moves on 64-bit targets. We need to deal with constants
2038 that would be legitimate immediate_operands but not legitimate
2039 move_operands. */
2040 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2041 && CONSTANT_P (src)
2042 && !move_operand (src, mode))
2043 {
2044 mips_legitimize_const_move (mode, dest, src);
2045 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2046 return true;
2047 }
2048 return false;
2049 }
2050
2051 /* We need a lot of little routines to check constant values on the
2052 mips16. These are used to figure out how long the instruction will
2053 be. It would be much better to do this using constraints, but
2054 there aren't nearly enough letters available. */
2055
2056 static int
m16_check_op(rtx op,int low,int high,int mask)2057 m16_check_op (rtx op, int low, int high, int mask)
2058 {
2059 return (GET_CODE (op) == CONST_INT
2060 && INTVAL (op) >= low
2061 && INTVAL (op) <= high
2062 && (INTVAL (op) & mask) == 0);
2063 }
2064
2065 int
m16_uimm3_b(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2066 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2067 {
2068 return m16_check_op (op, 0x1, 0x8, 0);
2069 }
2070
2071 int
m16_simm4_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2072 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2073 {
2074 return m16_check_op (op, - 0x8, 0x7, 0);
2075 }
2076
2077 int
m16_nsimm4_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2078 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2079 {
2080 return m16_check_op (op, - 0x7, 0x8, 0);
2081 }
2082
2083 int
m16_simm5_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2084 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2085 {
2086 return m16_check_op (op, - 0x10, 0xf, 0);
2087 }
2088
2089 int
m16_nsimm5_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2090 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2091 {
2092 return m16_check_op (op, - 0xf, 0x10, 0);
2093 }
2094
2095 int
m16_uimm5_4(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2096 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2097 {
2098 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2099 }
2100
2101 int
m16_nuimm5_4(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2102 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2103 {
2104 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2105 }
2106
2107 int
m16_simm8_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2108 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2109 {
2110 return m16_check_op (op, - 0x80, 0x7f, 0);
2111 }
2112
2113 int
m16_nsimm8_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2114 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2115 {
2116 return m16_check_op (op, - 0x7f, 0x80, 0);
2117 }
2118
2119 int
m16_uimm8_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2120 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2121 {
2122 return m16_check_op (op, 0x0, 0xff, 0);
2123 }
2124
2125 int
m16_nuimm8_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2126 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2127 {
2128 return m16_check_op (op, - 0xff, 0x0, 0);
2129 }
2130
2131 int
m16_uimm8_m1_1(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2132 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2133 {
2134 return m16_check_op (op, - 0x1, 0xfe, 0);
2135 }
2136
2137 int
m16_uimm8_4(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2138 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2139 {
2140 return m16_check_op (op, 0x0, 0xff << 2, 3);
2141 }
2142
2143 int
m16_nuimm8_4(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2144 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2145 {
2146 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2147 }
2148
2149 int
m16_simm8_8(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2150 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2151 {
2152 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2153 }
2154
2155 int
m16_nsimm8_8(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2156 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2157 {
2158 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2159 }
2160
2161 /* References to the string table on the mips16 only use a small
2162 offset if the function is small. We can't check for LABEL_REF here,
2163 because the offset is always large if the label is before the
2164 referencing instruction. */
2165
2166 int
m16_usym8_4(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2167 m16_usym8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2168 {
2169 if (GET_CODE (op) == SYMBOL_REF
2170 && SYMBOL_REF_FLAG (op)
2171 && cfun->machine->insns_len > 0
2172 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
2173 < 4 * 0x100))
2174 {
2175 struct string_constant *l;
2176
2177 /* Make sure this symbol is on thelist of string constants to be
2178 output for this function. It is possible that it has already
2179 been output, in which case this requires a large offset. */
2180 for (l = string_constants; l != NULL; l = l->next)
2181 if (strcmp (l->label, XSTR (op, 0)) == 0)
2182 return 1;
2183 }
2184
2185 return 0;
2186 }
2187
2188 int
m16_usym5_4(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)2189 m16_usym5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2190 {
2191 if (GET_CODE (op) == SYMBOL_REF
2192 && SYMBOL_REF_FLAG (op)
2193 && cfun->machine->insns_len > 0
2194 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
2195 < 4 * 0x20))
2196 {
2197 struct string_constant *l;
2198
2199 /* Make sure this symbol is on thelist of string constants to be
2200 output for this function. It is possible that it has already
2201 been output, in which case this requires a large offset. */
2202 for (l = string_constants; l != NULL; l = l->next)
2203 if (strcmp (l->label, XSTR (op, 0)) == 0)
2204 return 1;
2205 }
2206
2207 return 0;
2208 }
2209
2210 static bool
mips_rtx_costs(rtx x,int code,int outer_code,int * total)2211 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2212 {
2213 enum machine_mode mode = GET_MODE (x);
2214
2215 switch (code)
2216 {
2217 case CONST_INT:
2218 if (!TARGET_MIPS16)
2219 {
2220 /* Always return 0, since we don't have different sized
2221 instructions, hence different costs according to Richard
2222 Kenner */
2223 *total = 0;
2224 return true;
2225 }
2226
2227 /* A number between 1 and 8 inclusive is efficient for a shift.
2228 Otherwise, we will need an extended instruction. */
2229 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2230 || (outer_code) == LSHIFTRT)
2231 {
2232 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2233 *total = 0;
2234 else
2235 *total = COSTS_N_INSNS (1);
2236 return true;
2237 }
2238
2239 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2240 if ((outer_code) == XOR
2241 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2242 {
2243 *total = 0;
2244 return true;
2245 }
2246
2247 /* We may be able to use slt or sltu for a comparison with a
2248 signed 16 bit value. (The boundary conditions aren't quite
2249 right, but this is just a heuristic anyhow.) */
2250 if (((outer_code) == LT || (outer_code) == LE
2251 || (outer_code) == GE || (outer_code) == GT
2252 || (outer_code) == LTU || (outer_code) == LEU
2253 || (outer_code) == GEU || (outer_code) == GTU)
2254 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2255 {
2256 *total = 0;
2257 return true;
2258 }
2259
2260 /* Equality comparisons with 0 are cheap. */
2261 if (((outer_code) == EQ || (outer_code) == NE)
2262 && INTVAL (x) == 0)
2263 {
2264 *total = 0;
2265 return true;
2266 }
2267
2268 /* Otherwise fall through to the handling below. */
2269
2270 case CONST:
2271 case SYMBOL_REF:
2272 case LABEL_REF:
2273 case CONST_DOUBLE:
2274 if (LEGITIMATE_CONSTANT_P (x))
2275 {
2276 *total = COSTS_N_INSNS (1);
2277 return true;
2278 }
2279 else
2280 {
2281 /* The value will need to be fetched from the constant pool. */
2282 *total = CONSTANT_POOL_COST;
2283 return true;
2284 }
2285
2286 case MEM:
2287 {
2288 /* If the address is legitimate, return the number of
2289 instructions it needs, otherwise use the default handling. */
2290 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2291 if (n > 0)
2292 {
2293 *total = COSTS_N_INSNS (1 + n);
2294 return true;
2295 }
2296 return false;
2297 }
2298
2299 case FFS:
2300 *total = COSTS_N_INSNS (6);
2301 return true;
2302
2303 case NOT:
2304 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2305 return true;
2306
2307 case AND:
2308 case IOR:
2309 case XOR:
2310 if (mode == DImode && !TARGET_64BIT)
2311 {
2312 *total = COSTS_N_INSNS (2);
2313 return true;
2314 }
2315 return false;
2316
2317 case ASHIFT:
2318 case ASHIFTRT:
2319 case LSHIFTRT:
2320 if (mode == DImode && !TARGET_64BIT)
2321 {
2322 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2323 ? 4 : 12);
2324 return true;
2325 }
2326 return false;
2327
2328 case ABS:
2329 if (mode == SFmode || mode == DFmode)
2330 *total = COSTS_N_INSNS (1);
2331 else
2332 *total = COSTS_N_INSNS (4);
2333 return true;
2334
2335 case LO_SUM:
2336 *total = COSTS_N_INSNS (1);
2337 return true;
2338
2339 case PLUS:
2340 case MINUS:
2341 if (mode == SFmode || mode == DFmode)
2342 {
2343 if (TUNE_MIPS3000 || TUNE_MIPS3900)
2344 *total = COSTS_N_INSNS (2);
2345 else if (TUNE_MIPS6000)
2346 *total = COSTS_N_INSNS (3);
2347 else
2348 *total = COSTS_N_INSNS (6);
2349 return true;
2350 }
2351 if (mode == DImode && !TARGET_64BIT)
2352 {
2353 *total = COSTS_N_INSNS (4);
2354 return true;
2355 }
2356 return false;
2357
2358 case NEG:
2359 if (mode == DImode && !TARGET_64BIT)
2360 {
2361 *total = 4;
2362 return true;
2363 }
2364 return false;
2365
2366 case MULT:
2367 if (mode == SFmode)
2368 {
2369 if (TUNE_MIPS3000
2370 || TUNE_MIPS3900
2371 || TUNE_MIPS5000)
2372 *total = COSTS_N_INSNS (4);
2373 else if (TUNE_MIPS6000
2374 || TUNE_MIPS5400
2375 || TUNE_MIPS5500)
2376 *total = COSTS_N_INSNS (5);
2377 else
2378 *total = COSTS_N_INSNS (7);
2379 return true;
2380 }
2381
2382 if (mode == DFmode)
2383 {
2384 if (TUNE_MIPS3000
2385 || TUNE_MIPS3900
2386 || TUNE_MIPS5000)
2387 *total = COSTS_N_INSNS (5);
2388 else if (TUNE_MIPS6000
2389 || TUNE_MIPS5400
2390 || TUNE_MIPS5500)
2391 *total = COSTS_N_INSNS (6);
2392 else
2393 *total = COSTS_N_INSNS (8);
2394 return true;
2395 }
2396
2397 if (TUNE_MIPS3000)
2398 *total = COSTS_N_INSNS (12);
2399 else if (TUNE_MIPS3900)
2400 *total = COSTS_N_INSNS (2);
2401 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2402 *total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
2403 else if (TUNE_MIPS7000)
2404 *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
2405 else if (TUNE_MIPS9000)
2406 *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
2407 else if (TUNE_MIPS6000)
2408 *total = COSTS_N_INSNS (17);
2409 else if (TUNE_MIPS5000)
2410 *total = COSTS_N_INSNS (5);
2411 else
2412 *total = COSTS_N_INSNS (10);
2413 return true;
2414
2415 case DIV:
2416 case MOD:
2417 if (mode == SFmode)
2418 {
2419 if (TUNE_MIPS3000
2420 || TUNE_MIPS3900)
2421 *total = COSTS_N_INSNS (12);
2422 else if (TUNE_MIPS6000)
2423 *total = COSTS_N_INSNS (15);
2424 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2425 *total = COSTS_N_INSNS (30);
2426 else
2427 *total = COSTS_N_INSNS (23);
2428 return true;
2429 }
2430
2431 if (mode == DFmode)
2432 {
2433 if (TUNE_MIPS3000
2434 || TUNE_MIPS3900)
2435 *total = COSTS_N_INSNS (19);
2436 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2437 *total = COSTS_N_INSNS (59);
2438 else if (TUNE_MIPS6000)
2439 *total = COSTS_N_INSNS (16);
2440 else
2441 *total = COSTS_N_INSNS (36);
2442 return true;
2443 }
2444 /* Fall through. */
2445
2446 case UDIV:
2447 case UMOD:
2448 if (TUNE_MIPS3000
2449 || TUNE_MIPS3900)
2450 *total = COSTS_N_INSNS (35);
2451 else if (TUNE_MIPS6000)
2452 *total = COSTS_N_INSNS (38);
2453 else if (TUNE_MIPS5000)
2454 *total = COSTS_N_INSNS (36);
2455 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2456 *total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
2457 else
2458 *total = COSTS_N_INSNS (69);
2459 return true;
2460
2461 case SIGN_EXTEND:
2462 /* A sign extend from SImode to DImode in 64 bit mode is often
2463 zero instructions, because the result can often be used
2464 directly by another instruction; we'll call it one. */
2465 if (TARGET_64BIT && mode == DImode
2466 && GET_MODE (XEXP (x, 0)) == SImode)
2467 *total = COSTS_N_INSNS (1);
2468 else
2469 *total = COSTS_N_INSNS (2);
2470 return true;
2471
2472 case ZERO_EXTEND:
2473 if (TARGET_64BIT && mode == DImode
2474 && GET_MODE (XEXP (x, 0)) == SImode)
2475 *total = COSTS_N_INSNS (2);
2476 else
2477 *total = COSTS_N_INSNS (1);
2478 return true;
2479
2480 default:
2481 return false;
2482 }
2483 }
2484
2485 /* Provide the costs of an addressing mode that contains ADDR.
2486 If ADDR is not a valid address, its cost is irrelevant. */
2487
2488 static int
mips_address_cost(rtx addr)2489 mips_address_cost (rtx addr)
2490 {
2491 return mips_address_insns (addr, SImode);
2492 }
2493
2494 /* Return a pseudo that points to the address of the current function.
2495 The first time it is called for a function, an initializer for the
2496 pseudo is emitted in the beginning of the function. */
2497
2498 rtx
embedded_pic_fnaddr_reg(void)2499 embedded_pic_fnaddr_reg (void)
2500 {
2501 if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
2502 {
2503 rtx seq;
2504
2505 cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
2506
2507 /* Output code at function start to initialize the pseudo-reg. */
2508 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
2509 inline functions, because it is called after RTL for the function
2510 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
2511 does not get copied, and ends up not matching the rest of the RTL.
2512 This solution works, but means that we get unnecessary code to
2513 initialize this value every time a function is inlined into another
2514 function. */
2515 start_sequence ();
2516 emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
2517 XEXP (DECL_RTL (current_function_decl), 0)));
2518 seq = get_insns ();
2519 end_sequence ();
2520 push_topmost_sequence ();
2521 emit_insn_after (seq, get_insns ());
2522 pop_topmost_sequence ();
2523 }
2524
2525 return cfun->machine->embedded_pic_fnaddr_rtx;
2526 }
2527
2528 /* Return RTL for the offset from the current function to the argument.
2529 X is the symbol whose offset from the current function we want. */
2530
2531 rtx
embedded_pic_offset(rtx x)2532 embedded_pic_offset (rtx x)
2533 {
2534 /* Make sure it is emitted. */
2535 embedded_pic_fnaddr_reg ();
2536
2537 return
2538 gen_rtx_CONST (Pmode,
2539 gen_rtx_MINUS (Pmode, x,
2540 XEXP (DECL_RTL (current_function_decl), 0)));
2541 }
2542
2543 /* Return one word of double-word value OP, taking into account the fixed
2544 endianness of certain registers. HIGH_P is true to select the high part,
2545 false to select the low part. */
2546
2547 rtx
mips_subword(rtx op,int high_p)2548 mips_subword (rtx op, int high_p)
2549 {
2550 unsigned int byte;
2551 enum machine_mode mode;
2552
2553 mode = GET_MODE (op);
2554 if (mode == VOIDmode)
2555 mode = DImode;
2556
2557 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2558 byte = UNITS_PER_WORD;
2559 else
2560 byte = 0;
2561
2562 if (GET_CODE (op) == REG)
2563 {
2564 if (FP_REG_P (REGNO (op)))
2565 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2566 if (REGNO (op) == HI_REGNUM)
2567 return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
2568 }
2569
2570 if (GET_CODE (op) == MEM)
2571 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2572
2573 return simplify_gen_subreg (word_mode, op, mode, byte);
2574 }
2575
2576
2577 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2578
2579 bool
mips_split_64bit_move_p(rtx dest,rtx src)2580 mips_split_64bit_move_p (rtx dest, rtx src)
2581 {
2582 if (TARGET_64BIT)
2583 return false;
2584
2585 /* FP->FP moves can be done in a single instruction. */
2586 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2587 return false;
2588
2589 /* Check for floating-point loads and stores. They can be done using
2590 ldc1 and sdc1 on MIPS II and above. */
2591 if (mips_isa > 1)
2592 {
2593 if (FP_REG_RTX_P (dest) && GET_CODE (src) == MEM)
2594 return false;
2595 if (FP_REG_RTX_P (src) && GET_CODE (dest) == MEM)
2596 return false;
2597 }
2598 return true;
2599 }
2600
2601
2602 /* Split a 64-bit move from SRC to DEST assuming that
2603 mips_split_64bit_move_p holds.
2604
2605 Moves into and out of FPRs cause some difficulty here. Such moves
2606 will always be DFmode, since paired FPRs are not allowed to store
2607 DImode values. The most natural representation would be two separate
2608 32-bit moves, such as:
2609
2610 (set (reg:SI $f0) (mem:SI ...))
2611 (set (reg:SI $f1) (mem:SI ...))
2612
2613 However, the second insn is invalid because odd-numbered FPRs are
2614 not allowed to store independent values. Use the patterns load_df_low,
2615 load_df_high and store_df_high instead. */
2616
2617 void
mips_split_64bit_move(rtx dest,rtx src)2618 mips_split_64bit_move (rtx dest, rtx src)
2619 {
2620 if (FP_REG_RTX_P (dest))
2621 {
2622 /* Loading an FPR from memory or from GPRs. */
2623 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2624 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2625 copy_rtx (dest)));
2626 }
2627 else if (FP_REG_RTX_P (src))
2628 {
2629 /* Storing an FPR into memory or GPRs. */
2630 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2631 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2632 }
2633 else
2634 {
2635 /* The operation can be split into two normal moves. Decide in
2636 which order to do them. */
2637 rtx low_dest;
2638
2639 low_dest = mips_subword (dest, 0);
2640 if (GET_CODE (low_dest) == REG
2641 && reg_overlap_mentioned_p (low_dest, src))
2642 {
2643 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2644 emit_move_insn (low_dest, mips_subword (src, 0));
2645 }
2646 else
2647 {
2648 emit_move_insn (low_dest, mips_subword (src, 0));
2649 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2650 }
2651 }
2652 }
2653
2654 /* Return the appropriate instructions to move SRC into DEST. Assume
2655 that SRC is operand 1 and DEST is operand 0. */
2656
2657 const char *
mips_output_move(rtx dest,rtx src)2658 mips_output_move (rtx dest, rtx src)
2659 {
2660 enum rtx_code dest_code, src_code;
2661 bool dbl_p;
2662
2663 dest_code = GET_CODE (dest);
2664 src_code = GET_CODE (src);
2665 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2666
2667 if (dbl_p && mips_split_64bit_move_p (dest, src))
2668 return "#";
2669
2670 if ((src_code == REG && GP_REG_P (REGNO (src)))
2671 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2672 {
2673 if (dest_code == REG)
2674 {
2675 if (GP_REG_P (REGNO (dest)))
2676 return "move\t%0,%z1";
2677
2678 if (MD_REG_P (REGNO (dest)))
2679 return "mt%0\t%z1";
2680
2681 if (FP_REG_P (REGNO (dest)))
2682 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2683
2684 if (ALL_COP_REG_P (REGNO (dest)))
2685 {
2686 static char retval[] = "dmtc_\t%z1,%0";
2687
2688 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2689 return (dbl_p ? retval : retval + 1);
2690 }
2691 }
2692 if (dest_code == MEM)
2693 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2694 }
2695 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2696 {
2697 if (src_code == REG)
2698 {
2699 if (MD_REG_P (REGNO (src)))
2700 return "mf%1\t%0";
2701
2702 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2703 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2704
2705 if (FP_REG_P (REGNO (src)))
2706 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2707
2708 if (ALL_COP_REG_P (REGNO (src)))
2709 {
2710 static char retval[] = "dmfc_\t%0,%1";
2711
2712 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2713 return (dbl_p ? retval : retval + 1);
2714 }
2715 }
2716
2717 if (src_code == MEM)
2718 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2719
2720 if (src_code == CONST_INT)
2721 {
2722 /* Don't use the X format, because that will give out of
2723 range numbers for 64 bit hosts and 32 bit targets. */
2724 if (!TARGET_MIPS16)
2725 return "li\t%0,%1\t\t\t# %X1";
2726
2727 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2728 return "li\t%0,%1";
2729
2730 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2731 return "li\t%0,%n1\n\tneg\t%0";
2732 }
2733
2734 if (src_code == HIGH)
2735 return "lui\t%0,%h1";
2736
2737 if (CONST_GP_P (src))
2738 return "move\t%0,%1";
2739
2740 if (symbolic_operand (src, VOIDmode))
2741 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2742 }
2743 if (src_code == REG && FP_REG_P (REGNO (src)))
2744 {
2745 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2746 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2747
2748 if (dest_code == MEM)
2749 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2750 }
2751 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2752 {
2753 if (src_code == MEM)
2754 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2755 }
2756 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2757 {
2758 static char retval[] = "l_c_\t%0,%1";
2759
2760 retval[1] = (dbl_p ? 'd' : 'w');
2761 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2762 return retval;
2763 }
2764 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2765 {
2766 static char retval[] = "s_c_\t%1,%0";
2767
2768 retval[1] = (dbl_p ? 'd' : 'w');
2769 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2770 return retval;
2771 }
2772 abort ();
2773 }
2774
2775 /* Return an rtx for the gp save slot. Valid only when using o32 or
2776 o64 abicalls. */
2777
2778 rtx
mips_gp_save_slot(void)2779 mips_gp_save_slot (void)
2780 {
2781 rtx loc;
2782
2783 if (!TARGET_ABICALLS || TARGET_NEWABI)
2784 abort ();
2785
2786 if (frame_pointer_needed)
2787 loc = hard_frame_pointer_rtx;
2788 else
2789 loc = stack_pointer_rtx;
2790 loc = plus_constant (loc, current_function_outgoing_args_size);
2791 loc = gen_rtx_MEM (Pmode, loc);
2792 RTX_UNCHANGING_P (loc) = 1;
2793 return loc;
2794 }
2795
2796 /* Make normal rtx_code into something we can index from an array */
2797
2798 static enum internal_test
map_test_to_internal_test(enum rtx_code test_code)2799 map_test_to_internal_test (enum rtx_code test_code)
2800 {
2801 enum internal_test test = ITEST_MAX;
2802
2803 switch (test_code)
2804 {
2805 case EQ: test = ITEST_EQ; break;
2806 case NE: test = ITEST_NE; break;
2807 case GT: test = ITEST_GT; break;
2808 case GE: test = ITEST_GE; break;
2809 case LT: test = ITEST_LT; break;
2810 case LE: test = ITEST_LE; break;
2811 case GTU: test = ITEST_GTU; break;
2812 case GEU: test = ITEST_GEU; break;
2813 case LTU: test = ITEST_LTU; break;
2814 case LEU: test = ITEST_LEU; break;
2815 default: break;
2816 }
2817
2818 return test;
2819 }
2820
2821
2822 /* Generate the code to compare two integer values. The return value is:
2823 (reg:SI xx) The pseudo register the comparison is in
2824 0 No register, generate a simple branch.
2825
2826 ??? This is called with result nonzero by the Scond patterns in
2827 mips.md. These patterns are called with a target in the mode of
2828 the Scond instruction pattern. Since this must be a constant, we
2829 must use SImode. This means that if RESULT is nonzero, it will
2830 always be an SImode register, even if TARGET_64BIT is true. We
2831 cope with this by calling convert_move rather than emit_move_insn.
2832 This will sometimes lead to an unnecessary extension of the result;
2833 for example:
2834
2835 long long
2836 foo (long long i)
2837 {
2838 return i < 5;
2839 }
2840
2841 TEST_CODE is the rtx code for the comparison.
2842 CMP0 and CMP1 are the two operands to compare.
2843 RESULT is the register in which the result should be stored (null for
2844 branches).
2845 For branches, P_INVERT points to an integer that is nonzero on return
2846 if the branch should be inverted. */
2847
2848 rtx
gen_int_relational(enum rtx_code test_code,rtx result,rtx cmp0,rtx cmp1,int * p_invert)2849 gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0,
2850 rtx cmp1, int *p_invert)
2851 {
2852 struct cmp_info
2853 {
2854 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2855 int const_low; /* low bound of constant we can accept */
2856 int const_high; /* high bound of constant we can accept */
2857 int const_add; /* constant to add (convert LE -> LT) */
2858 int reverse_regs; /* reverse registers in test */
2859 int invert_const; /* != 0 if invert value if cmp1 is constant */
2860 int invert_reg; /* != 0 if invert value if cmp1 is register */
2861 int unsignedp; /* != 0 for unsigned comparisons. */
2862 };
2863
2864 static const struct cmp_info info[ (int)ITEST_MAX ] = {
2865
2866 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2867 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2868 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2869 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2870 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2871 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2872 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2873 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2874 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2875 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2876 };
2877
2878 enum internal_test test;
2879 enum machine_mode mode;
2880 const struct cmp_info *p_info;
2881 int branch_p;
2882 int eqne_p;
2883 int invert;
2884 rtx reg;
2885 rtx reg2;
2886
2887 test = map_test_to_internal_test (test_code);
2888 if (test == ITEST_MAX)
2889 abort ();
2890
2891 p_info = &info[(int) test];
2892 eqne_p = (p_info->test_code == XOR);
2893
2894 mode = GET_MODE (cmp0);
2895 if (mode == VOIDmode)
2896 mode = GET_MODE (cmp1);
2897
2898 /* Eliminate simple branches */
2899 branch_p = (result == 0);
2900 if (branch_p)
2901 {
2902 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2903 {
2904 /* Comparisons against zero are simple branches */
2905 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2906 && (! TARGET_MIPS16 || eqne_p))
2907 return 0;
2908
2909 /* Test for beq/bne. */
2910 if (eqne_p && ! TARGET_MIPS16)
2911 return 0;
2912 }
2913
2914 /* Allocate a pseudo to calculate the value in. */
2915 result = gen_reg_rtx (mode);
2916 }
2917
2918 /* Make sure we can handle any constants given to us. */
2919 if (GET_CODE (cmp0) == CONST_INT)
2920 cmp0 = force_reg (mode, cmp0);
2921
2922 if (GET_CODE (cmp1) == CONST_INT)
2923 {
2924 HOST_WIDE_INT value = INTVAL (cmp1);
2925
2926 if (value < p_info->const_low
2927 || value > p_info->const_high
2928 /* ??? Why? And why wasn't the similar code below modified too? */
2929 || (TARGET_64BIT
2930 && HOST_BITS_PER_WIDE_INT < 64
2931 && p_info->const_add != 0
2932 && ((p_info->unsignedp
2933 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2934 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2935 : (value + p_info->const_add) > INTVAL (cmp1))
2936 != (p_info->const_add > 0))))
2937 cmp1 = force_reg (mode, cmp1);
2938 }
2939
2940 /* See if we need to invert the result. */
2941 invert = (GET_CODE (cmp1) == CONST_INT
2942 ? p_info->invert_const : p_info->invert_reg);
2943
2944 if (p_invert != (int *)0)
2945 {
2946 *p_invert = invert;
2947 invert = 0;
2948 }
2949
2950 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2951 Comparison between two registers, may involve switching operands. */
2952 if (GET_CODE (cmp1) == CONST_INT)
2953 {
2954 if (p_info->const_add != 0)
2955 {
2956 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2957
2958 /* If modification of cmp1 caused overflow,
2959 we would get the wrong answer if we follow the usual path;
2960 thus, x > 0xffffffffU would turn into x > 0U. */
2961 if ((p_info->unsignedp
2962 ? (unsigned HOST_WIDE_INT) new >
2963 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2964 : new > INTVAL (cmp1))
2965 != (p_info->const_add > 0))
2966 {
2967 /* This test is always true, but if INVERT is true then
2968 the result of the test needs to be inverted so 0 should
2969 be returned instead. */
2970 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2971 return result;
2972 }
2973 else
2974 cmp1 = GEN_INT (new);
2975 }
2976 }
2977
2978 else if (p_info->reverse_regs)
2979 {
2980 rtx temp = cmp0;
2981 cmp0 = cmp1;
2982 cmp1 = temp;
2983 }
2984
2985 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2986 reg = cmp0;
2987 else
2988 {
2989 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2990 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2991 }
2992
2993 if (test == ITEST_NE)
2994 {
2995 if (! TARGET_MIPS16)
2996 {
2997 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2998 if (p_invert != NULL)
2999 *p_invert = 0;
3000 invert = 0;
3001 }
3002 else
3003 {
3004 reg2 = invert ? gen_reg_rtx (mode) : result;
3005 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
3006 reg = reg2;
3007 }
3008 }
3009
3010 else if (test == ITEST_EQ)
3011 {
3012 reg2 = invert ? gen_reg_rtx (mode) : result;
3013 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
3014 reg = reg2;
3015 }
3016
3017 if (invert)
3018 {
3019 rtx one;
3020
3021 if (! TARGET_MIPS16)
3022 one = const1_rtx;
3023 else
3024 {
3025 /* The value is in $24. Copy it to another register, so
3026 that reload doesn't think it needs to store the $24 and
3027 the input to the XOR in the same location. */
3028 reg2 = gen_reg_rtx (mode);
3029 emit_move_insn (reg2, reg);
3030 reg = reg2;
3031 one = force_reg (mode, const1_rtx);
3032 }
3033 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3034 }
3035
3036 return result;
3037 }
3038
3039 /* Work out how to check a floating-point condition. We need a
3040 separate comparison instruction (C.cond.fmt), followed by a
3041 branch or conditional move. Given that IN_CODE is the
3042 required condition, set *CMP_CODE to the C.cond.fmt code
3043 and *action_code to the branch or move code. */
3044
3045 static void
get_float_compare_codes(enum rtx_code in_code,enum rtx_code * cmp_code,enum rtx_code * action_code)3046 get_float_compare_codes (enum rtx_code in_code, enum rtx_code *cmp_code,
3047 enum rtx_code *action_code)
3048 {
3049 switch (in_code)
3050 {
3051 case NE:
3052 case UNGE:
3053 case UNGT:
3054 case LTGT:
3055 case ORDERED:
3056 *cmp_code = reverse_condition_maybe_unordered (in_code);
3057 *action_code = EQ;
3058 break;
3059
3060 default:
3061 *cmp_code = in_code;
3062 *action_code = NE;
3063 break;
3064 }
3065 }
3066
3067 /* Emit the common code for doing conditional branches.
3068 operand[0] is the label to jump to.
3069 The comparison operands are saved away by cmp{si,di,sf,df}. */
3070
3071 void
gen_conditional_branch(rtx * operands,enum rtx_code test_code)3072 gen_conditional_branch (rtx *operands, enum rtx_code test_code)
3073 {
3074 enum cmp_type type = branch_type;
3075 rtx cmp0 = branch_cmp[0];
3076 rtx cmp1 = branch_cmp[1];
3077 enum machine_mode mode;
3078 enum rtx_code cmp_code;
3079 rtx reg;
3080 int invert;
3081 rtx label1, label2;
3082
3083 switch (type)
3084 {
3085 case CMP_SI:
3086 case CMP_DI:
3087 mode = type == CMP_SI ? SImode : DImode;
3088 invert = 0;
3089 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3090
3091 if (reg)
3092 {
3093 cmp0 = reg;
3094 cmp1 = const0_rtx;
3095 test_code = NE;
3096 }
3097 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3098 /* We don't want to build a comparison against a nonzero
3099 constant. */
3100 cmp1 = force_reg (mode, cmp1);
3101
3102 break;
3103
3104 case CMP_SF:
3105 case CMP_DF:
3106 if (! ISA_HAS_8CC)
3107 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3108 else
3109 reg = gen_reg_rtx (CCmode);
3110
3111 get_float_compare_codes (test_code, &cmp_code, &test_code);
3112 emit_insn (gen_rtx_SET (VOIDmode, reg,
3113 gen_rtx (cmp_code, CCmode, cmp0, cmp1)));
3114
3115 mode = CCmode;
3116 cmp0 = reg;
3117 cmp1 = const0_rtx;
3118 invert = 0;
3119 break;
3120
3121 default:
3122 fatal_insn ("bad test", gen_rtx (test_code, VOIDmode, cmp0, cmp1));
3123 }
3124
3125 /* Generate the branch. */
3126
3127 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3128 label2 = pc_rtx;
3129
3130 if (invert)
3131 {
3132 label2 = label1;
3133 label1 = pc_rtx;
3134 }
3135
3136 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3137 gen_rtx_IF_THEN_ELSE (VOIDmode,
3138 gen_rtx (test_code, mode,
3139 cmp0, cmp1),
3140 label1, label2)));
3141 }
3142
3143 /* Emit the common code for conditional moves. OPERANDS is the array
3144 of operands passed to the conditional move define_expand. */
3145
3146 void
gen_conditional_move(rtx * operands)3147 gen_conditional_move (rtx *operands)
3148 {
3149 rtx op0 = branch_cmp[0];
3150 rtx op1 = branch_cmp[1];
3151 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3152 enum rtx_code cmp_code = GET_CODE (operands[1]);
3153 enum rtx_code move_code = NE;
3154 enum machine_mode op_mode = GET_MODE (operands[0]);
3155 enum machine_mode cmp_mode;
3156 rtx cmp_reg;
3157
3158 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3159 {
3160 switch (cmp_code)
3161 {
3162 case EQ:
3163 cmp_code = XOR;
3164 move_code = EQ;
3165 break;
3166 case NE:
3167 cmp_code = XOR;
3168 break;
3169 case LT:
3170 break;
3171 case GE:
3172 cmp_code = LT;
3173 move_code = EQ;
3174 break;
3175 case GT:
3176 cmp_code = LT;
3177 op0 = force_reg (mode, branch_cmp[1]);
3178 op1 = branch_cmp[0];
3179 break;
3180 case LE:
3181 cmp_code = LT;
3182 op0 = force_reg (mode, branch_cmp[1]);
3183 op1 = branch_cmp[0];
3184 move_code = EQ;
3185 break;
3186 case LTU:
3187 break;
3188 case GEU:
3189 cmp_code = LTU;
3190 move_code = EQ;
3191 break;
3192 case GTU:
3193 cmp_code = LTU;
3194 op0 = force_reg (mode, branch_cmp[1]);
3195 op1 = branch_cmp[0];
3196 break;
3197 case LEU:
3198 cmp_code = LTU;
3199 op0 = force_reg (mode, branch_cmp[1]);
3200 op1 = branch_cmp[0];
3201 move_code = EQ;
3202 break;
3203 default:
3204 abort ();
3205 }
3206 }
3207 else
3208 get_float_compare_codes (cmp_code, &cmp_code, &move_code);
3209
3210 if (mode == SImode || mode == DImode)
3211 cmp_mode = mode;
3212 else if (mode == SFmode || mode == DFmode)
3213 cmp_mode = CCmode;
3214 else
3215 abort ();
3216
3217 cmp_reg = gen_reg_rtx (cmp_mode);
3218 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3219 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3220
3221 emit_insn (gen_rtx_SET (op_mode, operands[0],
3222 gen_rtx_IF_THEN_ELSE (op_mode,
3223 gen_rtx (move_code, VOIDmode,
3224 cmp_reg,
3225 CONST0_RTX (SImode)),
3226 operands[2], operands[3])));
3227 }
3228
3229 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3230 the conditional_trap expander. */
3231
3232 void
mips_gen_conditional_trap(rtx * operands)3233 mips_gen_conditional_trap (rtx *operands)
3234 {
3235 rtx op0, op1;
3236 enum rtx_code cmp_code = GET_CODE (operands[0]);
3237 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3238
3239 /* MIPS conditional trap machine instructions don't have GT or LE
3240 flavors, so we must invert the comparison and convert to LT and
3241 GE, respectively. */
3242 switch (cmp_code)
3243 {
3244 case GT: cmp_code = LT; break;
3245 case LE: cmp_code = GE; break;
3246 case GTU: cmp_code = LTU; break;
3247 case LEU: cmp_code = GEU; break;
3248 default: break;
3249 }
3250 if (cmp_code == GET_CODE (operands[0]))
3251 {
3252 op0 = force_reg (mode, branch_cmp[0]);
3253 op1 = branch_cmp[1];
3254 }
3255 else
3256 {
3257 op0 = force_reg (mode, branch_cmp[1]);
3258 op1 = branch_cmp[0];
3259 }
3260 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3261 op1 = force_reg (mode, op1);
3262
3263 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3264 gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3265 operands[1]));
3266 }
3267
3268 /* Load function address ADDR into register DEST. SIBCALL_P is true
3269 if the address is needed for a sibling call. */
3270
3271 static void
mips_load_call_address(rtx dest,rtx addr,int sibcall_p)3272 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3273 {
3274 /* If we're generating PIC, and this call is to a global function,
3275 try to allow its address to be resolved lazily. This isn't
3276 possible for NewABI sibcalls since the value of $gp on entry
3277 to the stub would be our caller's gp, not ours. */
3278 if (TARGET_EXPLICIT_RELOCS
3279 && !(sibcall_p && TARGET_NEWABI)
3280 && global_got_operand (addr, VOIDmode))
3281 {
3282 rtx high, lo_sum_symbol;
3283
3284 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3285 addr, SYMBOL_GOTOFF_CALL);
3286 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3287 if (Pmode == SImode)
3288 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3289 else
3290 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3291 }
3292 else
3293 emit_move_insn (dest, addr);
3294 }
3295
3296
3297 /* Expand a call or call_value instruction. RESULT is where the
3298 result will go (null for calls), ADDR is the address of the
3299 function, ARGS_SIZE is the size of the arguments and AUX is
3300 the value passed to us by mips_function_arg. SIBCALL_P is true
3301 if we are expanding a sibling call, false if we're expanding
3302 a normal call. */
3303
3304 void
mips_expand_call(rtx result,rtx addr,rtx args_size,rtx aux,int sibcall_p)3305 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3306 {
3307 rtx orig_addr, pattern, insn;
3308
3309 orig_addr = addr;
3310 if (!call_insn_operand (addr, VOIDmode))
3311 {
3312 addr = gen_reg_rtx (Pmode);
3313 mips_load_call_address (addr, orig_addr, sibcall_p);
3314 }
3315
3316 if (TARGET_MIPS16
3317 && mips16_hard_float
3318 && build_mips16_call_stub (result, addr, args_size,
3319 aux == 0 ? 0 : (int) GET_MODE (aux)))
3320 return;
3321
3322 if (result == 0)
3323 pattern = (sibcall_p
3324 ? gen_sibcall_internal (addr, args_size)
3325 : gen_call_internal (addr, args_size));
3326 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3327 {
3328 rtx reg1, reg2;
3329
3330 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3331 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3332 pattern =
3333 (sibcall_p
3334 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3335 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3336 }
3337 else
3338 pattern = (sibcall_p
3339 ? gen_sibcall_value_internal (result, addr, args_size)
3340 : gen_call_value_internal (result, addr, args_size));
3341
3342 insn = emit_call_insn (pattern);
3343
3344 /* Lazy-binding stubs require $gp to be valid on entry. */
3345 if (global_got_operand (orig_addr, VOIDmode))
3346 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3347 }
3348
3349
3350 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3351
3352 static bool
mips_function_ok_for_sibcall(tree decl ATTRIBUTE_UNUSED,tree exp ATTRIBUTE_UNUSED)3353 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3354 tree exp ATTRIBUTE_UNUSED)
3355 {
3356 return TARGET_SIBCALLS;
3357 }
3358
3359 /* Return true if operand OP is a condition code register.
3360 Only for use during or after reload. */
3361
3362 int
fcc_register_operand(rtx op,enum machine_mode mode)3363 fcc_register_operand (rtx op, enum machine_mode mode)
3364 {
3365 return ((mode == VOIDmode || mode == GET_MODE (op))
3366 && (reload_in_progress || reload_completed)
3367 && (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
3368 && ST_REG_P (true_regnum (op)));
3369 }
3370
3371 /* Emit code to move general operand SRC into condition-code
3372 register DEST. SCRATCH is a scratch TFmode float register.
3373 The sequence is:
3374
3375 FP1 = SRC
3376 FP2 = 0.0f
3377 DEST = FP2 < FP1
3378
3379 where FP1 and FP2 are single-precision float registers
3380 taken from SCRATCH. */
3381
3382 void
mips_emit_fcc_reload(rtx dest,rtx src,rtx scratch)3383 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3384 {
3385 rtx fp1, fp2;
3386
3387 /* Change the source to SFmode. */
3388 if (GET_CODE (src) == MEM)
3389 src = adjust_address (src, SFmode, 0);
3390 else if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)
3391 src = gen_rtx_REG (SFmode, true_regnum (src));
3392
3393 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3394 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3395
3396 emit_move_insn (copy_rtx (fp1), src);
3397 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3398 emit_insn (gen_slt_sf (dest, fp2, fp1));
3399 }
3400
3401 /* Emit code to change the current function's return address to
3402 ADDRESS. SCRATCH is available as a scratch register, if needed.
3403 ADDRESS and SCRATCH are both word-mode GPRs. */
3404
3405 void
mips_set_return_address(rtx address,rtx scratch)3406 mips_set_return_address (rtx address, rtx scratch)
3407 {
3408 HOST_WIDE_INT gp_offset;
3409
3410 compute_frame_size (get_frame_size ());
3411 if (((cfun->machine->frame.mask >> 31) & 1) == 0)
3412 abort ();
3413 gp_offset = cfun->machine->frame.gp_sp_offset;
3414
3415 /* Reduce SP + GP_OFSET to a legitimate address and put it in SCRATCH. */
3416 if (gp_offset < 32768)
3417 scratch = plus_constant (stack_pointer_rtx, gp_offset);
3418 else
3419 {
3420 emit_move_insn (scratch, GEN_INT (gp_offset));
3421 if (Pmode == DImode)
3422 emit_insn (gen_adddi3 (scratch, scratch, stack_pointer_rtx));
3423 else
3424 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
3425 }
3426
3427 emit_move_insn (gen_rtx_MEM (GET_MODE (address), scratch), address);
3428 }
3429
3430 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3431 Assume that the areas do not overlap. */
3432
3433 static void
mips_block_move_straight(rtx dest,rtx src,HOST_WIDE_INT length)3434 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3435 {
3436 HOST_WIDE_INT offset, delta;
3437 unsigned HOST_WIDE_INT bits;
3438 int i;
3439 enum machine_mode mode;
3440 rtx *regs;
3441
3442 /* Work out how many bits to move at a time. If both operands have
3443 half-word alignment, it is usually better to move in half words.
3444 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3445 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3446 Otherwise move word-sized chunks. */
3447 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3448 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3449 bits = BITS_PER_WORD / 2;
3450 else
3451 bits = BITS_PER_WORD;
3452
3453 mode = mode_for_size (bits, MODE_INT, 0);
3454 delta = bits / BITS_PER_UNIT;
3455
3456 /* Allocate a buffer for the temporary registers. */
3457 regs = alloca (sizeof (rtx) * length / delta);
3458
3459 /* Load as many BITS-sized chunks as possible. Use a normal load if
3460 the source has enough alignment, otherwise use left/right pairs. */
3461 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3462 {
3463 regs[i] = gen_reg_rtx (mode);
3464 if (MEM_ALIGN (src) >= bits)
3465 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3466 else
3467 {
3468 rtx part = adjust_address (src, BLKmode, offset);
3469 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3470 abort ();
3471 }
3472 }
3473
3474 /* Copy the chunks to the destination. */
3475 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3476 if (MEM_ALIGN (dest) >= bits)
3477 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3478 else
3479 {
3480 rtx part = adjust_address (dest, BLKmode, offset);
3481 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3482 abort ();
3483 }
3484
3485 /* Mop up any left-over bytes. */
3486 if (offset < length)
3487 {
3488 src = adjust_address (src, BLKmode, offset);
3489 dest = adjust_address (dest, BLKmode, offset);
3490 move_by_pieces (dest, src, length - offset,
3491 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3492 }
3493 }
3494
3495 #define MAX_MOVE_REGS 4
3496 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3497
3498
3499 /* Helper function for doing a loop-based block operation on memory
3500 reference MEM. Each iteration of the loop will operate on LENGTH
3501 bytes of MEM.
3502
3503 Create a new base register for use within the loop and point it to
3504 the start of MEM. Create a new memory reference that uses this
3505 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3506
3507 static void
mips_adjust_block_mem(rtx mem,HOST_WIDE_INT length,rtx * loop_reg,rtx * loop_mem)3508 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3509 rtx *loop_reg, rtx *loop_mem)
3510 {
3511 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3512
3513 /* Although the new mem does not refer to a known location,
3514 it does keep up to LENGTH bytes of alignment. */
3515 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3516 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3517 }
3518
3519
3520 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3521 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3522 memory regions do not overlap. */
3523
3524 static void
mips_block_move_loop(rtx dest,rtx src,HOST_WIDE_INT length)3525 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3526 {
3527 rtx label, src_reg, dest_reg, final_src;
3528 HOST_WIDE_INT leftover;
3529
3530 leftover = length % MAX_MOVE_BYTES;
3531 length -= leftover;
3532
3533 /* Create registers and memory references for use within the loop. */
3534 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3535 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3536
3537 /* Calculate the value that SRC_REG should have after the last iteration
3538 of the loop. */
3539 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3540 0, 0, OPTAB_WIDEN);
3541
3542 /* Emit the start of the loop. */
3543 label = gen_label_rtx ();
3544 emit_label (label);
3545
3546 /* Emit the loop body. */
3547 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3548
3549 /* Move on to the next block. */
3550 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3551 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3552
3553 /* Emit the loop condition. */
3554 if (Pmode == DImode)
3555 emit_insn (gen_cmpdi (src_reg, final_src));
3556 else
3557 emit_insn (gen_cmpsi (src_reg, final_src));
3558 emit_jump_insn (gen_bne (label));
3559
3560 /* Mop up any left-over bytes. */
3561 if (leftover)
3562 mips_block_move_straight (dest, src, leftover);
3563 }
3564
3565 /* Expand a movstrsi instruction. */
3566
3567 bool
mips_expand_block_move(rtx dest,rtx src,rtx length)3568 mips_expand_block_move (rtx dest, rtx src, rtx length)
3569 {
3570 if (GET_CODE (length) == CONST_INT)
3571 {
3572 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3573 {
3574 mips_block_move_straight (dest, src, INTVAL (length));
3575 return true;
3576 }
3577 else if (optimize)
3578 {
3579 mips_block_move_loop (dest, src, INTVAL (length));
3580 return true;
3581 }
3582 }
3583 return false;
3584 }
3585
3586 /* Argument support functions. */
3587
3588 /* Initialize CUMULATIVE_ARGS for a function. */
3589
3590 void
init_cumulative_args(CUMULATIVE_ARGS * cum,tree fntype,rtx libname ATTRIBUTE_UNUSED)3591 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3592 rtx libname ATTRIBUTE_UNUSED)
3593 {
3594 static CUMULATIVE_ARGS zero_cum;
3595 tree param, next_param;
3596
3597 if (TARGET_DEBUG_E_MODE)
3598 {
3599 fprintf (stderr,
3600 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3601
3602 if (!fntype)
3603 fputc ('\n', stderr);
3604
3605 else
3606 {
3607 tree ret_type = TREE_TYPE (fntype);
3608 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3609 tree_code_name[(int)TREE_CODE (fntype)],
3610 tree_code_name[(int)TREE_CODE (ret_type)]);
3611 }
3612 }
3613
3614 *cum = zero_cum;
3615 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3616
3617 /* Determine if this function has variable arguments. This is
3618 indicated by the last argument being 'void_type_mode' if there
3619 are no variable arguments. The standard MIPS calling sequence
3620 passes all arguments in the general purpose registers in this case. */
3621
3622 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3623 param != 0; param = next_param)
3624 {
3625 next_param = TREE_CHAIN (param);
3626 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3627 cum->gp_reg_found = 1;
3628 }
3629 }
3630
3631
3632 /* Fill INFO with information about a single argument. CUM is the
3633 cumulative state for earlier arguments. MODE is the mode of this
3634 argument and TYPE is its type (if known). NAMED is true if this
3635 is a named (fixed) argument rather than a variable one. */
3636
3637 static void
mips_arg_info(const CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int named,struct mips_arg_info * info)3638 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3639 tree type, int named, struct mips_arg_info *info)
3640 {
3641 bool even_reg_p;
3642 unsigned int num_words, max_regs;
3643
3644 /* Decide whether this argument should go in a floating-point register,
3645 assuming one is free. Later code checks for availability. */
3646
3647 info->fpr_p = (GET_MODE_CLASS (mode) == MODE_FLOAT
3648 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3649
3650 if (info->fpr_p)
3651 switch (mips_abi)
3652 {
3653 case ABI_32:
3654 case ABI_O64:
3655 info->fpr_p = (!cum->gp_reg_found
3656 && cum->arg_number < 2
3657 && (type == 0 || FLOAT_TYPE_P (type)));
3658 break;
3659
3660 case ABI_N32:
3661 case ABI_64:
3662 info->fpr_p = (named && (type == 0 || FLOAT_TYPE_P (type)));
3663 break;
3664 }
3665
3666 /* Now decide whether the argument must go in an even-numbered register. */
3667
3668 even_reg_p = false;
3669 if (info->fpr_p)
3670 {
3671 /* Under the O64 ABI, the second float argument goes in $f13 if it
3672 is a double, but $f14 if it is a single. Otherwise, on a
3673 32-bit double-float machine, each FP argument must start in a
3674 new register pair. */
3675 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_HWFPVALUE
3676 || (mips_abi == ABI_O64 && mode == SFmode)
3677 || FP_INC > 1);
3678 }
3679 else if (!TARGET_64BIT || LONG_DOUBLE_TYPE_SIZE == 128)
3680 {
3681 if (GET_MODE_CLASS (mode) == MODE_INT
3682 || GET_MODE_CLASS (mode) == MODE_FLOAT)
3683 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);
3684
3685 else if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD)
3686 even_reg_p = true;
3687 }
3688
3689 if (mips_abi != ABI_EABI && MUST_PASS_IN_STACK (mode, type))
3690 /* This argument must be passed on the stack. Eat up all the
3691 remaining registers. */
3692 info->reg_offset = MAX_ARGS_IN_REGISTERS;
3693 else
3694 {
3695 /* Set REG_OFFSET to the register count we're interested in.
3696 The EABI allocates the floating-point registers separately,
3697 but the other ABIs allocate them like integer registers. */
3698 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3699 ? cum->num_fprs
3700 : cum->num_gprs);
3701
3702 if (even_reg_p)
3703 info->reg_offset += info->reg_offset & 1;
3704 }
3705
3706 /* The alignment applied to registers is also applied to stack arguments. */
3707 info->stack_offset = cum->stack_words;
3708 if (even_reg_p)
3709 info->stack_offset += info->stack_offset & 1;
3710
3711 if (mode == BLKmode)
3712 info->num_bytes = int_size_in_bytes (type);
3713 else
3714 info->num_bytes = GET_MODE_SIZE (mode);
3715
3716 num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3717 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3718
3719 /* Partition the argument between registers and stack. */
3720 info->reg_words = MIN (num_words, max_regs);
3721 info->stack_words = num_words - info->reg_words;
3722 }
3723
3724
3725 /* Implement FUNCTION_ARG_ADVANCE. */
3726
3727 void
function_arg_advance(CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int named)3728 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3729 tree type, int named)
3730 {
3731 struct mips_arg_info info;
3732
3733 mips_arg_info (cum, mode, type, named, &info);
3734
3735 if (!info.fpr_p)
3736 cum->gp_reg_found = true;
3737
3738 /* See the comment above the cumulative args structure in mips.h
3739 for an explanation of what this code does. It assumes the O32
3740 ABI, which passes at most 2 arguments in float registers. */
3741 if (cum->arg_number < 2 && info.fpr_p)
3742 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3743
3744 if (mips_abi != ABI_EABI || !info.fpr_p)
3745 cum->num_gprs = info.reg_offset + info.reg_words;
3746 else if (info.reg_words > 0)
3747 cum->num_fprs += FP_INC;
3748
3749 if (info.stack_words > 0)
3750 cum->stack_words = info.stack_offset + info.stack_words;
3751
3752 cum->arg_number++;
3753 }
3754
3755 /* Implement FUNCTION_ARG. */
3756
3757 struct rtx_def *
function_arg(const CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int named)3758 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3759 tree type, int named)
3760 {
3761 struct mips_arg_info info;
3762
3763 /* We will be called with a mode of VOIDmode after the last argument
3764 has been seen. Whatever we return will be passed to the call
3765 insn. If we need a mips16 fp_code, return a REG with the code
3766 stored as the mode. */
3767 if (mode == VOIDmode)
3768 {
3769 if (TARGET_MIPS16 && cum->fp_code != 0)
3770 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3771
3772 else
3773 return 0;
3774 }
3775
3776 mips_arg_info (cum, mode, type, named, &info);
3777
3778 /* Return straight away if the whole argument is passed on the stack. */
3779 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3780 return 0;
3781
3782 if (type != 0
3783 && TREE_CODE (type) == RECORD_TYPE
3784 && (mips_abi == ABI_N32 || mips_abi == ABI_64)
3785 && TYPE_SIZE_UNIT (type)
3786 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3787 && named)
3788 {
3789 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3790 structure contains a double in its entirety, then that 64 bit
3791 chunk is passed in a floating point register. */
3792 tree field;
3793
3794 /* First check to see if there is any such field. */
3795 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3796 if (TREE_CODE (field) == FIELD_DECL
3797 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3798 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3799 && host_integerp (bit_position (field), 0)
3800 && int_bit_position (field) % BITS_PER_WORD == 0)
3801 break;
3802
3803 if (field != 0)
3804 {
3805 /* Now handle the special case by returning a PARALLEL
3806 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3807 chunks are passed in registers. */
3808 unsigned int i;
3809 HOST_WIDE_INT bitpos;
3810 rtx ret;
3811
3812 /* assign_parms checks the mode of ENTRY_PARM, so we must
3813 use the actual mode here. */
3814 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3815
3816 bitpos = 0;
3817 field = TYPE_FIELDS (type);
3818 for (i = 0; i < info.reg_words; i++)
3819 {
3820 rtx reg;
3821
3822 for (; field; field = TREE_CHAIN (field))
3823 if (TREE_CODE (field) == FIELD_DECL
3824 && int_bit_position (field) >= bitpos)
3825 break;
3826
3827 if (field
3828 && int_bit_position (field) == bitpos
3829 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3830 && !TARGET_SOFT_FLOAT
3831 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3832 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3833 else
3834 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3835
3836 XVECEXP (ret, 0, i)
3837 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3838 GEN_INT (bitpos / BITS_PER_UNIT));
3839
3840 bitpos += BITS_PER_WORD;
3841 }
3842 return ret;
3843 }
3844 }
3845
3846 if (info.fpr_p)
3847 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3848 else
3849 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3850 }
3851
3852
3853 /* Implement FUNCTION_ARG_PARTIAL_NREGS. */
3854
3855 int
function_arg_partial_nregs(const CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int named)3856 function_arg_partial_nregs (const CUMULATIVE_ARGS *cum,
3857 enum machine_mode mode, tree type, int named)
3858 {
3859 struct mips_arg_info info;
3860
3861 mips_arg_info (cum, mode, type, named, &info);
3862 return info.stack_words > 0 ? info.reg_words : 0;
3863 }
3864
3865
3866 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3867 upward rather than downward. In other words, return true if the
3868 first byte of the stack slot has useful data, false if the last
3869 byte does. */
3870
3871 bool
mips_pad_arg_upward(enum machine_mode mode,tree type)3872 mips_pad_arg_upward (enum machine_mode mode, tree type)
3873 {
3874 /* On little-endian targets, the first byte of every stack argument
3875 is passed in the first byte of the stack slot. */
3876 if (!BYTES_BIG_ENDIAN)
3877 return true;
3878
3879 /* Otherwise, integral types are padded downward: the last byte of a
3880 stack argument is passed in the last byte of the stack slot. */
3881 if (type != 0
3882 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3883 : GET_MODE_CLASS (mode) == MODE_INT)
3884 return false;
3885
3886 /* Big-endian o64 pads floating-point arguments downward. */
3887 if (mips_abi == ABI_O64)
3888 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3889 return false;
3890
3891 /* Other types are padded upward for o32, o64, n32 and n64. */
3892 if (mips_abi != ABI_EABI)
3893 return true;
3894
3895 /* Arguments smaller than a stack slot are padded downward. */
3896 if (mode != BLKmode)
3897 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3898 else
3899 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3900 }
3901
3902
3903 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3904 if the least significant byte of the register has useful data. Return
3905 the opposite if the most significant byte does. */
3906
3907 bool
mips_pad_reg_upward(enum machine_mode mode,tree type)3908 mips_pad_reg_upward (enum machine_mode mode, tree type)
3909 {
3910 /* No shifting is required for floating-point arguments. */
3911 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3912 return !BYTES_BIG_ENDIAN;
3913
3914 /* Otherwise, apply the same padding to register arguments as we do
3915 to stack arguments. */
3916 return mips_pad_arg_upward (mode, type);
3917 }
3918
3919 int
mips_setup_incoming_varargs(const CUMULATIVE_ARGS * cum,enum machine_mode mode,tree type,int no_rtl)3920 mips_setup_incoming_varargs (const CUMULATIVE_ARGS *cum,
3921 enum machine_mode mode, tree type, int no_rtl)
3922 {
3923 CUMULATIVE_ARGS local_cum;
3924 int gp_saved, fp_saved;
3925
3926 /* The caller has advanced CUM up to, but not beyond, the last named
3927 argument. Advance a local copy of CUM past the last "real" named
3928 argument, to find out how many registers are left over. */
3929
3930 local_cum = *cum;
3931 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3932
3933 /* Found out how many registers we need to save. */
3934 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3935 fp_saved = (EABI_FLOAT_VARARGS_P
3936 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3937 : 0);
3938
3939 if (!no_rtl)
3940 {
3941 if (gp_saved > 0)
3942 {
3943 rtx ptr, mem;
3944
3945 ptr = virtual_incoming_args_rtx;
3946 switch (mips_abi)
3947 {
3948 case ABI_32:
3949 case ABI_O64:
3950 ptr = plus_constant (ptr, local_cum.num_gprs * UNITS_PER_WORD);
3951 break;
3952
3953 case ABI_EABI:
3954 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
3955 break;
3956 }
3957 mem = gen_rtx_MEM (BLKmode, ptr);
3958 set_mem_alias_set (mem, get_varargs_alias_set ());
3959
3960 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3961 mem, gp_saved);
3962 }
3963 if (fp_saved > 0)
3964 {
3965 /* We can't use move_block_from_reg, because it will use
3966 the wrong mode. */
3967 enum machine_mode mode;
3968 int off, i;
3969
3970 /* Set OFF to the offset from virtual_incoming_args_rtx of
3971 the first float register. The FP save area lies below
3972 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3973 off = -gp_saved * UNITS_PER_WORD;
3974 off &= ~(UNITS_PER_FPVALUE - 1);
3975 off -= fp_saved * UNITS_PER_FPREG;
3976
3977 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3978
3979 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3980 {
3981 rtx ptr, mem;
3982
3983 ptr = plus_constant (virtual_incoming_args_rtx, off);
3984 mem = gen_rtx_MEM (mode, ptr);
3985 set_mem_alias_set (mem, get_varargs_alias_set ());
3986 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3987 off += UNITS_PER_HWFPVALUE;
3988 }
3989 }
3990 }
3991 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3992 /* No need for pretend arguments: the register parameter area was
3993 allocated by the caller. */
3994 return 0;
3995 return (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
3996 }
3997
3998 /* Create the va_list data type.
3999 We keep 3 pointers, and two offsets.
4000 Two pointers are to the overflow area, which starts at the CFA.
4001 One of these is constant, for addressing into the GPR save area below it.
4002 The other is advanced up the stack through the overflow region.
4003 The third pointer is to the GPR save area. Since the FPR save area
4004 is just below it, we can address FPR slots off this pointer.
4005 We also keep two one-byte offsets, which are to be subtracted from the
4006 constant pointers to yield addresses in the GPR and FPR save areas.
4007 These are downcounted as float or non-float arguments are used,
4008 and when they get to zero, the argument must be obtained from the
4009 overflow region.
4010 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4011 pointer is enough. It's started at the GPR save area, and is
4012 advanced, period.
4013 Note that the GPR save area is not constant size, due to optimization
4014 in the prologue. Hence, we can't use a design with two pointers
4015 and two offsets, although we could have designed this with two pointers
4016 and three offsets. */
4017
4018 static tree
mips_build_builtin_va_list(void)4019 mips_build_builtin_va_list (void)
4020 {
4021 if (EABI_FLOAT_VARARGS_P)
4022 {
4023 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4024 tree array, index;
4025
4026 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4027
4028 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4029 ptr_type_node);
4030 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4031 ptr_type_node);
4032 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4033 ptr_type_node);
4034 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4035 unsigned_char_type_node);
4036 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4037 unsigned_char_type_node);
4038 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4039 warn on every user file. */
4040 index = build_int_2 (GET_MODE_SIZE (ptr_mode) - 2 - 1, 0);
4041 array = build_array_type (unsigned_char_type_node,
4042 build_index_type (index));
4043 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4044
4045 DECL_FIELD_CONTEXT (f_ovfl) = record;
4046 DECL_FIELD_CONTEXT (f_gtop) = record;
4047 DECL_FIELD_CONTEXT (f_ftop) = record;
4048 DECL_FIELD_CONTEXT (f_goff) = record;
4049 DECL_FIELD_CONTEXT (f_foff) = record;
4050 DECL_FIELD_CONTEXT (f_res) = record;
4051
4052 TYPE_FIELDS (record) = f_ovfl;
4053 TREE_CHAIN (f_ovfl) = f_gtop;
4054 TREE_CHAIN (f_gtop) = f_ftop;
4055 TREE_CHAIN (f_ftop) = f_goff;
4056 TREE_CHAIN (f_goff) = f_foff;
4057 TREE_CHAIN (f_foff) = f_res;
4058
4059 layout_type (record);
4060 return record;
4061 }
4062 else if (TARGET_IRIX && !TARGET_IRIX5)
4063 /* On IRIX 6, this type is 'char *'. */
4064 return build_pointer_type (char_type_node);
4065 else
4066 /* Otherwise, we use 'void *'. */
4067 return ptr_type_node;
4068 }
4069
4070 /* Implement va_start. */
4071
4072 void
mips_va_start(tree valist,rtx nextarg)4073 mips_va_start (tree valist, rtx nextarg)
4074 {
4075 const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
4076
4077 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
4078 since the stack is aligned for a pair of argument-passing slots,
4079 and the beginning of a variable argument list may be an odd slot,
4080 we have to decrease its alignment. */
4081 if (cfun && cfun->emit->regno_pointer_align)
4082 while (((current_function_pretend_args_size * BITS_PER_UNIT)
4083 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
4084 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
4085
4086 if (mips_abi == ABI_EABI)
4087 {
4088 int gpr_save_area_size;
4089
4090 gpr_save_area_size
4091 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4092
4093 if (EABI_FLOAT_VARARGS_P)
4094 {
4095 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4096 tree ovfl, gtop, ftop, goff, foff;
4097 tree t;
4098 int fpr_offset;
4099 int fpr_save_area_size;
4100
4101 f_ovfl = TYPE_FIELDS (va_list_type_node);
4102 f_gtop = TREE_CHAIN (f_ovfl);
4103 f_ftop = TREE_CHAIN (f_gtop);
4104 f_goff = TREE_CHAIN (f_ftop);
4105 f_foff = TREE_CHAIN (f_goff);
4106
4107 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4108 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4109 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4110 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4111 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4112
4113 /* Emit code to initialize OVFL, which points to the next varargs
4114 stack argument. CUM->STACK_WORDS gives the number of stack
4115 words used by named arguments. */
4116 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4117 if (cum->stack_words > 0)
4118 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4119 build_int_2 (cum->stack_words * UNITS_PER_WORD, 0));
4120 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4121 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4122
4123 /* Emit code to initialize GTOP, the top of the GPR save area. */
4124 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4125 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4126 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4127
4128 /* Emit code to initialize FTOP, the top of the FPR save area.
4129 This address is gpr_save_area_bytes below GTOP, rounded
4130 down to the next fp-aligned boundary. */
4131 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4132 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4133 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4134 if (fpr_offset)
4135 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4136 build_int_2 (-fpr_offset, -1));
4137 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4138 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4139
4140 /* Emit code to initialize GOFF, the offset from GTOP of the
4141 next GPR argument. */
4142 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4143 build_int_2 (gpr_save_area_size, 0));
4144 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4145
4146 /* Likewise emit code to initialize FOFF, the offset from FTOP
4147 of the next FPR argument. */
4148 fpr_save_area_size
4149 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4150 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4151 build_int_2 (fpr_save_area_size, 0));
4152 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4153 }
4154 else
4155 {
4156 /* Everything is in the GPR save area, or in the overflow
4157 area which is contiguous with it. */
4158 nextarg = plus_constant (nextarg, -gpr_save_area_size);
4159 std_expand_builtin_va_start (valist, nextarg);
4160 }
4161 }
4162 else
4163 std_expand_builtin_va_start (valist, nextarg);
4164 }
4165
4166 /* Implement va_arg. */
4167
4168 rtx
mips_va_arg(tree valist,tree type)4169 mips_va_arg (tree valist, tree type)
4170 {
4171 HOST_WIDE_INT size, rsize;
4172 rtx addr_rtx;
4173 tree t;
4174
4175 size = int_size_in_bytes (type);
4176 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4177
4178 if (mips_abi == ABI_EABI)
4179 {
4180 bool indirect;
4181 rtx r;
4182
4183 indirect
4184 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4185
4186 if (indirect)
4187 {
4188 size = POINTER_SIZE / BITS_PER_UNIT;
4189 rsize = UNITS_PER_WORD;
4190 }
4191
4192 addr_rtx = gen_reg_rtx (Pmode);
4193
4194 if (!EABI_FLOAT_VARARGS_P)
4195 {
4196 /* Case of all args in a merged stack. No need to check bounds,
4197 just advance valist along the stack. */
4198
4199 tree gpr = valist;
4200 if (!indirect
4201 && !TARGET_64BIT
4202 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4203 {
4204 /* Align the pointer using: ap = (ap + align - 1) & -align,
4205 where align is 2 * UNITS_PER_WORD. */
4206 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4207 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4208 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4209 build_int_2 (-2 * UNITS_PER_WORD, -1));
4210 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4211 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4212 }
4213
4214 /* Emit code to set addr_rtx to the valist, and postincrement
4215 the valist by the size of the argument, rounded up to the
4216 next word. */
4217 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4218 size_int (rsize));
4219 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4220 if (r != addr_rtx)
4221 emit_move_insn (addr_rtx, r);
4222
4223 /* Flush the POSTINCREMENT. */
4224 emit_queue();
4225 }
4226 else
4227 {
4228 /* Not a simple merged stack. */
4229
4230 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4231 tree ovfl, top, off;
4232 rtx lab_over = NULL_RTX, lab_false;
4233 HOST_WIDE_INT osize;
4234
4235 f_ovfl = TYPE_FIELDS (va_list_type_node);
4236 f_gtop = TREE_CHAIN (f_ovfl);
4237 f_ftop = TREE_CHAIN (f_gtop);
4238 f_goff = TREE_CHAIN (f_ftop);
4239 f_foff = TREE_CHAIN (f_goff);
4240
4241 /* We maintain separate pointers and offsets for floating-point
4242 and integer arguments, but we need similar code in both cases.
4243 Let:
4244
4245 TOP be the top of the register save area;
4246 OFF be the offset from TOP of the next register;
4247 ADDR_RTX be the address of the argument;
4248 RSIZE be the number of bytes used to store the argument
4249 when it's in the register save area;
4250 OSIZE be the number of bytes used to store it when it's
4251 in the stack overflow area; and
4252 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4253
4254 The code we want is:
4255
4256 1: off &= -rsize; // round down
4257 2: if (off != 0)
4258 3: {
4259 4: addr_rtx = top - off;
4260 5: off -= rsize;
4261 6: }
4262 7: else
4263 8: {
4264 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4265 10: addr_rtx = ovfl + PADDING;
4266 11: ovfl += osize;
4267 14: }
4268
4269 [1] and [9] can sometimes be optimized away. */
4270
4271 lab_false = gen_label_rtx ();
4272 lab_over = gen_label_rtx ();
4273
4274 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4275 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4276 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4277 {
4278 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4279 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4280
4281 /* When floating-point registers are saved to the stack,
4282 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4283 of the float's precision. */
4284 rsize = UNITS_PER_HWFPVALUE;
4285 }
4286 else
4287 {
4288 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4289 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4290 if (rsize > UNITS_PER_WORD)
4291 {
4292 /* [1] Emit code for: off &= -rsize. */
4293 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4294 build_int_2 (-rsize, -1));
4295 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4296 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4297 }
4298 }
4299 /* Every overflow argument must take up at least UNITS_PER_WORD
4300 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
4301 than that, such as in the combination -mgp64 -msingle-float
4302 -fshort-double. Doubles passed in registers will then take
4303 up UNITS_PER_HWFPVALUE bytes, but those passed on the stack
4304 take up UNITS_PER_WORD bytes. */
4305 osize = MAX (rsize, UNITS_PER_WORD);
4306
4307 /* [2] Emit code to branch if off == 0. */
4308 r = expand_expr (off, NULL_RTX, TYPE_MODE (TREE_TYPE (off)),
4309 EXPAND_NORMAL);
4310 emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
4311 1, lab_false);
4312
4313 /* [4] Emit code for: addr_rtx = top - off. */
4314 t = build (MINUS_EXPR, TREE_TYPE (top), top, off);
4315 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4316 if (r != addr_rtx)
4317 emit_move_insn (addr_rtx, r);
4318
4319 /* [5] Emit code for: off -= rsize. */
4320 t = build (MINUS_EXPR, TREE_TYPE (off), off, build_int_2 (rsize, 0));
4321 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4322 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4323
4324 /* [7] Emit code to jump over the else clause, then the label
4325 that starts it. */
4326 emit_queue();
4327 emit_jump (lab_over);
4328 emit_barrier ();
4329 emit_label (lab_false);
4330
4331 if (osize > UNITS_PER_WORD)
4332 {
4333 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4334 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl,
4335 build_int_2 (osize - 1, 0));
4336 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t,
4337 build_int_2 (-osize, -1));
4338 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4339 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4340 }
4341
4342 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4343 post-increment ovfl by osize. On big-endian machines,
4344 the argument has OSIZE - RSIZE bytes of leading padding. */
4345 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl,
4346 size_int (osize));
4347 if (BYTES_BIG_ENDIAN && osize > rsize)
4348 t = build (PLUS_EXPR, TREE_TYPE (t), t,
4349 build_int_2 (osize - rsize, 0));
4350 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4351 if (r != addr_rtx)
4352 emit_move_insn (addr_rtx, r);
4353
4354 emit_queue();
4355 emit_label (lab_over);
4356 }
4357 if (BYTES_BIG_ENDIAN && rsize != size)
4358 addr_rtx = plus_constant (addr_rtx, rsize - size);
4359 if (indirect)
4360 {
4361 addr_rtx = force_reg (Pmode, addr_rtx);
4362 r = gen_rtx_MEM (Pmode, addr_rtx);
4363 set_mem_alias_set (r, get_varargs_alias_set ());
4364 emit_move_insn (addr_rtx, r);
4365 }
4366 return addr_rtx;
4367 }
4368 else
4369 {
4370 /* Not EABI. */
4371 int align;
4372 HOST_WIDE_INT min_offset;
4373
4374 /* ??? The original va-mips.h did always align, despite the fact
4375 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4376 increment mechanism. */
4377
4378 if ((mips_abi == ABI_N32 || mips_abi == ABI_64)
4379 && TYPE_ALIGN (type) > 64)
4380 align = 16;
4381 else if (TARGET_64BIT)
4382 align = 8;
4383 else if (TYPE_ALIGN (type) > 32)
4384 align = 8;
4385 else
4386 align = 4;
4387
4388 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4389 build_int_2 (align - 1, 0));
4390 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4391
4392 /* If arguments of type TYPE must be passed on the stack,
4393 set MIN_OFFSET to the offset of the first stack parameter. */
4394 if (!MUST_PASS_IN_STACK (TYPE_MODE (type), type))
4395 min_offset = 0;
4396 else if (TARGET_NEWABI)
4397 min_offset = current_function_pretend_args_size;
4398 else
4399 min_offset = REG_PARM_STACK_SPACE (current_function_decl);
4400
4401 /* Make sure the new address is at least MIN_OFFSET bytes from
4402 the incoming argument pointer. */
4403 if (min_offset > 0)
4404 t = build (MAX_EXPR, TREE_TYPE (valist), t,
4405 make_tree (TREE_TYPE (valist),
4406 plus_constant (virtual_incoming_args_rtx,
4407 min_offset)));
4408
4409 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4410 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4411
4412 /* Everything past the alignment is standard. */
4413 return std_expand_builtin_va_arg (valist, type);
4414 }
4415 }
4416
4417 /* Return true if it is possible to use left/right accesses for a
4418 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4419 returning true, update *OP, *LEFT and *RIGHT as follows:
4420
4421 *OP is a BLKmode reference to the whole field.
4422
4423 *LEFT is a QImode reference to the first byte if big endian or
4424 the last byte if little endian. This address can be used in the
4425 left-side instructions (lwl, swl, ldl, sdl).
4426
4427 *RIGHT is a QImode reference to the opposite end of the field and
4428 can be used in the parterning right-side instruction. */
4429
4430 static bool
mips_get_unaligned_mem(rtx * op,unsigned int width,int bitpos,rtx * left,rtx * right)4431 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4432 rtx *left, rtx *right)
4433 {
4434 rtx first, last;
4435
4436 /* Check that the operand really is a MEM. Not all the extv and
4437 extzv predicates are checked. */
4438 if (GET_CODE (*op) != MEM)
4439 return false;
4440
4441 /* Check that the size is valid. */
4442 if (width != 32 && (!TARGET_64BIT || width != 64))
4443 return false;
4444
4445 /* We can only access byte-aligned values. Since we are always passed
4446 a reference to the first byte of the field, it is not necessary to
4447 do anything with BITPOS after this check. */
4448 if (bitpos % BITS_PER_UNIT != 0)
4449 return false;
4450
4451 /* Reject aligned bitfields: we want to use a normal load or store
4452 instead of a left/right pair. */
4453 if (MEM_ALIGN (*op) >= width)
4454 return false;
4455
4456 /* Adjust *OP to refer to the whole field. This also has the effect
4457 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4458 *op = adjust_address (*op, BLKmode, 0);
4459 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4460
4461 /* Get references to both ends of the field. We deliberately don't
4462 use the original QImode *OP for FIRST since the new BLKmode one
4463 might have a simpler address. */
4464 first = adjust_address (*op, QImode, 0);
4465 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4466
4467 /* Allocate to LEFT and RIGHT according to endiannes. LEFT should
4468 be the upper word and RIGHT the lower word. */
4469 if (TARGET_BIG_ENDIAN)
4470 *left = first, *right = last;
4471 else
4472 *left = last, *right = first;
4473
4474 return true;
4475 }
4476
4477
4478 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4479 Return true on success. We only handle cases where zero_extract is
4480 equivalent to sign_extract. */
4481
4482 bool
mips_expand_unaligned_load(rtx dest,rtx src,unsigned int width,int bitpos)4483 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4484 {
4485 rtx left, right, temp;
4486
4487 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4488 paradoxical word_mode subreg. This is the only case in which
4489 we allow the destination to be larger than the source. */
4490 if (GET_CODE (dest) == SUBREG
4491 && GET_MODE (dest) == DImode
4492 && SUBREG_BYTE (dest) == 0
4493 && GET_MODE (SUBREG_REG (dest)) == SImode)
4494 dest = SUBREG_REG (dest);
4495
4496 /* After the above adjustment, the destination must be the same
4497 width as the source. */
4498 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4499 return false;
4500
4501 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4502 return false;
4503
4504 temp = gen_reg_rtx (GET_MODE (dest));
4505 if (GET_MODE (dest) == DImode)
4506 {
4507 emit_insn (gen_mov_ldl (temp, src, left));
4508 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4509 }
4510 else
4511 {
4512 emit_insn (gen_mov_lwl (temp, src, left));
4513 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4514 }
4515 return true;
4516 }
4517
4518
4519 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4520 true on success. */
4521
4522 bool
mips_expand_unaligned_store(rtx dest,rtx src,unsigned int width,int bitpos)4523 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4524 {
4525 rtx left, right;
4526
4527 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4528 return false;
4529
4530 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4531
4532 if (GET_MODE (src) == DImode)
4533 {
4534 emit_insn (gen_mov_sdl (dest, src, left));
4535 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4536 }
4537 else
4538 {
4539 emit_insn (gen_mov_swl (dest, src, left));
4540 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4541 }
4542 return true;
4543 }
4544
4545 /* Set up globals to generate code for the ISA or processor
4546 described by INFO. */
4547
4548 static void
mips_set_architecture(const struct mips_cpu_info * info)4549 mips_set_architecture (const struct mips_cpu_info *info)
4550 {
4551 if (info != 0)
4552 {
4553 mips_arch_info = info;
4554 mips_arch = info->cpu;
4555 mips_isa = info->isa;
4556 }
4557 }
4558
4559
4560 /* Likewise for tuning. */
4561
4562 static void
mips_set_tune(const struct mips_cpu_info * info)4563 mips_set_tune (const struct mips_cpu_info *info)
4564 {
4565 if (info != 0)
4566 {
4567 mips_tune_info = info;
4568 mips_tune = info->cpu;
4569 }
4570 }
4571
4572
4573 /* Set up the threshold for data to go into the small data area, instead
4574 of the normal data area, and detect any conflicts in the switches. */
4575
4576 void
override_options(void)4577 override_options (void)
4578 {
4579 int i, start, regno;
4580 enum machine_mode mode;
4581
4582 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4583
4584 /* Interpret -mabi. */
4585 mips_abi = MIPS_ABI_DEFAULT;
4586 if (mips_abi_string != 0)
4587 {
4588 if (strcmp (mips_abi_string, "32") == 0)
4589 mips_abi = ABI_32;
4590 else if (strcmp (mips_abi_string, "o64") == 0)
4591 mips_abi = ABI_O64;
4592 else if (strcmp (mips_abi_string, "n32") == 0)
4593 mips_abi = ABI_N32;
4594 else if (strcmp (mips_abi_string, "64") == 0)
4595 mips_abi = ABI_64;
4596 else if (strcmp (mips_abi_string, "eabi") == 0)
4597 mips_abi = ABI_EABI;
4598 else
4599 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
4600 }
4601
4602 /* The following code determines the architecture and register size.
4603 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4604 The GAS and GCC code should be kept in sync as much as possible. */
4605
4606 if (mips_arch_string != 0)
4607 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
4608
4609 if (mips_isa_string != 0)
4610 {
4611 /* Handle -mipsN. */
4612 char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
4613 const struct mips_cpu_info *isa_info;
4614
4615 isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
4616 free (whole_isa_str);
4617
4618 /* -march takes precedence over -mipsN, since it is more descriptive.
4619 There's no harm in specifying both as long as the ISA levels
4620 are the same. */
4621 if (mips_arch_info != 0 && mips_isa != isa_info->isa)
4622 error ("-mips%s conflicts with the other architecture options, "
4623 "which specify a MIPS%d processor",
4624 mips_isa_string, mips_isa);
4625
4626 /* Set architecture based on the given option. */
4627 mips_set_architecture (isa_info);
4628 }
4629
4630 if (mips_arch_info == 0)
4631 {
4632 #ifdef MIPS_CPU_STRING_DEFAULT
4633 mips_set_architecture (mips_parse_cpu ("default CPU",
4634 MIPS_CPU_STRING_DEFAULT));
4635 #else
4636 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4637 #endif
4638 }
4639
4640 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4641 error ("-march=%s is not compatible with the selected ABI",
4642 mips_arch_info->name);
4643
4644 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4645 if (mips_tune_string != 0)
4646 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
4647
4648 if (mips_tune_info == 0)
4649 mips_set_tune (mips_arch_info);
4650
4651 if ((target_flags_explicit & MASK_64BIT) != 0)
4652 {
4653 /* The user specified the size of the integer registers. Make sure
4654 it agrees with the ABI and ISA. */
4655 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4656 error ("-mgp64 used with a 32-bit processor");
4657 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4658 error ("-mgp32 used with a 64-bit ABI");
4659 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4660 error ("-mgp64 used with a 32-bit ABI");
4661 }
4662 else
4663 {
4664 /* Infer the integer register size from the ABI and processor.
4665 Restrict ourselves to 32-bit registers if that's all the
4666 processor has, or if the ABI cannot handle 64-bit registers. */
4667 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4668 target_flags &= ~MASK_64BIT;
4669 else
4670 target_flags |= MASK_64BIT;
4671 }
4672
4673 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4674 {
4675 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4676 only one right answer here. */
4677 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4678 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4679 else if (!TARGET_64BIT && TARGET_FLOAT64)
4680 error ("unsupported combination: %s", "-mgp32 -mfp64");
4681 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4682 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4683 }
4684 else
4685 {
4686 /* -msingle-float selects 32-bit float registers. Otherwise the
4687 float registers should be the same size as the integer ones. */
4688 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4689 target_flags |= MASK_FLOAT64;
4690 else
4691 target_flags &= ~MASK_FLOAT64;
4692 }
4693
4694 /* End of code shared with GAS. */
4695
4696 if ((target_flags_explicit & MASK_LONG64) == 0)
4697 {
4698 /* If no type size setting options (-mlong64,-mint64,-mlong32)
4699 were used, then set the type sizes. In the EABI in 64 bit mode,
4700 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
4701 ABI. */
4702 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4703 target_flags |= MASK_LONG64;
4704 else
4705 target_flags &= ~MASK_LONG64;
4706 }
4707
4708 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4709 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4710 {
4711 /* For some configurations, it is useful to have -march control
4712 the default setting of MASK_SOFT_FLOAT. */
4713 switch ((int) mips_arch)
4714 {
4715 case PROCESSOR_R4100:
4716 case PROCESSOR_R4111:
4717 case PROCESSOR_R4120:
4718 target_flags |= MASK_SOFT_FLOAT;
4719 break;
4720
4721 default:
4722 target_flags &= ~MASK_SOFT_FLOAT;
4723 break;
4724 }
4725 }
4726
4727 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
4728 flag_pcc_struct_return = 0;
4729
4730 #if defined(USE_COLLECT2)
4731 /* For IRIX 5 or IRIX 6 with integrated O32 ABI support, USE_COLLECT2 is
4732 always defined when GNU as is not in use, but collect2 is only used
4733 for the O32 ABI, so override the toplev.c and target-def.h defaults
4734 for flag_gnu_linker, TARGET_ASM_{CONSTRUCTOR, DESTRUCTOR} and
4735 TARGET_HAVE_CTORS_DTORS.
4736
4737 Since the IRIX 5 and IRIX 6 O32 assemblers cannot handle named
4738 sections, constructor/destructor handling depends on the ABI in use.
4739
4740 Since USE_COLLECT2 is defined, we only need to restore the non-collect2
4741 defaults for the N32/N64 ABIs. */
4742 if (TARGET_IRIX && !TARGET_SGI_O32_AS)
4743 {
4744 targetm.have_ctors_dtors = true;
4745 targetm.asm_out.constructor = default_named_section_asm_out_constructor;
4746 targetm.asm_out.destructor = default_named_section_asm_out_destructor;
4747 }
4748 #endif
4749
4750 /* Handle some quirks of the IRIX 5 and IRIX 6 O32 assemblers. */
4751
4752 if (TARGET_SGI_O32_AS)
4753 {
4754 /* They don't recognize `.[248]byte'. */
4755 targetm.asm_out.unaligned_op.hi = "\t.align 0\n\t.half\t";
4756 targetm.asm_out.unaligned_op.si = "\t.align 0\n\t.word\t";
4757 /* The IRIX 6 O32 assembler gives an error for `align 0; .dword',
4758 contrary to the documentation, so disable it. */
4759 targetm.asm_out.unaligned_op.di = NULL;
4760
4761 /* They cannot handle named sections. */
4762 targetm.have_named_sections = false;
4763 /* Therefore, EH_FRAME_SECTION_NAME isn't defined and we must use
4764 collect2. */
4765 targetm.terminate_dw2_eh_frame_info = true;
4766 targetm.asm_out.eh_frame_section = collect2_eh_frame_section;
4767
4768 /* They cannot handle debug information. */
4769 if (write_symbols != NO_DEBUG)
4770 {
4771 /* Adapt wording to IRIX version: IRIX 5 only had a single ABI,
4772 so -mabi=32 isn't usually specified. */
4773 if (TARGET_IRIX5)
4774 inform ("-g is only supported using GNU as,");
4775 else
4776 inform ("-g is only supported using GNU as with -mabi=32,");
4777 inform ("-g option disabled");
4778 write_symbols = NO_DEBUG;
4779 }
4780 }
4781
4782 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4783 {
4784 /* If neither -mbranch-likely nor -mno-branch-likely was given
4785 on the command line, set MASK_BRANCHLIKELY based on the target
4786 architecture.
4787
4788 By default, we enable use of Branch Likely instructions on
4789 all architectures which support them except for MIPS32 and MIPS64
4790 (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
4791 implement them).
4792
4793 The MIPS32 and MIPS64 architecture specifications say "Software
4794 is strongly encouraged to avoid use of Branch Likely
4795 instructions, as they will be removed from a future revision
4796 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4797 issue those instructions unless instructed to do so by
4798 -mbranch-likely. */
4799 if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64))
4800 target_flags |= MASK_BRANCHLIKELY;
4801 else
4802 target_flags &= ~MASK_BRANCHLIKELY;
4803 }
4804 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4805 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
4806
4807 /* The effect of -mabicalls isn't defined for the EABI. */
4808 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4809 {
4810 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4811 target_flags &= ~MASK_ABICALLS;
4812 }
4813
4814 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4815 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4816 /* ??? -non_shared turns off pic code generation, but this is not
4817 implemented. */
4818 if (TARGET_ABICALLS)
4819 {
4820 flag_pic = 1;
4821 if (mips_section_threshold > 0)
4822 warning ("-G is incompatible with PIC code which is the default");
4823 }
4824
4825 /* The MIPS and SGI o32 assemblers expect small-data variables to
4826 be declared before they are used. Although we once had code to
4827 do this, it was very invasive and fragile. It no longer seems
4828 worth the effort. */
4829 if (!TARGET_EXPLICIT_RELOCS && !TARGET_GAS)
4830 mips_section_threshold = 0;
4831
4832 /* We switch to small data sections using ".section", which the native
4833 o32 irix assemblers don't understand. Disable -G accordingly.
4834 We must do this regardless of command-line options since otherwise
4835 the compiler would abort. */
4836 if (!targetm.have_named_sections)
4837 mips_section_threshold = 0;
4838
4839 /* -membedded-pic is a form of PIC code suitable for embedded
4840 systems. All calls are made using PC relative addressing, and
4841 all data is addressed using the $gp register. This requires gas,
4842 which does most of the work, and GNU ld, which automatically
4843 expands PC relative calls which are out of range into a longer
4844 instruction sequence. All gcc really does differently is
4845 generate a different sequence for a switch. */
4846 if (TARGET_EMBEDDED_PIC)
4847 {
4848 flag_pic = 1;
4849 if (TARGET_ABICALLS)
4850 warning ("-membedded-pic and -mabicalls are incompatible");
4851
4852 if (g_switch_set)
4853 warning ("-G and -membedded-pic are incompatible");
4854
4855 /* Setting mips_section_threshold is not required, because gas
4856 will force everything to be GP addressable anyhow, but
4857 setting it will cause gcc to make better estimates of the
4858 number of instructions required to access a particular data
4859 item. */
4860 mips_section_threshold = 0x7fffffff;
4861 }
4862
4863 /* mips_split_addresses is a half-way house between explicit
4864 relocations and the traditional assembler macros. It can
4865 split absolute 32-bit symbolic constants into a high/lo_sum
4866 pair but uses macros for other sorts of access.
4867
4868 Like explicit relocation support for REL targets, it relies
4869 on GNU extensions in the assembler and the linker.
4870
4871 Although this code should work for -O0, it has traditionally
4872 been treated as an optimization. */
4873 if (TARGET_GAS && !TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4874 && optimize && !flag_pic
4875 && !ABI_HAS_64BIT_SYMBOLS)
4876 mips_split_addresses = 1;
4877 else
4878 mips_split_addresses = 0;
4879
4880 /* -mexplicit-relocs doesn't yet support non-PIC n64. We don't know
4881 how to generate %highest/%higher/%hi/%lo sequences. */
4882 if (mips_abi == ABI_64 && !TARGET_ABICALLS)
4883 {
4884 if ((target_flags_explicit & target_flags & MASK_EXPLICIT_RELOCS) != 0)
4885 sorry ("non-PIC n64 with explicit relocations");
4886 target_flags &= ~MASK_EXPLICIT_RELOCS;
4887 }
4888
4889 /* Explicit relocations for "old" ABIs are a GNU extension. Unless
4890 the user has said otherwise, assume that they are not available
4891 with assemblers other than gas. */
4892 if (!TARGET_NEWABI && !TARGET_GAS
4893 && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4894 target_flags &= ~MASK_EXPLICIT_RELOCS;
4895
4896 /* Make -mabicalls -fno-unit-at-a-time imply -mno-explicit-relocs
4897 unless the user says otherwise.
4898
4899 There are two problems here:
4900
4901 (1) The value of an R_MIPS_GOT16 relocation depends on whether
4902 the symbol is local or global. We therefore need to know
4903 a symbol's binding before refering to it using %got().
4904
4905 (2) R_MIPS_CALL16 can only be applied to global symbols.
4906
4907 When not using -funit-at-a-time, a symbol's binding may change
4908 after it has been used. For example, the C++ front-end will
4909 initially assume that the typeinfo for an incomplete type will be
4910 comdat, on the basis that the type could be completed later in the
4911 file. But if the type never is completed, the typeinfo will become
4912 local instead. */
4913 if (!flag_unit_at_a_time
4914 && TARGET_ABICALLS
4915 && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4916 target_flags &= ~MASK_EXPLICIT_RELOCS;
4917
4918 /* -mrnames says to use the MIPS software convention for register
4919 names instead of the hardware names (ie, $a0 instead of $4).
4920 We do this by switching the names in mips_reg_names, which the
4921 reg_names points into via the REGISTER_NAMES macro. */
4922
4923 if (TARGET_NAME_REGS)
4924 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
4925
4926 /* When compiling for the mips16, we can not use floating point. We
4927 record the original hard float value in mips16_hard_float. */
4928 if (TARGET_MIPS16)
4929 {
4930 if (TARGET_SOFT_FLOAT)
4931 mips16_hard_float = 0;
4932 else
4933 mips16_hard_float = 1;
4934 target_flags |= MASK_SOFT_FLOAT;
4935
4936 /* Don't run the scheduler before reload, since it tends to
4937 increase register pressure. */
4938 flag_schedule_insns = 0;
4939
4940 /* Silently disable -mexplicit-relocs since it doesn't apply
4941 to mips16 code. Even so, it would overly pedantic to warn
4942 about "-mips16 -mexplicit-relocs", especially given that
4943 we use a %gprel() operator. */
4944 target_flags &= ~MASK_EXPLICIT_RELOCS;
4945 }
4946
4947 /* When using explicit relocs, we call dbr_schedule from within
4948 mips_reorg. */
4949 if (TARGET_EXPLICIT_RELOCS)
4950 {
4951 mips_flag_delayed_branch = flag_delayed_branch;
4952 flag_delayed_branch = 0;
4953 }
4954
4955 #ifdef MIPS_TFMODE_FORMAT
4956 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4957 #endif
4958
4959 mips_print_operand_punct['?'] = 1;
4960 mips_print_operand_punct['#'] = 1;
4961 mips_print_operand_punct['/'] = 1;
4962 mips_print_operand_punct['&'] = 1;
4963 mips_print_operand_punct['!'] = 1;
4964 mips_print_operand_punct['*'] = 1;
4965 mips_print_operand_punct['@'] = 1;
4966 mips_print_operand_punct['.'] = 1;
4967 mips_print_operand_punct['('] = 1;
4968 mips_print_operand_punct[')'] = 1;
4969 mips_print_operand_punct['['] = 1;
4970 mips_print_operand_punct[']'] = 1;
4971 mips_print_operand_punct['<'] = 1;
4972 mips_print_operand_punct['>'] = 1;
4973 mips_print_operand_punct['{'] = 1;
4974 mips_print_operand_punct['}'] = 1;
4975 mips_print_operand_punct['^'] = 1;
4976 mips_print_operand_punct['$'] = 1;
4977 mips_print_operand_punct['+'] = 1;
4978 mips_print_operand_punct['~'] = 1;
4979
4980 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4981 mips_char_to_class['e'] = M16_NA_REGS;
4982 mips_char_to_class['t'] = T_REG;
4983 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4984 mips_char_to_class['h'] = HI_REG;
4985 mips_char_to_class['l'] = LO_REG;
4986 mips_char_to_class['x'] = MD_REGS;
4987 mips_char_to_class['b'] = ALL_REGS;
4988 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4989 TARGET_MIPS16 ? M16_NA_REGS :
4990 GR_REGS);
4991 mips_char_to_class['e'] = LEA_REGS;
4992 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4993 mips_char_to_class['y'] = GR_REGS;
4994 mips_char_to_class['z'] = ST_REGS;
4995 mips_char_to_class['B'] = COP0_REGS;
4996 mips_char_to_class['C'] = COP2_REGS;
4997 mips_char_to_class['D'] = COP3_REGS;
4998
4999 /* Set up array to map GCC register number to debug register number.
5000 Ignore the special purpose register numbers. */
5001
5002 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5003 mips_dbx_regno[i] = -1;
5004
5005 start = GP_DBX_FIRST - GP_REG_FIRST;
5006 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5007 mips_dbx_regno[i] = i + start;
5008
5009 start = FP_DBX_FIRST - FP_REG_FIRST;
5010 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5011 mips_dbx_regno[i] = i + start;
5012
5013 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
5014 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
5015
5016 /* Set up array giving whether a given register can hold a given mode. */
5017
5018 for (mode = VOIDmode;
5019 mode != MAX_MACHINE_MODE;
5020 mode = (enum machine_mode) ((int)mode + 1))
5021 {
5022 register int size = GET_MODE_SIZE (mode);
5023 register enum mode_class class = GET_MODE_CLASS (mode);
5024
5025 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5026 {
5027 register int temp;
5028
5029 if (mode == CCmode)
5030 {
5031 if (! ISA_HAS_8CC)
5032 temp = (regno == FPSW_REGNUM);
5033 else
5034 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5035 || FP_REG_P (regno));
5036 }
5037
5038 else if (GP_REG_P (regno))
5039 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5040
5041 else if (FP_REG_P (regno))
5042 temp = ((regno % FP_INC) == 0)
5043 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
5044 && size <= UNITS_PER_FPVALUE)
5045 /* Allow integer modes that fit into a single
5046 register. We need to put integers into FPRs
5047 when using instructions like cvt and trunc. */
5048 || (class == MODE_INT && size <= UNITS_PER_FPREG)
5049 /* Allow TFmode for CCmode reloads. */
5050 || (ISA_HAS_8CC && mode == TFmode));
5051
5052 else if (MD_REG_P (regno))
5053 temp = (class == MODE_INT
5054 && (size <= UNITS_PER_WORD
5055 || (regno == MD_REG_FIRST
5056 && size == 2 * UNITS_PER_WORD)));
5057
5058 else if (ALL_COP_REG_P (regno))
5059 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5060 else
5061 temp = 0;
5062
5063 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5064 }
5065 }
5066
5067 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5068 initialized yet, so we can't use that here. */
5069 gpr_mode = TARGET_64BIT ? DImode : SImode;
5070
5071 /* Provide default values for align_* for 64-bit targets. */
5072 if (TARGET_64BIT && !TARGET_MIPS16)
5073 {
5074 if (align_loops == 0)
5075 align_loops = 8;
5076 if (align_jumps == 0)
5077 align_jumps = 8;
5078 if (align_functions == 0)
5079 align_functions = 8;
5080 }
5081
5082 /* Function to allocate machine-dependent function status. */
5083 init_machine_status = &mips_init_machine_status;
5084
5085 /* Create a unique alias set for GOT references. */
5086 mips_got_alias_set = new_alias_set ();
5087
5088 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5089 {
5090 mips_split_p[SYMBOL_GENERAL] = true;
5091 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5092 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5093 }
5094
5095 if (TARGET_MIPS16)
5096 {
5097 /* The high part is provided by a pseudo copy of $gp. */
5098 mips_split_p[SYMBOL_SMALL_DATA] = true;
5099 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5100 }
5101
5102 if (TARGET_EXPLICIT_RELOCS)
5103 {
5104 /* Small data constants are kept whole until after reload,
5105 then lowered by mips_rewrite_small_data. */
5106 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5107
5108 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5109 if (TARGET_NEWABI)
5110 {
5111 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5112 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5113 }
5114 else
5115 {
5116 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5117 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5118 }
5119
5120 if (TARGET_XGOT)
5121 {
5122 /* The HIGH and LO_SUM are matched by special .md patterns. */
5123 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5124
5125 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5126 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5127 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5128
5129 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5130 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5131 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5132 }
5133 else
5134 {
5135 if (TARGET_NEWABI)
5136 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5137 else
5138 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5139 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5140 }
5141 }
5142
5143 if (TARGET_NEWABI)
5144 {
5145 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5146 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5147 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5148 }
5149 }
5150
5151 /* Implement CONDITIONAL_REGISTER_USAGE. */
5152
5153 void
mips_conditional_register_usage(void)5154 mips_conditional_register_usage (void)
5155 {
5156 if (!TARGET_HARD_FLOAT)
5157 {
5158 int regno;
5159
5160 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5161 fixed_regs[regno] = call_used_regs[regno] = 1;
5162 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5163 fixed_regs[regno] = call_used_regs[regno] = 1;
5164 }
5165 else if (! ISA_HAS_8CC)
5166 {
5167 int regno;
5168
5169 /* We only have a single condition code register. We
5170 implement this by hiding all the condition code registers,
5171 and generating RTL that refers directly to ST_REG_FIRST. */
5172 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5173 fixed_regs[regno] = call_used_regs[regno] = 1;
5174 }
5175 /* In mips16 mode, we permit the $t temporary registers to be used
5176 for reload. We prohibit the unused $s registers, since they
5177 are caller saved, and saving them via a mips16 register would
5178 probably waste more time than just reloading the value. */
5179 if (TARGET_MIPS16)
5180 {
5181 fixed_regs[18] = call_used_regs[18] = 1;
5182 fixed_regs[19] = call_used_regs[19] = 1;
5183 fixed_regs[20] = call_used_regs[20] = 1;
5184 fixed_regs[21] = call_used_regs[21] = 1;
5185 fixed_regs[22] = call_used_regs[22] = 1;
5186 fixed_regs[23] = call_used_regs[23] = 1;
5187 fixed_regs[26] = call_used_regs[26] = 1;
5188 fixed_regs[27] = call_used_regs[27] = 1;
5189 fixed_regs[30] = call_used_regs[30] = 1;
5190 }
5191 /* fp20-23 are now caller saved. */
5192 if (mips_abi == ABI_64)
5193 {
5194 int regno;
5195 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5196 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5197 }
5198 /* Odd registers from fp21 to fp31 are now caller saved. */
5199 if (mips_abi == ABI_N32)
5200 {
5201 int regno;
5202 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5203 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5204 }
5205 }
5206
5207 /* Allocate a chunk of memory for per-function machine-dependent data. */
5208 static struct machine_function *
mips_init_machine_status(void)5209 mips_init_machine_status (void)
5210 {
5211 return ((struct machine_function *)
5212 ggc_alloc_cleared (sizeof (struct machine_function)));
5213 }
5214
5215 /* On the mips16, we want to allocate $24 (T_REG) before other
5216 registers for instructions for which it is possible. This helps
5217 avoid shuffling registers around in order to set up for an xor,
5218 encouraging the compiler to use a cmp instead. */
5219
5220 void
mips_order_regs_for_local_alloc(void)5221 mips_order_regs_for_local_alloc (void)
5222 {
5223 register int i;
5224
5225 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5226 reg_alloc_order[i] = i;
5227
5228 if (TARGET_MIPS16)
5229 {
5230 /* It really doesn't matter where we put register 0, since it is
5231 a fixed register anyhow. */
5232 reg_alloc_order[0] = 24;
5233 reg_alloc_order[24] = 0;
5234 }
5235 }
5236
5237
5238 /* The MIPS debug format wants all automatic variables and arguments
5239 to be in terms of the virtual frame pointer (stack pointer before
5240 any adjustment in the function), while the MIPS 3.0 linker wants
5241 the frame pointer to be the stack pointer after the initial
5242 adjustment. So, we do the adjustment here. The arg pointer (which
5243 is eliminated) points to the virtual frame pointer, while the frame
5244 pointer (which may be eliminated) points to the stack pointer after
5245 the initial adjustments. */
5246
5247 HOST_WIDE_INT
mips_debugger_offset(rtx addr,HOST_WIDE_INT offset)5248 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5249 {
5250 rtx offset2 = const0_rtx;
5251 rtx reg = eliminate_constant_term (addr, &offset2);
5252
5253 if (offset == 0)
5254 offset = INTVAL (offset2);
5255
5256 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5257 || reg == hard_frame_pointer_rtx)
5258 {
5259 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5260 ? compute_frame_size (get_frame_size ())
5261 : cfun->machine->frame.total_size;
5262
5263 /* MIPS16 frame is smaller */
5264 if (frame_pointer_needed && TARGET_MIPS16)
5265 frame_size -= cfun->machine->frame.args_size;
5266
5267 offset = offset - frame_size;
5268 }
5269
5270 /* sdbout_parms does not want this to crash for unrecognized cases. */
5271 #if 0
5272 else if (reg != arg_pointer_rtx)
5273 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5274 addr);
5275 #endif
5276
5277 return offset;
5278 }
5279
5280 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5281
5282 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5283 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5284 'h' OP is HIGH, prints %hi(X),
5285 'd' output integer constant in decimal,
5286 'z' if the operand is 0, use $0 instead of normal operand.
5287 'D' print second part of double-word register or memory operand.
5288 'L' print low-order register of double-word register operand.
5289 'M' print high-order register of double-word register operand.
5290 'C' print part of opcode for a branch condition.
5291 'F' print part of opcode for a floating-point branch condition.
5292 'N' print part of opcode for a branch condition, inverted.
5293 'W' print part of opcode for a floating-point branch condition, inverted.
5294 'S' OP is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5295 'B' print 'z' for EQ, 'n' for NE
5296 'b' print 'n' for EQ, 'z' for NE
5297 'T' print 'f' for EQ, 't' for NE
5298 't' print 't' for EQ, 'f' for NE
5299 'Z' print register and a comma, but print nothing for $fcc0
5300 'R' print the reloc associated with LO_SUM
5301
5302 The punctuation characters are:
5303
5304 '(' Turn on .set noreorder
5305 ')' Turn on .set reorder
5306 '[' Turn on .set noat
5307 ']' Turn on .set at
5308 '<' Turn on .set nomacro
5309 '>' Turn on .set macro
5310 '{' Turn on .set volatile (not GAS)
5311 '}' Turn on .set novolatile (not GAS)
5312 '&' Turn on .set noreorder if filling delay slots
5313 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5314 '!' Turn on .set nomacro if filling delay slots
5315 '#' Print nop if in a .set noreorder section.
5316 '/' Like '#', but does nothing within a delayed branch sequence
5317 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5318 '@' Print the name of the assembler temporary register (at or $1).
5319 '.' Print the name of the register with a hard-wired zero (zero or $0).
5320 '^' Print the name of the pic call-through register (t9 or $25).
5321 '$' Print the name of the stack pointer register (sp or $29).
5322 '+' Print the name of the gp register (usually gp or $28).
5323 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5324
5325 void
print_operand(FILE * file,rtx op,int letter)5326 print_operand (FILE *file, rtx op, int letter)
5327 {
5328 register enum rtx_code code;
5329
5330 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5331 {
5332 switch (letter)
5333 {
5334 case '?':
5335 if (mips_branch_likely)
5336 putc ('l', file);
5337 break;
5338
5339 case '@':
5340 fputs (reg_names [GP_REG_FIRST + 1], file);
5341 break;
5342
5343 case '^':
5344 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5345 break;
5346
5347 case '.':
5348 fputs (reg_names [GP_REG_FIRST + 0], file);
5349 break;
5350
5351 case '$':
5352 fputs (reg_names[STACK_POINTER_REGNUM], file);
5353 break;
5354
5355 case '+':
5356 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5357 break;
5358
5359 case '&':
5360 if (final_sequence != 0 && set_noreorder++ == 0)
5361 fputs (".set\tnoreorder\n\t", file);
5362 break;
5363
5364 case '*':
5365 if (final_sequence != 0)
5366 {
5367 if (set_noreorder++ == 0)
5368 fputs (".set\tnoreorder\n\t", file);
5369
5370 if (set_nomacro++ == 0)
5371 fputs (".set\tnomacro\n\t", file);
5372 }
5373 break;
5374
5375 case '!':
5376 if (final_sequence != 0 && set_nomacro++ == 0)
5377 fputs ("\n\t.set\tnomacro", file);
5378 break;
5379
5380 case '#':
5381 if (set_noreorder != 0)
5382 fputs ("\n\tnop", file);
5383 break;
5384
5385 case '/':
5386 /* Print an extra newline so that the delayed insn is separated
5387 from the following ones. This looks neater and is consistent
5388 with non-nop delayed sequences. */
5389 if (set_noreorder != 0 && final_sequence == 0)
5390 fputs ("\n\tnop\n", file);
5391 break;
5392
5393 case '(':
5394 if (set_noreorder++ == 0)
5395 fputs (".set\tnoreorder\n\t", file);
5396 break;
5397
5398 case ')':
5399 if (set_noreorder == 0)
5400 error ("internal error: %%) found without a %%( in assembler pattern");
5401
5402 else if (--set_noreorder == 0)
5403 fputs ("\n\t.set\treorder", file);
5404
5405 break;
5406
5407 case '[':
5408 if (set_noat++ == 0)
5409 fputs (".set\tnoat\n\t", file);
5410 break;
5411
5412 case ']':
5413 if (set_noat == 0)
5414 error ("internal error: %%] found without a %%[ in assembler pattern");
5415 else if (--set_noat == 0)
5416 fputs ("\n\t.set\tat", file);
5417
5418 break;
5419
5420 case '<':
5421 if (set_nomacro++ == 0)
5422 fputs (".set\tnomacro\n\t", file);
5423 break;
5424
5425 case '>':
5426 if (set_nomacro == 0)
5427 error ("internal error: %%> found without a %%< in assembler pattern");
5428 else if (--set_nomacro == 0)
5429 fputs ("\n\t.set\tmacro", file);
5430
5431 break;
5432
5433 case '{':
5434 if (set_volatile++ == 0)
5435 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5436 break;
5437
5438 case '}':
5439 if (set_volatile == 0)
5440 error ("internal error: %%} found without a %%{ in assembler pattern");
5441 else if (--set_volatile == 0)
5442 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5443
5444 break;
5445
5446 case '~':
5447 {
5448 if (align_labels_log > 0)
5449 ASM_OUTPUT_ALIGN (file, align_labels_log);
5450 }
5451 break;
5452
5453 default:
5454 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5455 break;
5456 }
5457
5458 return;
5459 }
5460
5461 if (! op)
5462 {
5463 error ("PRINT_OPERAND null pointer");
5464 return;
5465 }
5466
5467 code = GET_CODE (op);
5468
5469 if (letter == 'C')
5470 switch (code)
5471 {
5472 case EQ: fputs ("eq", file); break;
5473 case NE: fputs ("ne", file); break;
5474 case GT: fputs ("gt", file); break;
5475 case GE: fputs ("ge", file); break;
5476 case LT: fputs ("lt", file); break;
5477 case LE: fputs ("le", file); break;
5478 case GTU: fputs ("gtu", file); break;
5479 case GEU: fputs ("geu", file); break;
5480 case LTU: fputs ("ltu", file); break;
5481 case LEU: fputs ("leu", file); break;
5482 default:
5483 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5484 }
5485
5486 else if (letter == 'N')
5487 switch (code)
5488 {
5489 case EQ: fputs ("ne", file); break;
5490 case NE: fputs ("eq", file); break;
5491 case GT: fputs ("le", file); break;
5492 case GE: fputs ("lt", file); break;
5493 case LT: fputs ("ge", file); break;
5494 case LE: fputs ("gt", file); break;
5495 case GTU: fputs ("leu", file); break;
5496 case GEU: fputs ("ltu", file); break;
5497 case LTU: fputs ("geu", file); break;
5498 case LEU: fputs ("gtu", file); break;
5499 default:
5500 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5501 }
5502
5503 else if (letter == 'F')
5504 switch (code)
5505 {
5506 case EQ: fputs ("c1f", file); break;
5507 case NE: fputs ("c1t", file); break;
5508 default:
5509 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5510 }
5511
5512 else if (letter == 'W')
5513 switch (code)
5514 {
5515 case EQ: fputs ("c1t", file); break;
5516 case NE: fputs ("c1f", file); break;
5517 default:
5518 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5519 }
5520
5521 else if (letter == 'h')
5522 {
5523 if (GET_CODE (op) == HIGH)
5524 op = XEXP (op, 0);
5525
5526 print_operand_reloc (file, op, mips_hi_relocs);
5527 }
5528
5529 else if (letter == 'R')
5530 print_operand_reloc (file, op, mips_lo_relocs);
5531
5532 else if (letter == 'S')
5533 {
5534 char buffer[100];
5535
5536 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5537 assemble_name (file, buffer);
5538 }
5539
5540 else if (letter == 'Z')
5541 {
5542 register int regnum;
5543
5544 if (code != REG)
5545 abort ();
5546
5547 regnum = REGNO (op);
5548 if (! ST_REG_P (regnum))
5549 abort ();
5550
5551 if (regnum != ST_REG_FIRST)
5552 fprintf (file, "%s,", reg_names[regnum]);
5553 }
5554
5555 else if (code == REG || code == SUBREG)
5556 {
5557 register int regnum;
5558
5559 if (code == REG)
5560 regnum = REGNO (op);
5561 else
5562 regnum = true_regnum (op);
5563
5564 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5565 || (letter == 'L' && WORDS_BIG_ENDIAN)
5566 || letter == 'D')
5567 regnum++;
5568
5569 fprintf (file, "%s", reg_names[regnum]);
5570 }
5571
5572 else if (code == MEM)
5573 {
5574 if (letter == 'D')
5575 output_address (plus_constant (XEXP (op, 0), 4));
5576 else
5577 output_address (XEXP (op, 0));
5578 }
5579
5580 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5581 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5582
5583 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5584 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5585
5586 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5587 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5588
5589 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5590 fputs (reg_names[GP_REG_FIRST], file);
5591
5592 else if (letter == 'd' || letter == 'x' || letter == 'X')
5593 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5594
5595 else if (letter == 'B')
5596 fputs (code == EQ ? "z" : "n", file);
5597 else if (letter == 'b')
5598 fputs (code == EQ ? "n" : "z", file);
5599 else if (letter == 'T')
5600 fputs (code == EQ ? "f" : "t", file);
5601 else if (letter == 't')
5602 fputs (code == EQ ? "t" : "f", file);
5603
5604 else if (CONST_GP_P (op))
5605 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5606
5607 else
5608 output_addr_const (file, op);
5609 }
5610
5611
5612 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5613 RELOCS is the array of relocations to use. */
5614
5615 static void
print_operand_reloc(FILE * file,rtx op,const char ** relocs)5616 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5617 {
5618 enum mips_symbol_type symbol_type;
5619 const char *p;
5620 rtx base;
5621 HOST_WIDE_INT offset;
5622
5623 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5624 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5625
5626 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5627 mips_split_const (op, &base, &offset);
5628 if (UNSPEC_ADDRESS_P (base))
5629 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5630
5631 fputs (relocs[symbol_type], file);
5632 output_addr_const (file, op);
5633 for (p = relocs[symbol_type]; *p != 0; p++)
5634 if (*p == '(')
5635 fputc (')', file);
5636 }
5637
5638 /* Output address operand X to FILE. */
5639
5640 void
print_operand_address(FILE * file,rtx x)5641 print_operand_address (FILE *file, rtx x)
5642 {
5643 struct mips_address_info addr;
5644
5645 if (mips_classify_address (&addr, x, word_mode, true))
5646 switch (addr.type)
5647 {
5648 case ADDRESS_REG:
5649 print_operand (file, addr.offset, 0);
5650 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5651 return;
5652
5653 case ADDRESS_LO_SUM:
5654 print_operand (file, addr.offset, 'R');
5655 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5656 return;
5657
5658 case ADDRESS_CONST_INT:
5659 case ADDRESS_SYMBOLIC:
5660 output_addr_const (file, x);
5661 return;
5662 }
5663 abort ();
5664 }
5665
5666 /* Target hook for assembling integer objects. It appears that the Irix
5667 6 assembler can't handle 64-bit decimal integers, so avoid printing
5668 such an integer here. */
5669
5670 static bool
mips_assemble_integer(rtx x,unsigned int size,int aligned_p)5671 mips_assemble_integer (rtx x, unsigned int size, int aligned_p)
5672 {
5673 if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
5674 {
5675 fputs ("\t.dword\t", asm_out_file);
5676 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
5677 output_addr_const (asm_out_file, x);
5678 else
5679 print_operand (asm_out_file, x, 'X');
5680 fputc ('\n', asm_out_file);
5681 return true;
5682 }
5683 return default_assemble_integer (x, size, aligned_p);
5684 }
5685
5686 /* When using assembler macros, keep track of all of small-data externs
5687 so that mips_file_end can emit the appropriate declarations for them.
5688
5689 In most cases it would be safe (though pointless) to emit .externs
5690 for other symbols too. One exception is when an object is within
5691 the -G limit but declared by the user to be in a section other
5692 than .sbss or .sdata. */
5693
5694 int
mips_output_external(FILE * file ATTRIBUTE_UNUSED,tree decl,const char * name)5695 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5696 {
5697 register struct extern_list *p;
5698
5699 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5700 {
5701 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5702 p->next = extern_head;
5703 p->name = name;
5704 p->size = int_size_in_bytes (TREE_TYPE (decl));
5705 extern_head = p;
5706 }
5707
5708 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5709 {
5710 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5711 p->next = extern_head;
5712 p->name = name;
5713 p->size = -1;
5714 extern_head = p;
5715 }
5716
5717 return 0;
5718 }
5719
5720 #if TARGET_IRIX
5721 void
irix_output_external_libcall(rtx fun)5722 irix_output_external_libcall (rtx fun)
5723 {
5724 register struct extern_list *p;
5725
5726 if (mips_abi == ABI_32)
5727 {
5728 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5729 p->next = extern_head;
5730 p->name = XSTR (fun, 0);
5731 p->size = -1;
5732 extern_head = p;
5733 }
5734 }
5735 #endif
5736
5737 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5738 put out a MIPS ECOFF file and a stab. */
5739
5740 void
mips_output_filename(FILE * stream,const char * name)5741 mips_output_filename (FILE *stream, const char *name)
5742 {
5743 char ltext_label_name[100];
5744
5745 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5746 directives. */
5747 if (write_symbols == DWARF2_DEBUG)
5748 return;
5749 else if (mips_output_filename_first_time)
5750 {
5751 mips_output_filename_first_time = 0;
5752 SET_FILE_NUMBER ();
5753 current_function_file = name;
5754 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5755 /* This tells mips-tfile that stabs will follow. */
5756 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5757 fprintf (stream, "\t#@stabs\n");
5758 }
5759
5760 else if (write_symbols == DBX_DEBUG)
5761 {
5762 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5763 fprintf (stream, "%s", ASM_STABS_OP);
5764 output_quoted_string (stream, name);
5765 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5766 }
5767
5768 else if (name != current_function_file
5769 && strcmp (name, current_function_file) != 0)
5770 {
5771 SET_FILE_NUMBER ();
5772 current_function_file = name;
5773 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5774 }
5775 }
5776
5777 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5778 as well as a .loc, since it is possible that MIPS ECOFF might not be
5779 able to represent the location for inlines that come from a different
5780 file. */
5781
5782 void
mips_output_lineno(FILE * stream,int line)5783 mips_output_lineno (FILE *stream, int line)
5784 {
5785 if (write_symbols == DBX_DEBUG)
5786 {
5787 ++sym_lineno;
5788 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5789 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5790 LOCAL_LABEL_PREFIX, sym_lineno);
5791 }
5792 else
5793 {
5794 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
5795 LABEL_AFTER_LOC (stream);
5796 }
5797 }
5798
5799 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5800 that should be written before the opening quote, such as "\t.ascii\t"
5801 for real string data or "\t# " for a comment. */
5802
5803 void
mips_output_ascii(FILE * stream,const char * string_param,size_t len,const char * prefix)5804 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5805 const char *prefix)
5806 {
5807 size_t i;
5808 int cur_pos = 17;
5809 register const unsigned char *string =
5810 (const unsigned char *)string_param;
5811
5812 fprintf (stream, "%s\"", prefix);
5813 for (i = 0; i < len; i++)
5814 {
5815 register int c = string[i];
5816
5817 switch (c)
5818 {
5819 case '\"':
5820 case '\\':
5821 putc ('\\', stream);
5822 putc (c, stream);
5823 cur_pos += 2;
5824 break;
5825
5826 case TARGET_NEWLINE:
5827 fputs ("\\n", stream);
5828 if (i+1 < len
5829 && (((c = string[i+1]) >= '\040' && c <= '~')
5830 || c == TARGET_TAB))
5831 cur_pos = 32767; /* break right here */
5832 else
5833 cur_pos += 2;
5834 break;
5835
5836 case TARGET_TAB:
5837 fputs ("\\t", stream);
5838 cur_pos += 2;
5839 break;
5840
5841 case TARGET_FF:
5842 fputs ("\\f", stream);
5843 cur_pos += 2;
5844 break;
5845
5846 case TARGET_BS:
5847 fputs ("\\b", stream);
5848 cur_pos += 2;
5849 break;
5850
5851 case TARGET_CR:
5852 fputs ("\\r", stream);
5853 cur_pos += 2;
5854 break;
5855
5856 default:
5857 if (c >= ' ' && c < 0177)
5858 {
5859 putc (c, stream);
5860 cur_pos++;
5861 }
5862 else
5863 {
5864 fprintf (stream, "\\%03o", c);
5865 cur_pos += 4;
5866 }
5867 }
5868
5869 if (cur_pos > 72 && i+1 < len)
5870 {
5871 cur_pos = 17;
5872 fprintf (stream, "\"\n%s\"", prefix);
5873 }
5874 }
5875 fprintf (stream, "\"\n");
5876 }
5877
5878 /* Implement TARGET_ASM_FILE_START. */
5879
5880 static void
mips_file_start(void)5881 mips_file_start (void)
5882 {
5883 default_file_start ();
5884
5885 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5886 inside of a .set noreorder section jumps to a label outside of the .set
5887 noreorder section. Revision 2.20 just set nobopt silently rather than
5888 fixing the bug. */
5889
5890 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5891 fprintf (asm_out_file, "\t.set\tnobopt\n");
5892
5893 if (TARGET_GAS)
5894 {
5895 #if defined(OBJECT_FORMAT_ELF) && !TARGET_IRIX
5896 /* Generate a special section to describe the ABI switches used to
5897 produce the resultant binary. This used to be done by the assembler
5898 setting bits in the ELF header's flags field, but we have run out of
5899 bits. GDB needs this information in order to be able to correctly
5900 debug these binaries. See the function mips_gdbarch_init() in
5901 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5902 causes unnecessary IRIX 6 ld warnings. */
5903 const char * abi_string = NULL;
5904
5905 switch (mips_abi)
5906 {
5907 case ABI_32: abi_string = "abi32"; break;
5908 case ABI_N32: abi_string = "abiN32"; break;
5909 case ABI_64: abi_string = "abi64"; break;
5910 case ABI_O64: abi_string = "abiO64"; break;
5911 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5912 default:
5913 abort ();
5914 }
5915 /* Note - we use fprintf directly rather than called named_section()
5916 because in this way we can avoid creating an allocated section. We
5917 do not want this section to take up any space in the running
5918 executable. */
5919 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5920
5921 /* Restore the default section. */
5922 fprintf (asm_out_file, "\t.previous\n");
5923 #endif
5924 }
5925
5926 /* Generate the pseudo ops that System V.4 wants. */
5927 #ifndef ABICALLS_ASM_OP
5928 #define ABICALLS_ASM_OP "\t.abicalls"
5929 #endif
5930 if (TARGET_ABICALLS)
5931 /* ??? but do not want this (or want pic0) if -non-shared? */
5932 fprintf (asm_out_file, "%s\n", ABICALLS_ASM_OP);
5933
5934 if (TARGET_MIPS16)
5935 fprintf (asm_out_file, "\t.set\tmips16\n");
5936
5937 if (flag_verbose_asm)
5938 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5939 ASM_COMMENT_START,
5940 mips_section_threshold, mips_arch_info->name, mips_isa);
5941 }
5942
5943 #ifdef BSS_SECTION_ASM_OP
5944 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5945 in the use of sbss. */
5946
5947 void
mips_output_aligned_bss(FILE * stream,tree decl,const char * name,unsigned HOST_WIDE_INT size,int align)5948 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5949 unsigned HOST_WIDE_INT size, int align)
5950 {
5951 extern tree last_assemble_variable_decl;
5952
5953 if (mips_in_small_data_p (decl))
5954 named_section (0, ".sbss", 0);
5955 else
5956 bss_section ();
5957 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5958 last_assemble_variable_decl = decl;
5959 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5960 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5961 }
5962 #endif
5963
5964 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5965 .externs for any small-data variables that turned out to be external. */
5966
5967 static void
mips_file_end(void)5968 mips_file_end (void)
5969 {
5970 tree name_tree;
5971 struct extern_list *p;
5972
5973 if (extern_head)
5974 {
5975 fputs ("\n", asm_out_file);
5976
5977 for (p = extern_head; p != 0; p = p->next)
5978 {
5979 name_tree = get_identifier (p->name);
5980
5981 /* Positively ensure only one .extern for any given symbol. */
5982 if (!TREE_ASM_WRITTEN (name_tree)
5983 && TREE_SYMBOL_REFERENCED (name_tree))
5984 {
5985 TREE_ASM_WRITTEN (name_tree) = 1;
5986 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5987 `.global name .text' directive for every used but
5988 undefined function. If we don't, the linker may perform
5989 an optimization (skipping over the insns that set $gp)
5990 when it is unsafe. */
5991 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5992 {
5993 fputs ("\t.globl ", asm_out_file);
5994 assemble_name (asm_out_file, p->name);
5995 fputs (" .text\n", asm_out_file);
5996 }
5997 else
5998 {
5999 fputs ("\t.extern\t", asm_out_file);
6000 assemble_name (asm_out_file, p->name);
6001 fprintf (asm_out_file, ", %d\n", p->size);
6002 }
6003 }
6004 }
6005 }
6006 }
6007
6008 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as
6009 the elfos.h version, but we also need to handle -muninit-const-in-rodata
6010 and the limitations of the SGI o32 assembler. */
6011
6012 void
mips_output_aligned_decl_common(FILE * stream,tree decl,const char * name,unsigned HOST_WIDE_INT size,unsigned int align)6013 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
6014 unsigned HOST_WIDE_INT size,
6015 unsigned int align)
6016 {
6017 /* If the target wants uninitialized const declarations in
6018 .rdata then don't put them in .comm. */
6019 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
6020 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
6021 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
6022 {
6023 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
6024 targetm.asm_out.globalize_label (stream, name);
6025
6026 readonly_data_section ();
6027 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6028 mips_declare_object (stream, name, "",
6029 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
6030 size);
6031 }
6032 else
6033 /* The SGI o32 assembler doesn't accept an alignment. */
6034 mips_declare_common_object (stream, name, "\n\t.comm\t",
6035 size, align, !TARGET_SGI_O32_AS);
6036 }
6037
6038 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
6039 NAME is the name of the object and ALIGN is the required alignment
6040 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
6041 alignment argument. */
6042
6043 void
mips_declare_common_object(FILE * stream,const char * name,const char * init_string,unsigned HOST_WIDE_INT size,unsigned int align,bool takes_alignment_p)6044 mips_declare_common_object (FILE *stream, const char *name,
6045 const char *init_string,
6046 unsigned HOST_WIDE_INT size,
6047 unsigned int align, bool takes_alignment_p)
6048 {
6049 if (!takes_alignment_p)
6050 {
6051 size += (align / BITS_PER_UNIT) - 1;
6052 size -= size % (align / BITS_PER_UNIT);
6053 mips_declare_object (stream, name, init_string,
6054 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6055 }
6056 else
6057 mips_declare_object (stream, name, init_string,
6058 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6059 size, align / BITS_PER_UNIT);
6060 }
6061
6062 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6063 macros, mark the symbol as written so that mips_file_end won't emit an
6064 .extern for it. STREAM is the output file, NAME is the name of the
6065 symbol, INIT_STRING is the string that should be written before the
6066 symbol and FINAL_STRING is the string that shoulbe written after it.
6067 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6068
6069 void
mips_declare_object(FILE * stream,const char * name,const char * init_string,const char * final_string,...)6070 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6071 const char *final_string, ...)
6072 {
6073 va_list ap;
6074
6075 fputs (init_string, stream);
6076 assemble_name (stream, name);
6077 va_start (ap, final_string);
6078 vfprintf (stream, final_string, ap);
6079 va_end (ap);
6080
6081 if (!TARGET_EXPLICIT_RELOCS)
6082 {
6083 tree name_tree = get_identifier (name);
6084 TREE_ASM_WRITTEN (name_tree) = 1;
6085 }
6086 }
6087
6088 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6089 extern int size_directive_output;
6090
6091 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6092 definitions except that it uses mips_declare_object() to emit the label. */
6093
6094 void
mips_declare_object_name(FILE * stream,const char * name,tree decl ATTRIBUTE_UNUSED)6095 mips_declare_object_name (FILE *stream, const char *name,
6096 tree decl ATTRIBUTE_UNUSED)
6097 {
6098 if (!TARGET_SGI_O32_AS)
6099 {
6100 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6101 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6102 #endif
6103
6104 size_directive_output = 0;
6105 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6106 {
6107 HOST_WIDE_INT size;
6108
6109 size_directive_output = 1;
6110 size = int_size_in_bytes (TREE_TYPE (decl));
6111 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6112 }
6113 }
6114
6115 mips_declare_object (stream, name, "", ":\n", 0);
6116 }
6117
6118 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6119
6120 void
mips_finish_declare_object(FILE * stream,tree decl,int top_level,int at_end)6121 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6122 {
6123 const char *name;
6124
6125 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6126 if (!TARGET_SGI_O32_AS
6127 && !flag_inhibit_size_directive
6128 && DECL_SIZE (decl) != 0
6129 && !at_end && top_level
6130 && DECL_INITIAL (decl) == error_mark_node
6131 && !size_directive_output)
6132 {
6133 HOST_WIDE_INT size;
6134
6135 size_directive_output = 1;
6136 size = int_size_in_bytes (TREE_TYPE (decl));
6137 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6138 }
6139 }
6140 #endif
6141
6142 /* Return true if X is a small data address that can be rewritten
6143 as a LO_SUM. */
6144
6145 static bool
mips_rewrite_small_data_p(rtx x)6146 mips_rewrite_small_data_p (rtx x)
6147 {
6148 enum mips_symbol_type symbol_type;
6149
6150 return (TARGET_EXPLICIT_RELOCS
6151 && mips_symbolic_constant_p (x, &symbol_type)
6152 && symbol_type == SYMBOL_SMALL_DATA);
6153 }
6154
6155
6156 /* A for_each_rtx callback for small_data_pattern. */
6157
6158 static int
small_data_pattern_1(rtx * loc,void * data ATTRIBUTE_UNUSED)6159 small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6160 {
6161 if (GET_CODE (*loc) == LO_SUM)
6162 return -1;
6163
6164 return mips_rewrite_small_data_p (*loc);
6165 }
6166
6167 /* Return true if OP refers to small data symbols directly, not through
6168 a LO_SUM. */
6169
6170 int
small_data_pattern(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)6171 small_data_pattern (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
6172 {
6173 return (GET_CODE (op) != SEQUENCE
6174 && for_each_rtx (&op, small_data_pattern_1, 0));
6175 }
6176
6177 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6178
6179 static int
mips_rewrite_small_data_1(rtx * loc,void * data ATTRIBUTE_UNUSED)6180 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6181 {
6182 if (mips_rewrite_small_data_p (*loc))
6183 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6184
6185 if (GET_CODE (*loc) == LO_SUM)
6186 return -1;
6187
6188 return 0;
6189 }
6190
6191 /* If possible, rewrite OP so that it refers to small data using
6192 explicit relocations. */
6193
6194 rtx
mips_rewrite_small_data(rtx op)6195 mips_rewrite_small_data (rtx op)
6196 {
6197 op = copy_insn (op);
6198 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6199 return op;
6200 }
6201
6202 /* Return true if the current function has an insn that implicitly
6203 refers to $gp. */
6204
6205 static bool
mips_function_has_gp_insn(void)6206 mips_function_has_gp_insn (void)
6207 {
6208 /* Don't bother rechecking if we found one last time. */
6209 if (!cfun->machine->has_gp_insn_p)
6210 {
6211 rtx insn;
6212
6213 push_topmost_sequence ();
6214 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6215 if (INSN_P (insn)
6216 && GET_CODE (PATTERN (insn)) != USE
6217 && GET_CODE (PATTERN (insn)) != CLOBBER
6218 && (get_attr_got (insn) != GOT_UNSET
6219 || small_data_pattern (PATTERN (insn), VOIDmode)))
6220 break;
6221 pop_topmost_sequence ();
6222
6223 cfun->machine->has_gp_insn_p = (insn != 0);
6224 }
6225 return cfun->machine->has_gp_insn_p;
6226 }
6227
6228
6229 /* Return the register that should be used as the global pointer
6230 within this function. Return 0 if the function doesn't need
6231 a global pointer. */
6232
6233 static unsigned int
mips_global_pointer(void)6234 mips_global_pointer (void)
6235 {
6236 unsigned int regno;
6237
6238 /* $gp is always available in non-abicalls code. */
6239 if (!TARGET_ABICALLS)
6240 return GLOBAL_POINTER_REGNUM;
6241
6242 /* We must always provide $gp when it is used implicitly. */
6243 if (!TARGET_EXPLICIT_RELOCS)
6244 return GLOBAL_POINTER_REGNUM;
6245
6246 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6247 a valid gp. */
6248 if (current_function_profile)
6249 return GLOBAL_POINTER_REGNUM;
6250
6251 /* If the function has a nonlocal goto, $gp must hold the correct
6252 global pointer for the target function. */
6253 if (current_function_has_nonlocal_goto)
6254 return GLOBAL_POINTER_REGNUM;
6255
6256 /* If the gp is never referenced, there's no need to initialize it.
6257 Note that reload can sometimes introduce constant pool references
6258 into a function that otherwise didn't need them. For example,
6259 suppose we have an instruction like:
6260
6261 (set (reg:DF R1) (float:DF (reg:SI R2)))
6262
6263 If R2 turns out to be constant such as 1, the instruction may have a
6264 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6265 using this constant if R2 doesn't get allocated to a register.
6266
6267 In cases like these, reload will have added the constant to the pool
6268 but no instruction will yet refer to it. */
6269 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6270 && !current_function_uses_const_pool
6271 && !mips_function_has_gp_insn ())
6272 return 0;
6273
6274 /* We need a global pointer, but perhaps we can use a call-clobbered
6275 register instead of $gp. */
6276 if (TARGET_NEWABI && current_function_is_leaf)
6277 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6278 if (!regs_ever_live[regno]
6279 && call_used_regs[regno]
6280 && !fixed_regs[regno]
6281 && regno != PIC_FUNCTION_ADDR_REGNUM)
6282 return regno;
6283
6284 return GLOBAL_POINTER_REGNUM;
6285 }
6286
6287
6288 /* Return true if the current function must save REGNO. */
6289
6290 static bool
mips_save_reg_p(unsigned int regno)6291 mips_save_reg_p (unsigned int regno)
6292 {
6293 /* We only need to save $gp for NewABI PIC. */
6294 if (regno == GLOBAL_POINTER_REGNUM)
6295 return (TARGET_ABICALLS && TARGET_NEWABI
6296 && cfun->machine->global_pointer == regno);
6297
6298 /* Check call-saved registers. */
6299 if (regs_ever_live[regno] && !call_used_regs[regno])
6300 return true;
6301
6302 /* We need to save the old frame pointer before setting up a new one. */
6303 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6304 return true;
6305
6306 /* We need to save the incoming return address if it is ever clobbered
6307 within the function. */
6308 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6309 return true;
6310
6311 if (TARGET_MIPS16)
6312 {
6313 tree return_type;
6314
6315 return_type = DECL_RESULT (current_function_decl);
6316
6317 /* $18 is a special case in mips16 code. It may be used to call
6318 a function which returns a floating point value, but it is
6319 marked in call_used_regs. */
6320 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6321 return true;
6322
6323 /* $31 is also a special case. It will be used to copy a return
6324 value into the floating point registers if the return value is
6325 floating point. */
6326 if (regno == GP_REG_FIRST + 31
6327 && mips16_hard_float
6328 && !aggregate_value_p (return_type, current_function_decl)
6329 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6330 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6331 return true;
6332 }
6333
6334 return false;
6335 }
6336
6337
6338 /* Return the bytes needed to compute the frame pointer from the current
6339 stack pointer. SIZE is the size (in bytes) of the local variables.
6340
6341 Mips stack frames look like:
6342
6343 Before call After call
6344 +-----------------------+ +-----------------------+
6345 high | | | |
6346 mem. | | | |
6347 | caller's temps. | | caller's temps. |
6348 | | | |
6349 +-----------------------+ +-----------------------+
6350 | | | |
6351 | arguments on stack. | | arguments on stack. |
6352 | | | |
6353 +-----------------------+ +-----------------------+
6354 | 4 words to save | | 4 words to save |
6355 | arguments passed | | arguments passed |
6356 | in registers, even | | in registers, even |
6357 SP->| if not passed. | VFP->| if not passed. |
6358 +-----------------------+ +-----------------------+
6359 | |
6360 | fp register save |
6361 | |
6362 +-----------------------+
6363 | |
6364 | gp register save |
6365 | |
6366 +-----------------------+
6367 | |
6368 | local variables |
6369 | |
6370 +-----------------------+
6371 | |
6372 | alloca allocations |
6373 | |
6374 +-----------------------+
6375 | |
6376 | GP save for V.4 abi |
6377 | |
6378 +-----------------------+
6379 | |
6380 | arguments on stack |
6381 | |
6382 +-----------------------+
6383 | 4 words to save |
6384 | arguments passed |
6385 | in registers, even |
6386 low SP->| if not passed. |
6387 memory +-----------------------+
6388
6389 */
6390
6391 HOST_WIDE_INT
compute_frame_size(HOST_WIDE_INT size)6392 compute_frame_size (HOST_WIDE_INT size)
6393 {
6394 unsigned int regno;
6395 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6396 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6397 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6398 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6399 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6400 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6401 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6402 unsigned int mask; /* mask of saved gp registers */
6403 unsigned int fmask; /* mask of saved fp registers */
6404
6405 cfun->machine->global_pointer = mips_global_pointer ();
6406
6407 gp_reg_size = 0;
6408 fp_reg_size = 0;
6409 mask = 0;
6410 fmask = 0;
6411 var_size = MIPS_STACK_ALIGN (size);
6412 args_size = current_function_outgoing_args_size;
6413 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6414
6415 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6416 functions. If the function has local variables, we're committed
6417 to allocating it anyway. Otherwise reclaim it here. */
6418 if (var_size == 0 && current_function_is_leaf)
6419 cprestore_size = args_size = 0;
6420
6421 /* The MIPS 3.0 linker does not like functions that dynamically
6422 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6423 looks like we are trying to create a second frame pointer to the
6424 function, so allocate some stack space to make it happy. */
6425
6426 if (args_size == 0 && current_function_calls_alloca)
6427 args_size = 4 * UNITS_PER_WORD;
6428
6429 total_size = var_size + args_size + cprestore_size;
6430
6431 /* Calculate space needed for gp registers. */
6432 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6433 if (mips_save_reg_p (regno))
6434 {
6435 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6436 mask |= 1 << (regno - GP_REG_FIRST);
6437 }
6438
6439 /* We need to restore these for the handler. */
6440 if (current_function_calls_eh_return)
6441 {
6442 unsigned int i;
6443 for (i = 0; ; ++i)
6444 {
6445 regno = EH_RETURN_DATA_REGNO (i);
6446 if (regno == INVALID_REGNUM)
6447 break;
6448 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6449 mask |= 1 << (regno - GP_REG_FIRST);
6450 }
6451 }
6452
6453 /* This loop must iterate over the same space as its companion in
6454 save_restore_insns. */
6455 for (regno = (FP_REG_LAST - FP_INC + 1);
6456 regno >= FP_REG_FIRST;
6457 regno -= FP_INC)
6458 {
6459 if (mips_save_reg_p (regno))
6460 {
6461 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6462 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6463 }
6464 }
6465
6466 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6467 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6468
6469 /* Add in space reserved on the stack by the callee for storing arguments
6470 passed in registers. */
6471 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
6472 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6473
6474 /* Save other computed information. */
6475 cfun->machine->frame.total_size = total_size;
6476 cfun->machine->frame.var_size = var_size;
6477 cfun->machine->frame.args_size = args_size;
6478 cfun->machine->frame.cprestore_size = cprestore_size;
6479 cfun->machine->frame.gp_reg_size = gp_reg_size;
6480 cfun->machine->frame.fp_reg_size = fp_reg_size;
6481 cfun->machine->frame.mask = mask;
6482 cfun->machine->frame.fmask = fmask;
6483 cfun->machine->frame.initialized = reload_completed;
6484 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6485 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6486
6487 if (mask)
6488 {
6489 HOST_WIDE_INT offset;
6490
6491 offset = (args_size + cprestore_size + var_size
6492 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6493 cfun->machine->frame.gp_sp_offset = offset;
6494 cfun->machine->frame.gp_save_offset = offset - total_size;
6495 }
6496 else
6497 {
6498 cfun->machine->frame.gp_sp_offset = 0;
6499 cfun->machine->frame.gp_save_offset = 0;
6500 }
6501
6502 if (fmask)
6503 {
6504 HOST_WIDE_INT offset;
6505
6506 offset = (args_size + cprestore_size + var_size
6507 + gp_reg_rounded + fp_reg_size
6508 - FP_INC * UNITS_PER_FPREG);
6509 cfun->machine->frame.fp_sp_offset = offset;
6510 cfun->machine->frame.fp_save_offset = offset - total_size;
6511 }
6512 else
6513 {
6514 cfun->machine->frame.fp_sp_offset = 0;
6515 cfun->machine->frame.fp_save_offset = 0;
6516 }
6517
6518 /* Ok, we're done. */
6519 return total_size;
6520 }
6521
6522 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6523 pointer or argument pointer. TO is either the stack pointer or
6524 hard frame pointer. */
6525
6526 HOST_WIDE_INT
mips_initial_elimination_offset(int from,int to)6527 mips_initial_elimination_offset (int from, int to)
6528 {
6529 HOST_WIDE_INT offset;
6530
6531 compute_frame_size (get_frame_size ());
6532
6533 /* Set OFFSET to the offset from the stack pointer. */
6534 switch (from)
6535 {
6536 case FRAME_POINTER_REGNUM:
6537 offset = 0;
6538 break;
6539
6540 case ARG_POINTER_REGNUM:
6541 offset = cfun->machine->frame.total_size;
6542 if (mips_abi == ABI_N32 || mips_abi == ABI_64)
6543 offset -= current_function_pretend_args_size;
6544 break;
6545
6546 default:
6547 abort ();
6548 }
6549
6550 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6551 offset -= cfun->machine->frame.args_size;
6552
6553 return offset;
6554 }
6555
6556 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6557 back to a previous frame. */
6558 rtx
mips_return_addr(int count,rtx frame ATTRIBUTE_UNUSED)6559 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6560 {
6561 if (count != 0)
6562 return const0_rtx;
6563
6564 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6565 }
6566
6567 /* Use FN to save or restore register REGNO. MODE is the register's
6568 mode and OFFSET is the offset of its save slot from the current
6569 stack pointer. */
6570
6571 static void
mips_save_restore_reg(enum machine_mode mode,int regno,HOST_WIDE_INT offset,mips_save_restore_fn fn)6572 mips_save_restore_reg (enum machine_mode mode, int regno,
6573 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6574 {
6575 rtx mem;
6576
6577 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6578 if (!current_function_calls_eh_return)
6579 RTX_UNCHANGING_P (mem) = 1;
6580
6581 fn (gen_rtx_REG (mode, regno), mem);
6582 }
6583
6584
6585 /* Call FN for each register that is saved by the current function.
6586 SP_OFFSET is the offset of the current stack pointer from the start
6587 of the frame. */
6588
6589 static void
mips_for_each_saved_reg(HOST_WIDE_INT sp_offset,mips_save_restore_fn fn)6590 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6591 {
6592 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6593
6594 enum machine_mode fpr_mode;
6595 HOST_WIDE_INT offset;
6596 int regno;
6597
6598 /* Save registers starting from high to low. The debuggers prefer at least
6599 the return register be stored at func+4, and also it allows us not to
6600 need a nop in the epilog if at least one register is reloaded in
6601 addition to return address. */
6602 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6603 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6604 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6605 {
6606 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6607 offset -= GET_MODE_SIZE (gpr_mode);
6608 }
6609
6610 /* This loop must iterate over the same space as its companion in
6611 compute_frame_size. */
6612 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6613 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6614 for (regno = (FP_REG_LAST - FP_INC + 1);
6615 regno >= FP_REG_FIRST;
6616 regno -= FP_INC)
6617 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6618 {
6619 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6620 offset -= GET_MODE_SIZE (fpr_mode);
6621 }
6622 #undef BITSET_P
6623 }
6624
6625 /* If we're generating n32 or n64 abicalls, and the current function
6626 does not use $28 as its global pointer, emit a cplocal directive.
6627 Use pic_offset_table_rtx as the argument to the directive. */
6628
6629 static void
mips_output_cplocal(void)6630 mips_output_cplocal (void)
6631 {
6632 if (!TARGET_EXPLICIT_RELOCS
6633 && cfun->machine->global_pointer > 0
6634 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6635 output_asm_insn (".cplocal %+", 0);
6636 }
6637
6638 /* If we're generating n32 or n64 abicalls, emit instructions
6639 to set up the global pointer. */
6640
6641 static void
mips_emit_loadgp(void)6642 mips_emit_loadgp (void)
6643 {
6644 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6645 {
6646 rtx addr, offset, incoming_address;
6647
6648 addr = XEXP (DECL_RTL (current_function_decl), 0);
6649 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6650 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6651 emit_insn (gen_loadgp (offset, incoming_address));
6652 if (!TARGET_EXPLICIT_RELOCS)
6653 emit_insn (gen_loadgp_blockage ());
6654 }
6655 }
6656
6657 /* Set up the stack and frame (if desired) for the function. */
6658
6659 static void
mips_output_function_prologue(FILE * file,HOST_WIDE_INT size ATTRIBUTE_UNUSED)6660 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6661 {
6662 const char *fnname;
6663 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6664
6665 /* ??? When is this really needed? At least the GNU assembler does not
6666 need the source filename more than once in the file, beyond what is
6667 emitted by the debug information. */
6668 if (!TARGET_GAS)
6669 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6670
6671 #ifdef SDB_DEBUGGING_INFO
6672 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6673 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl), 0);
6674 #endif
6675
6676 /* In mips16 mode, we may need to generate a 32 bit to handle
6677 floating point arguments. The linker will arrange for any 32 bit
6678 functions to call this stub, which will then jump to the 16 bit
6679 function proper. */
6680 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6681 && current_function_args_info.fp_code != 0)
6682 build_mips16_function_stub (file);
6683
6684 if (!FUNCTION_NAME_ALREADY_DECLARED)
6685 {
6686 /* Get the function name the same way that toplev.c does before calling
6687 assemble_start_function. This is needed so that the name used here
6688 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6689 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6690
6691 if (!flag_inhibit_size_directive)
6692 {
6693 fputs ("\t.ent\t", file);
6694 assemble_name (file, fnname);
6695 fputs ("\n", file);
6696 }
6697
6698 assemble_name (file, fnname);
6699 fputs (":\n", file);
6700 }
6701
6702 if (!flag_inhibit_size_directive)
6703 {
6704 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6705 fprintf (file,
6706 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6707 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6708 ", args= " HOST_WIDE_INT_PRINT_DEC
6709 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6710 (reg_names[(frame_pointer_needed)
6711 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6712 ((frame_pointer_needed && TARGET_MIPS16)
6713 ? tsize - cfun->machine->frame.args_size
6714 : tsize),
6715 reg_names[GP_REG_FIRST + 31],
6716 cfun->machine->frame.var_size,
6717 cfun->machine->frame.num_gp,
6718 cfun->machine->frame.num_fp,
6719 cfun->machine->frame.args_size,
6720 cfun->machine->frame.cprestore_size);
6721
6722 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6723 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6724 cfun->machine->frame.mask,
6725 cfun->machine->frame.gp_save_offset);
6726 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6727 cfun->machine->frame.fmask,
6728 cfun->machine->frame.fp_save_offset);
6729
6730 /* Require:
6731 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6732 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6733 }
6734
6735 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6736 {
6737 /* Handle the initialization of $gp for SVR4 PIC. */
6738 if (!cfun->machine->all_noreorder_p)
6739 output_asm_insn ("%(.cpload\t%^%)", 0);
6740 else
6741 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6742 }
6743 else if (cfun->machine->all_noreorder_p)
6744 output_asm_insn ("%(%<", 0);
6745
6746 /* Tell the assembler which register we're using as the global
6747 pointer. This is needed for thunks, since they can use either
6748 explicit relocs or assembler macros. */
6749 mips_output_cplocal ();
6750 }
6751
6752 /* Make the last instruction frame related and note that it performs
6753 the operation described by FRAME_PATTERN. */
6754
6755 static void
mips_set_frame_expr(rtx frame_pattern)6756 mips_set_frame_expr (rtx frame_pattern)
6757 {
6758 rtx insn;
6759
6760 insn = get_last_insn ();
6761 RTX_FRAME_RELATED_P (insn) = 1;
6762 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6763 frame_pattern,
6764 REG_NOTES (insn));
6765 }
6766
6767
6768 /* Return a frame-related rtx that stores REG at MEM.
6769 REG must be a single register. */
6770
6771 static rtx
mips_frame_set(rtx mem,rtx reg)6772 mips_frame_set (rtx mem, rtx reg)
6773 {
6774 rtx set = gen_rtx_SET (VOIDmode, mem, reg);
6775 RTX_FRAME_RELATED_P (set) = 1;
6776 return set;
6777 }
6778
6779
6780 /* Save register REG to MEM. Make the instruction frame-related. */
6781
6782 static void
mips_save_reg(rtx reg,rtx mem)6783 mips_save_reg (rtx reg, rtx mem)
6784 {
6785 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6786 {
6787 rtx x1, x2;
6788
6789 if (mips_split_64bit_move_p (mem, reg))
6790 mips_split_64bit_move (mem, reg);
6791 else
6792 emit_move_insn (mem, reg);
6793
6794 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6795 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6796 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6797 }
6798 else
6799 {
6800 if (TARGET_MIPS16
6801 && REGNO (reg) != GP_REG_FIRST + 31
6802 && !M16_REG_P (REGNO (reg)))
6803 {
6804 /* Save a non-mips16 register by moving it through a temporary.
6805 We don't need to do this for $31 since there's a special
6806 instruction for it. */
6807 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6808 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6809 }
6810 else
6811 emit_move_insn (mem, reg);
6812
6813 mips_set_frame_expr (mips_frame_set (mem, reg));
6814 }
6815 }
6816
6817
6818 /* Expand the prologue into a bunch of separate insns. */
6819
6820 void
mips_expand_prologue(void)6821 mips_expand_prologue (void)
6822 {
6823 HOST_WIDE_INT size;
6824
6825 if (cfun->machine->global_pointer > 0)
6826 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6827
6828 size = compute_frame_size (get_frame_size ());
6829
6830 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6831 bytes beforehand; this is enough to cover the register save area
6832 without going out of range. */
6833 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6834 {
6835 HOST_WIDE_INT step1;
6836
6837 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6838 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6839 stack_pointer_rtx,
6840 GEN_INT (-step1)))) = 1;
6841 size -= step1;
6842 mips_for_each_saved_reg (size, mips_save_reg);
6843 }
6844
6845 /* Allocate the rest of the frame. */
6846 if (size > 0)
6847 {
6848 if (SMALL_OPERAND (-size))
6849 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6850 stack_pointer_rtx,
6851 GEN_INT (-size)))) = 1;
6852 else
6853 {
6854 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6855 if (TARGET_MIPS16)
6856 {
6857 /* There are no instructions to add or subtract registers
6858 from the stack pointer, so use the frame pointer as a
6859 temporary. We should always be using a frame pointer
6860 in this case anyway. */
6861 if (!frame_pointer_needed)
6862 abort ();
6863
6864 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6865 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6866 hard_frame_pointer_rtx,
6867 MIPS_PROLOGUE_TEMP (Pmode)));
6868 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6869 }
6870 else
6871 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6872 stack_pointer_rtx,
6873 MIPS_PROLOGUE_TEMP (Pmode)));
6874
6875 /* Describe the combined effect of the previous instructions. */
6876 mips_set_frame_expr
6877 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6878 plus_constant (stack_pointer_rtx, -size)));
6879 }
6880 }
6881
6882 /* Set up the frame pointer, if we're using one. In mips16 code,
6883 we point the frame pointer ahead of the outgoing argument area.
6884 This should allow more variables & incoming arguments to be
6885 accessed with unextended instructions. */
6886 if (frame_pointer_needed)
6887 {
6888 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6889 {
6890 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6891 RTX_FRAME_RELATED_P
6892 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6893 stack_pointer_rtx,
6894 offset))) = 1;
6895 }
6896 else
6897 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6898 stack_pointer_rtx)) = 1;
6899 }
6900
6901 /* If generating o32/o64 abicalls, save $gp on the stack. */
6902 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6903 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6904
6905 mips_emit_loadgp ();
6906
6907 /* If we are profiling, make sure no instructions are scheduled before
6908 the call to mcount. */
6909
6910 if (current_function_profile)
6911 emit_insn (gen_blockage ());
6912 }
6913
6914 /* Do any necessary cleanup after a function to restore stack, frame,
6915 and regs. */
6916
6917 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6918 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6919
6920 static void
mips_output_function_epilogue(FILE * file ATTRIBUTE_UNUSED,HOST_WIDE_INT size ATTRIBUTE_UNUSED)6921 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6922 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6923 {
6924 rtx string;
6925
6926 /* Reinstate the normal $gp. */
6927 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6928 mips_output_cplocal ();
6929
6930 if (cfun->machine->all_noreorder_p)
6931 {
6932 /* Avoid using %>%) since it adds excess whitespace. */
6933 output_asm_insn (".set\tmacro", 0);
6934 output_asm_insn (".set\treorder", 0);
6935 set_noreorder = set_nomacro = 0;
6936 }
6937
6938 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6939 {
6940 const char *fnname;
6941
6942 /* Get the function name the same way that toplev.c does before calling
6943 assemble_start_function. This is needed so that the name used here
6944 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6945 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6946 fputs ("\t.end\t", file);
6947 assemble_name (file, fnname);
6948 fputs ("\n", file);
6949 }
6950
6951 while (string_constants != NULL)
6952 {
6953 struct string_constant *next;
6954
6955 next = string_constants->next;
6956 free (string_constants);
6957 string_constants = next;
6958 }
6959
6960 /* If any following function uses the same strings as this one, force
6961 them to refer those strings indirectly. Nearby functions could
6962 refer them using pc-relative addressing, but it isn't safe in
6963 general. For instance, some functions may be placed in sections
6964 other than .text, and we don't know whether they be close enough
6965 to this one. In large files, even other .text functions can be
6966 too far away. */
6967 for (string = mips16_strings; string != 0; string = XEXP (string, 1))
6968 SYMBOL_REF_FLAG (XEXP (string, 0)) = 0;
6969 free_EXPR_LIST_list (&mips16_strings);
6970 }
6971
6972 /* Emit instructions to restore register REG from slot MEM. */
6973
6974 static void
mips_restore_reg(rtx reg,rtx mem)6975 mips_restore_reg (rtx reg, rtx mem)
6976 {
6977 /* There's no mips16 instruction to load $31 directly. Load into
6978 $7 instead and adjust the return insn appropriately. */
6979 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6980 reg = gen_rtx_REG (GET_MODE (reg), 7);
6981
6982 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6983 {
6984 /* Can't restore directly; move through a temporary. */
6985 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6986 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6987 }
6988 else
6989 emit_move_insn (reg, mem);
6990 }
6991
6992
6993 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6994 if this epilogue precedes a sibling call, false if it is for a normal
6995 "epilogue" pattern. */
6996
6997 void
mips_expand_epilogue(int sibcall_p)6998 mips_expand_epilogue (int sibcall_p)
6999 {
7000 HOST_WIDE_INT step1, step2;
7001 rtx base, target;
7002
7003 if (!sibcall_p && mips_can_use_return_insn ())
7004 {
7005 emit_jump_insn (gen_return ());
7006 return;
7007 }
7008
7009 /* Split the frame into two. STEP1 is the amount of stack we should
7010 deallocate before restoring the registers. STEP2 is the amount we
7011 should deallocate afterwards.
7012
7013 Start off by assuming that no registers need to be restored. */
7014 step1 = cfun->machine->frame.total_size;
7015 step2 = 0;
7016
7017 /* Work out which register holds the frame address. Account for the
7018 frame pointer offset used by mips16 code. */
7019 if (!frame_pointer_needed)
7020 base = stack_pointer_rtx;
7021 else
7022 {
7023 base = hard_frame_pointer_rtx;
7024 if (TARGET_MIPS16)
7025 step1 -= cfun->machine->frame.args_size;
7026 }
7027
7028 /* If we need to restore registers, deallocate as much stack as
7029 possible in the second step without going out of range. */
7030 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7031 {
7032 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7033 step1 -= step2;
7034 }
7035
7036 /* Set TARGET to BASE + STEP1. */
7037 target = base;
7038 if (step1 > 0)
7039 {
7040 rtx adjust;
7041
7042 /* Get an rtx for STEP1 that we can add to BASE. */
7043 adjust = GEN_INT (step1);
7044 if (!SMALL_OPERAND (step1))
7045 {
7046 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7047 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7048 }
7049
7050 /* Normal mode code can copy the result straight into $sp. */
7051 if (!TARGET_MIPS16)
7052 target = stack_pointer_rtx;
7053
7054 emit_insn (gen_add3_insn (target, base, adjust));
7055 }
7056
7057 /* Copy TARGET into the stack pointer. */
7058 if (target != stack_pointer_rtx)
7059 emit_move_insn (stack_pointer_rtx, target);
7060
7061 /* If we're using addressing macros for n32/n64 abicalls, $gp is
7062 implicitly used by all SYMBOL_REFs. We must emit a blockage
7063 insn before restoring it. */
7064 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
7065 emit_insn (gen_blockage ());
7066
7067 /* Restore the registers. */
7068 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7069 mips_restore_reg);
7070
7071 /* Deallocate the final bit of the frame. */
7072 if (step2 > 0)
7073 emit_insn (gen_add3_insn (stack_pointer_rtx,
7074 stack_pointer_rtx,
7075 GEN_INT (step2)));
7076
7077 /* Add in the __builtin_eh_return stack adjustment. We need to
7078 use a temporary in mips16 code. */
7079 if (current_function_calls_eh_return)
7080 {
7081 if (TARGET_MIPS16)
7082 {
7083 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7084 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7085 MIPS_EPILOGUE_TEMP (Pmode),
7086 EH_RETURN_STACKADJ_RTX));
7087 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7088 }
7089 else
7090 emit_insn (gen_add3_insn (stack_pointer_rtx,
7091 stack_pointer_rtx,
7092 EH_RETURN_STACKADJ_RTX));
7093 }
7094
7095 if (!sibcall_p)
7096 {
7097 /* The mips16 loads the return address into $7, not $31. */
7098 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7099 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7100 GP_REG_FIRST + 7)));
7101 else
7102 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7103 GP_REG_FIRST + 31)));
7104 }
7105 }
7106
7107 /* Return nonzero if this function is known to have a null epilogue.
7108 This allows the optimizer to omit jumps to jumps if no stack
7109 was created. */
7110
7111 int
mips_can_use_return_insn(void)7112 mips_can_use_return_insn (void)
7113 {
7114 tree return_type;
7115
7116 if (! reload_completed)
7117 return 0;
7118
7119 if (regs_ever_live[31] || current_function_profile)
7120 return 0;
7121
7122 return_type = DECL_RESULT (current_function_decl);
7123
7124 /* In mips16 mode, a function which returns a floating point value
7125 needs to arrange to copy the return value into the floating point
7126 registers. */
7127 if (TARGET_MIPS16
7128 && mips16_hard_float
7129 && ! aggregate_value_p (return_type, current_function_decl)
7130 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7131 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7132 return 0;
7133
7134 if (cfun->machine->frame.initialized)
7135 return cfun->machine->frame.total_size == 0;
7136
7137 return compute_frame_size (get_frame_size ()) == 0;
7138 }
7139
7140 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7141 in order to avoid duplicating too much logic from elsewhere. */
7142
7143 static void
mips_output_mi_thunk(FILE * file,tree thunk_fndecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset,tree function)7144 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7145 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7146 tree function)
7147 {
7148 rtx this, temp1, temp2, insn, fnaddr;
7149
7150 /* Pretend to be a post-reload pass while generating rtl. */
7151 no_new_pseudos = 1;
7152 reload_completed = 1;
7153
7154 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7155 for TARGET_NEWABI since the latter is a call-saved register. */
7156 if (TARGET_ABICALLS)
7157 cfun->machine->global_pointer
7158 = REGNO (pic_offset_table_rtx)
7159 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7160
7161 /* Set up the global pointer for n32 or n64 abicalls. */
7162 mips_emit_loadgp ();
7163
7164 /* We need two temporary registers in some cases. */
7165 temp1 = gen_rtx_REG (Pmode, 2);
7166 temp2 = gen_rtx_REG (Pmode, 3);
7167
7168 /* Find out which register contains the "this" pointer. */
7169 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7170 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7171 else
7172 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7173
7174 /* Add DELTA to THIS. */
7175 if (delta != 0)
7176 {
7177 rtx offset = GEN_INT (delta);
7178 if (!SMALL_OPERAND (delta))
7179 {
7180 emit_move_insn (temp1, offset);
7181 offset = temp1;
7182 }
7183 emit_insn (gen_add3_insn (this, this, offset));
7184 }
7185
7186 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7187 if (vcall_offset != 0)
7188 {
7189 rtx addr;
7190
7191 /* Set TEMP1 to *THIS. */
7192 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7193
7194 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7195 if (SMALL_OPERAND (vcall_offset))
7196 addr = gen_rtx_PLUS (Pmode, temp1, GEN_INT (vcall_offset));
7197 else if (TARGET_MIPS16)
7198 {
7199 /* Load the full offset into a register so that we can use
7200 an unextended instruction for the load itself. */
7201 emit_move_insn (temp2, GEN_INT (vcall_offset));
7202 emit_insn (gen_add3_insn (temp1, temp1, temp2));
7203 addr = temp1;
7204 }
7205 else
7206 {
7207 /* Load the high part of the offset into a register and
7208 leave the low part for the address. */
7209 emit_move_insn (temp2, GEN_INT (CONST_HIGH_PART (vcall_offset)));
7210 emit_insn (gen_add3_insn (temp1, temp1, temp2));
7211 addr = gen_rtx_PLUS (Pmode, temp1,
7212 GEN_INT (CONST_LOW_PART (vcall_offset)));
7213 }
7214
7215 /* Load the offset and add it to THIS. */
7216 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7217 emit_insn (gen_add3_insn (this, this, temp1));
7218 }
7219
7220 /* Jump to the target function. Use a sibcall if direct jumps are
7221 allowed, otherwise load the address into a register first. */
7222 fnaddr = XEXP (DECL_RTL (function), 0);
7223 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7224 {
7225 /* This is messy. gas treats "la $25,foo" as part of a call
7226 sequence and may allow a global "foo" to be lazily bound.
7227 The general move patterns therefore reject this combination.
7228
7229 In this context, lazy binding would actually be OK for o32 and o64,
7230 but it's still wrong for n32 and n64; see mips_load_call_address.
7231 We must therefore load the address via a temporary register if
7232 mips_dangerous_for_la25_p.
7233
7234 If we jump to the temporary register rather than $25, the assembler
7235 can use the move insn to fill the jump's delay slot. */
7236 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7237 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7238 mips_load_call_address (temp1, fnaddr, true);
7239
7240 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7241 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7242 emit_jump_insn (gen_indirect_jump (temp1));
7243 }
7244 else
7245 {
7246 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7247 SIBLING_CALL_P (insn) = 1;
7248 }
7249
7250 /* Run just enough of rest_of_compilation. This sequence was
7251 "borrowed" from alpha.c. */
7252 insn = get_insns ();
7253 insn_locators_initialize ();
7254 split_all_insns_noflow ();
7255 shorten_branches (insn);
7256 final_start_function (insn, file, 1);
7257 final (insn, file, 1, 0);
7258 final_end_function ();
7259
7260 /* Clean up the vars set above. Note that final_end_function resets
7261 the global pointer for us. */
7262 reload_completed = 0;
7263 no_new_pseudos = 0;
7264 }
7265
7266 /* Returns nonzero if X contains a SYMBOL_REF. */
7267
7268 static int
symbolic_expression_p(rtx x)7269 symbolic_expression_p (rtx x)
7270 {
7271 if (GET_CODE (x) == SYMBOL_REF)
7272 return 1;
7273
7274 if (GET_CODE (x) == CONST)
7275 return symbolic_expression_p (XEXP (x, 0));
7276
7277 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7278 return symbolic_expression_p (XEXP (x, 0));
7279
7280 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7281 || GET_RTX_CLASS (GET_CODE (x)) == '2')
7282 return (symbolic_expression_p (XEXP (x, 0))
7283 || symbolic_expression_p (XEXP (x, 1)));
7284
7285 return 0;
7286 }
7287
7288 /* Choose the section to use for the constant rtx expression X that has
7289 mode MODE. */
7290
7291 static void
mips_select_rtx_section(enum machine_mode mode,rtx x,unsigned HOST_WIDE_INT align)7292 mips_select_rtx_section (enum machine_mode mode, rtx x,
7293 unsigned HOST_WIDE_INT align)
7294 {
7295 if (TARGET_MIPS16)
7296 {
7297 /* In mips16 mode, the constant table always goes in the same section
7298 as the function, so that constants can be loaded using PC relative
7299 addressing. */
7300 function_section (current_function_decl);
7301 }
7302 else if (TARGET_EMBEDDED_DATA)
7303 {
7304 /* For embedded applications, always put constants in read-only data,
7305 in order to reduce RAM usage. */
7306 mergeable_constant_section (mode, align, 0);
7307 }
7308 else
7309 {
7310 /* For hosted applications, always put constants in small data if
7311 possible, as this gives the best performance. */
7312 /* ??? Consider using mergeable small data sections. */
7313
7314 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7315 && mips_section_threshold > 0)
7316 named_section (0, ".sdata", 0);
7317 else if (flag_pic && symbolic_expression_p (x))
7318 {
7319 if (targetm.have_named_sections)
7320 named_section (0, ".data.rel.ro", 3);
7321 else
7322 data_section ();
7323 }
7324 else
7325 mergeable_constant_section (mode, align, 0);
7326 }
7327 }
7328
7329 /* Choose the section to use for DECL. RELOC is true if its value contains
7330 any relocatable expression. */
7331
7332 static void
mips_select_section(tree decl,int reloc,unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)7333 mips_select_section (tree decl, int reloc,
7334 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
7335 {
7336 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7337 && TREE_CODE (decl) == STRING_CST
7338 && !flag_writable_strings)
7339 /* For embedded position independent code, put constant strings in the
7340 text section, because the data section is limited to 64K in size.
7341 For mips16 code, put strings in the text section so that a PC
7342 relative load instruction can be used to get their address. */
7343 text_section ();
7344 else if (targetm.have_named_sections)
7345 default_elf_select_section (decl, reloc, align);
7346 else
7347 /* The native irix o32 assembler doesn't support named sections. */
7348 default_select_section (decl, reloc, align);
7349 }
7350
7351
7352 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7353 access DECL using %gp_rel(...)($gp). */
7354
7355 static bool
mips_in_small_data_p(tree decl)7356 mips_in_small_data_p (tree decl)
7357 {
7358 HOST_WIDE_INT size;
7359
7360 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7361 return false;
7362
7363 /* We don't yet generate small-data references for -mabicalls. See related
7364 -G handling in override_options. */
7365 if (TARGET_ABICALLS)
7366 return false;
7367
7368 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7369 {
7370 const char *name;
7371
7372 /* Reject anything that isn't in a known small-data section. */
7373 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7374 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7375 return false;
7376
7377 /* If a symbol is defined externally, the assembler will use the
7378 usual -G rules when deciding how to implement macros. */
7379 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7380 return true;
7381 }
7382 else if (TARGET_EMBEDDED_DATA)
7383 {
7384 /* Don't put constants into the small data section: we want them
7385 to be in ROM rather than RAM. */
7386 if (TREE_CODE (decl) != VAR_DECL)
7387 return false;
7388
7389 if (TREE_READONLY (decl)
7390 && !TREE_SIDE_EFFECTS (decl)
7391 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7392 return false;
7393 }
7394
7395 size = int_size_in_bytes (TREE_TYPE (decl));
7396 return (size > 0 && size <= mips_section_threshold);
7397 }
7398
7399
7400 /* When generating embedded PIC code, SYMBOL_REF_FLAG is set for
7401 symbols which are not in the .text section.
7402
7403 When generating mips16 code, SYMBOL_REF_FLAG is set for string
7404 constants which are put in the .text section. We also record the
7405 total length of all such strings; this total is used to decide
7406 whether we need to split the constant table, and need not be
7407 precisely correct. */
7408
7409 static void
mips_encode_section_info(tree decl,rtx rtl,int first)7410 mips_encode_section_info (tree decl, rtx rtl, int first)
7411 {
7412 rtx symbol;
7413
7414 if (GET_CODE (rtl) != MEM)
7415 return;
7416
7417 symbol = XEXP (rtl, 0);
7418
7419 if (GET_CODE (symbol) != SYMBOL_REF)
7420 return;
7421
7422 if (TARGET_MIPS16)
7423 {
7424 if (first && TREE_CODE (decl) == STRING_CST
7425 && ! flag_writable_strings
7426 /* If this string is from a function, and the function will
7427 go in a gnu linkonce section, then we can't directly
7428 access the string. This gets an assembler error
7429 "unsupported PC relative reference to different section".
7430 If we modify SELECT_SECTION to put it in function_section
7431 instead of text_section, it still fails because
7432 DECL_SECTION_NAME isn't set until assemble_start_function.
7433 If we fix that, it still fails because strings are shared
7434 among multiple functions, and we have cross section
7435 references again. We force it to work by putting string
7436 addresses in the constant pool and indirecting. */
7437 && (! current_function_decl
7438 || ! DECL_ONE_ONLY (current_function_decl)))
7439 {
7440 mips16_strings = alloc_EXPR_LIST (0, symbol, mips16_strings);
7441 SYMBOL_REF_FLAG (symbol) = 1;
7442 mips_string_length += TREE_STRING_LENGTH (decl);
7443 }
7444 }
7445
7446 if (TARGET_EMBEDDED_PIC)
7447 {
7448 if (TREE_CODE (decl) == VAR_DECL)
7449 SYMBOL_REF_FLAG (symbol) = 1;
7450 else if (TREE_CODE (decl) == FUNCTION_DECL)
7451 SYMBOL_REF_FLAG (symbol) = 0;
7452 else if (TREE_CODE (decl) == STRING_CST
7453 && ! flag_writable_strings)
7454 SYMBOL_REF_FLAG (symbol) = 0;
7455 else
7456 SYMBOL_REF_FLAG (symbol) = 1;
7457 }
7458
7459 default_encode_section_info (decl, rtl, first);
7460 }
7461
7462 /* See whether VALTYPE is a record whose fields should be returned in
7463 floating-point registers. If so, return the number of fields and
7464 list them in FIELDS (which should have two elements). Return 0
7465 otherwise.
7466
7467 For n32 & n64, a structure with one or two fields is returned in
7468 floating-point registers as long as every field has a floating-point
7469 type. */
7470
7471 static int
mips_fpr_return_fields(tree valtype,tree * fields)7472 mips_fpr_return_fields (tree valtype, tree *fields)
7473 {
7474 tree field;
7475 int i;
7476
7477 if (!TARGET_NEWABI)
7478 return 0;
7479
7480 if (TREE_CODE (valtype) != RECORD_TYPE)
7481 return 0;
7482
7483 i = 0;
7484 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7485 {
7486 if (TREE_CODE (field) != FIELD_DECL)
7487 continue;
7488
7489 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7490 return 0;
7491
7492 if (i == 2)
7493 return 0;
7494
7495 fields[i++] = field;
7496 }
7497 return i;
7498 }
7499
7500
7501 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7502 a value in the most significant part of $2/$3 if:
7503
7504 - the target is big-endian;
7505
7506 - the value has a structure or union type (we generalize this to
7507 cover aggregates from other languages too); and
7508
7509 - the structure is not returned in floating-point registers. */
7510
7511 static bool
mips_return_in_msb(tree valtype)7512 mips_return_in_msb (tree valtype)
7513 {
7514 tree fields[2];
7515
7516 return (TARGET_NEWABI
7517 && TARGET_BIG_ENDIAN
7518 && AGGREGATE_TYPE_P (valtype)
7519 && mips_fpr_return_fields (valtype, fields) == 0);
7520 }
7521
7522
7523 /* Return a composite value in a pair of floating-point registers.
7524 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7525 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7526 complete value.
7527
7528 For n32 & n64, $f0 always holds the first value and $f2 the second.
7529 Otherwise the values are packed together as closely as possible. */
7530
7531 static rtx
mips_return_fpr_pair(enum machine_mode mode,enum machine_mode mode1,HOST_WIDE_INT offset1,enum machine_mode mode2,HOST_WIDE_INT offset2)7532 mips_return_fpr_pair (enum machine_mode mode,
7533 enum machine_mode mode1, HOST_WIDE_INT offset1,
7534 enum machine_mode mode2, HOST_WIDE_INT offset2)
7535 {
7536 int inc;
7537
7538 inc = (TARGET_NEWABI ? 2 : FP_INC);
7539 return gen_rtx_PARALLEL
7540 (mode,
7541 gen_rtvec (2,
7542 gen_rtx_EXPR_LIST (VOIDmode,
7543 gen_rtx_REG (mode1, FP_RETURN),
7544 GEN_INT (offset1)),
7545 gen_rtx_EXPR_LIST (VOIDmode,
7546 gen_rtx_REG (mode2, FP_RETURN + inc),
7547 GEN_INT (offset2))));
7548
7549 }
7550
7551
7552 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7553 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7554 VALTYPE is null and MODE is the mode of the return value. */
7555
7556 rtx
mips_function_value(tree valtype,tree func ATTRIBUTE_UNUSED,enum machine_mode mode)7557 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7558 enum machine_mode mode)
7559 {
7560 if (valtype)
7561 {
7562 tree fields[2];
7563 int unsignedp;
7564
7565 mode = TYPE_MODE (valtype);
7566 unsignedp = TREE_UNSIGNED (valtype);
7567
7568 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote
7569 the mode just as PROMOTE_MODE does. */
7570 mode = promote_mode (valtype, mode, &unsignedp, 1);
7571
7572 /* Handle structures whose fields are returned in $f0/$f2. */
7573 switch (mips_fpr_return_fields (valtype, fields))
7574 {
7575 case 1:
7576 return gen_rtx_REG (mode, FP_RETURN);
7577
7578 case 2:
7579 return mips_return_fpr_pair (mode,
7580 TYPE_MODE (TREE_TYPE (fields[0])),
7581 int_byte_position (fields[0]),
7582 TYPE_MODE (TREE_TYPE (fields[1])),
7583 int_byte_position (fields[1]));
7584 }
7585
7586 /* If a value is passed in the most significant part of a register, see
7587 whether we have to round the mode up to a whole number of words. */
7588 if (mips_return_in_msb (valtype))
7589 {
7590 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7591 if (size % UNITS_PER_WORD != 0)
7592 {
7593 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7594 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7595 }
7596 }
7597 }
7598
7599 if (GET_MODE_CLASS (mode) == MODE_FLOAT
7600 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7601 return gen_rtx_REG (mode, FP_RETURN);
7602
7603 /* Handle long doubles for n32 & n64. */
7604 if (mode == TFmode)
7605 return mips_return_fpr_pair (mode,
7606 DImode, 0,
7607 DImode, GET_MODE_SIZE (mode) / 2);
7608
7609 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7610 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7611 return mips_return_fpr_pair (mode,
7612 GET_MODE_INNER (mode), 0,
7613 GET_MODE_INNER (mode),
7614 GET_MODE_SIZE (mode) / 2);
7615
7616 return gen_rtx_REG (mode, GP_RETURN);
7617 }
7618
7619 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7620 nonzero when an argument must be passed by reference. */
7621
7622 int
function_arg_pass_by_reference(const CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED,enum machine_mode mode,tree type,int named ATTRIBUTE_UNUSED)7623 function_arg_pass_by_reference (const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7624 enum machine_mode mode, tree type,
7625 int named ATTRIBUTE_UNUSED)
7626 {
7627 int size;
7628
7629 /* The EABI is the only one to pass args by reference. */
7630 if (mips_abi != ABI_EABI)
7631 return 0;
7632
7633 /* ??? How should SCmode be handled? */
7634 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7635 return 0;
7636
7637 size = int_size_in_bytes (type);
7638 return size == -1 || size > UNITS_PER_WORD;
7639 }
7640
7641 /* Return the class of registers for which a mode change from FROM to TO
7642 is invalid.
7643
7644 In little-endian mode, the hi-lo registers are numbered backwards,
7645 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
7646 word as intended.
7647
7648 Similarly, when using paired floating-point registers, the first
7649 register holds the low word, regardless of endianness. So in big
7650 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
7651 as intended.
7652
7653 Also, loading a 32-bit value into a 64-bit floating-point register
7654 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7655 We can't allow 64-bit float registers to change from a 32-bit
7656 mode to a 64-bit mode. */
7657
7658 bool
mips_cannot_change_mode_class(enum machine_mode from,enum machine_mode to,enum reg_class class)7659 mips_cannot_change_mode_class (enum machine_mode from,
7660 enum machine_mode to, enum reg_class class)
7661 {
7662 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
7663 {
7664 if (TARGET_BIG_ENDIAN)
7665 return reg_classes_intersect_p (FP_REGS, class);
7666 if (TARGET_FLOAT64)
7667 return reg_classes_intersect_p (HI_AND_FP_REGS, class);
7668 return reg_classes_intersect_p (HI_REG, class);
7669 }
7670 return false;
7671 }
7672
7673 /* Return true if X should not be moved directly into register $25.
7674 We need this because many versions of GAS will treat "la $25,foo" as
7675 part of a call sequence and so allow a global "foo" to be lazily bound. */
7676
7677 bool
mips_dangerous_for_la25_p(rtx x)7678 mips_dangerous_for_la25_p (rtx x)
7679 {
7680 HOST_WIDE_INT offset;
7681
7682 if (TARGET_EXPLICIT_RELOCS)
7683 return false;
7684
7685 mips_split_const (x, &x, &offset);
7686 return global_got_operand (x, VOIDmode);
7687 }
7688
7689 /* Implement PREFERRED_RELOAD_CLASS. */
7690
7691 enum reg_class
mips_preferred_reload_class(rtx x,enum reg_class class)7692 mips_preferred_reload_class (rtx x, enum reg_class class)
7693 {
7694 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7695 return LEA_REGS;
7696
7697 if (TARGET_HARD_FLOAT
7698 && FLOAT_MODE_P (GET_MODE (x))
7699 && reg_class_subset_p (FP_REGS, class))
7700 return FP_REGS;
7701
7702 if (reg_class_subset_p (GR_REGS, class))
7703 class = GR_REGS;
7704
7705 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7706 class = M16_REGS;
7707
7708 return class;
7709 }
7710
7711 /* This function returns the register class required for a secondary
7712 register when copying between one of the registers in CLASS, and X,
7713 using MODE. If IN_P is nonzero, the copy is going from X to the
7714 register, otherwise the register is the source. A return value of
7715 NO_REGS means that no secondary register is required. */
7716
7717 enum reg_class
mips_secondary_reload_class(enum reg_class class,enum machine_mode mode,rtx x,int in_p)7718 mips_secondary_reload_class (enum reg_class class,
7719 enum machine_mode mode, rtx x, int in_p)
7720 {
7721 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7722 int regno = -1;
7723 int gp_reg_p;
7724
7725 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7726 regno = true_regnum (x);
7727
7728 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7729
7730 if (mips_dangerous_for_la25_p (x))
7731 {
7732 gr_regs = LEA_REGS;
7733 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7734 return gr_regs;
7735 }
7736
7737 /* Copying from HI or LO to anywhere other than a general register
7738 requires a general register. */
7739 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7740 {
7741 if (TARGET_MIPS16 && in_p)
7742 {
7743 /* We can't really copy to HI or LO at all in mips16 mode. */
7744 return M16_REGS;
7745 }
7746 return gp_reg_p ? NO_REGS : gr_regs;
7747 }
7748 if (MD_REG_P (regno))
7749 {
7750 if (TARGET_MIPS16 && ! in_p)
7751 {
7752 /* We can't really copy to HI or LO at all in mips16 mode. */
7753 return M16_REGS;
7754 }
7755 return class == gr_regs ? NO_REGS : gr_regs;
7756 }
7757
7758 /* We can only copy a value to a condition code register from a
7759 floating point register, and even then we require a scratch
7760 floating point register. We can only copy a value out of a
7761 condition code register into a general register. */
7762 if (class == ST_REGS)
7763 {
7764 if (in_p)
7765 return FP_REGS;
7766 return gp_reg_p ? NO_REGS : gr_regs;
7767 }
7768 if (ST_REG_P (regno))
7769 {
7770 if (! in_p)
7771 return FP_REGS;
7772 return class == gr_regs ? NO_REGS : gr_regs;
7773 }
7774
7775 if (class == FP_REGS)
7776 {
7777 if (GET_CODE (x) == MEM)
7778 {
7779 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7780 return NO_REGS;
7781 }
7782 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7783 {
7784 /* We can use the l.s and l.d macros to load floating-point
7785 constants. ??? For l.s, we could probably get better
7786 code by returning GR_REGS here. */
7787 return NO_REGS;
7788 }
7789 else if (gp_reg_p || x == CONST0_RTX (mode))
7790 {
7791 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7792 return NO_REGS;
7793 }
7794 else if (FP_REG_P (regno))
7795 {
7796 /* In this case we can use mov.s or mov.d. */
7797 return NO_REGS;
7798 }
7799 else
7800 {
7801 /* Otherwise, we need to reload through an integer register. */
7802 return gr_regs;
7803 }
7804 }
7805
7806 /* In mips16 mode, going between memory and anything but M16_REGS
7807 requires an M16_REG. */
7808 if (TARGET_MIPS16)
7809 {
7810 if (class != M16_REGS && class != M16_NA_REGS)
7811 {
7812 if (gp_reg_p)
7813 return NO_REGS;
7814 return M16_REGS;
7815 }
7816 if (! gp_reg_p)
7817 {
7818 if (class == M16_REGS || class == M16_NA_REGS)
7819 return NO_REGS;
7820 return M16_REGS;
7821 }
7822 }
7823
7824 return NO_REGS;
7825 }
7826
7827 /* Implement CLASS_MAX_NREGS.
7828
7829 Usually all registers are word-sized. The only supported exception
7830 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7831 registers. A word-based calculation is correct even in that case,
7832 since -msingle-float disallows multi-FPR values. */
7833
7834 int
mips_class_max_nregs(enum reg_class class ATTRIBUTE_UNUSED,enum machine_mode mode)7835 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7836 enum machine_mode mode)
7837 {
7838 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7839 }
7840
7841 bool
mips_valid_pointer_mode(enum machine_mode mode)7842 mips_valid_pointer_mode (enum machine_mode mode)
7843 {
7844 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7845 }
7846
7847
7848 /* If we can access small data directly (using gp-relative relocation
7849 operators) return the small data pointer, otherwise return null.
7850
7851 For each mips16 function which refers to GP relative symbols, we
7852 use a pseudo register, initialized at the start of the function, to
7853 hold the $gp value. */
7854
7855 static rtx
mips16_gp_pseudo_reg(void)7856 mips16_gp_pseudo_reg (void)
7857 {
7858 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7859 {
7860 rtx unspec;
7861 rtx insn, scan;
7862
7863 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7864 RTX_UNCHANGING_P (cfun->machine->mips16_gp_pseudo_rtx) = 1;
7865
7866 /* We want to initialize this to a value which gcc will believe
7867 is constant. */
7868 start_sequence ();
7869 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7870 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7871 gen_rtx_CONST (Pmode, unspec));
7872 insn = get_insns ();
7873 end_sequence ();
7874
7875 push_topmost_sequence ();
7876 /* We need to emit the initialization after the FUNCTION_BEG
7877 note, so that it will be integrated. */
7878 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7879 if (GET_CODE (scan) == NOTE
7880 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7881 break;
7882 if (scan == NULL_RTX)
7883 scan = get_insns ();
7884 insn = emit_insn_after (insn, scan);
7885 pop_topmost_sequence ();
7886 }
7887
7888 return cfun->machine->mips16_gp_pseudo_rtx;
7889 }
7890
7891 /* Write out code to move floating point arguments in or out of
7892 general registers. Output the instructions to FILE. FP_CODE is
7893 the code describing which arguments are present (see the comment at
7894 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7895 we are copying from the floating point registers. */
7896
7897 static void
mips16_fp_args(FILE * file,int fp_code,int from_fp_p)7898 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7899 {
7900 const char *s;
7901 int gparg, fparg;
7902 unsigned int f;
7903
7904 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7905 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
7906 abort ();
7907
7908 if (from_fp_p)
7909 s = "mfc1";
7910 else
7911 s = "mtc1";
7912 gparg = GP_ARG_FIRST;
7913 fparg = FP_ARG_FIRST;
7914 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7915 {
7916 if ((f & 3) == 1)
7917 {
7918 if ((fparg & 1) != 0)
7919 ++fparg;
7920 fprintf (file, "\t%s\t%s,%s\n", s,
7921 reg_names[gparg], reg_names[fparg]);
7922 }
7923 else if ((f & 3) == 2)
7924 {
7925 if (TARGET_64BIT)
7926 fprintf (file, "\td%s\t%s,%s\n", s,
7927 reg_names[gparg], reg_names[fparg]);
7928 else
7929 {
7930 if ((fparg & 1) != 0)
7931 ++fparg;
7932 if (TARGET_BIG_ENDIAN)
7933 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7934 reg_names[gparg], reg_names[fparg + 1], s,
7935 reg_names[gparg + 1], reg_names[fparg]);
7936 else
7937 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7938 reg_names[gparg], reg_names[fparg], s,
7939 reg_names[gparg + 1], reg_names[fparg + 1]);
7940 ++gparg;
7941 ++fparg;
7942 }
7943 }
7944 else
7945 abort ();
7946
7947 ++gparg;
7948 ++fparg;
7949 }
7950 }
7951
7952 /* Build a mips16 function stub. This is used for functions which
7953 take arguments in the floating point registers. It is 32 bit code
7954 that moves the floating point args into the general registers, and
7955 then jumps to the 16 bit code. */
7956
7957 static void
build_mips16_function_stub(FILE * file)7958 build_mips16_function_stub (FILE *file)
7959 {
7960 const char *fnname;
7961 char *secname, *stubname;
7962 tree stubid, stubdecl;
7963 int need_comma;
7964 unsigned int f;
7965
7966 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7967 secname = (char *) alloca (strlen (fnname) + 20);
7968 sprintf (secname, ".mips16.fn.%s", fnname);
7969 stubname = (char *) alloca (strlen (fnname) + 20);
7970 sprintf (stubname, "__fn_stub_%s", fnname);
7971 stubid = get_identifier (stubname);
7972 stubdecl = build_decl (FUNCTION_DECL, stubid,
7973 build_function_type (void_type_node, NULL_TREE));
7974 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7975
7976 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7977 need_comma = 0;
7978 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7979 {
7980 fprintf (file, "%s%s",
7981 need_comma ? ", " : "",
7982 (f & 3) == 1 ? "float" : "double");
7983 need_comma = 1;
7984 }
7985 fprintf (file, ")\n");
7986
7987 fprintf (file, "\t.set\tnomips16\n");
7988 function_section (stubdecl);
7989 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7990
7991 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7992 within a .ent, and we can not emit another .ent. */
7993 if (!FUNCTION_NAME_ALREADY_DECLARED)
7994 {
7995 fputs ("\t.ent\t", file);
7996 assemble_name (file, stubname);
7997 fputs ("\n", file);
7998 }
7999
8000 assemble_name (file, stubname);
8001 fputs (":\n", file);
8002
8003 /* We don't want the assembler to insert any nops here. */
8004 fprintf (file, "\t.set\tnoreorder\n");
8005
8006 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8007
8008 fprintf (asm_out_file, "\t.set\tnoat\n");
8009 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8010 assemble_name (file, fnname);
8011 fprintf (file, "\n");
8012 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8013 fprintf (asm_out_file, "\t.set\tat\n");
8014
8015 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8016 with one of the mfc1 instructions, because the result is not
8017 available for one instruction, so if the very first instruction
8018 in the function refers to the register, it will see the wrong
8019 value. */
8020 fprintf (file, "\tnop\n");
8021
8022 fprintf (file, "\t.set\treorder\n");
8023
8024 if (!FUNCTION_NAME_ALREADY_DECLARED)
8025 {
8026 fputs ("\t.end\t", file);
8027 assemble_name (file, stubname);
8028 fputs ("\n", file);
8029 }
8030
8031 fprintf (file, "\t.set\tmips16\n");
8032
8033 function_section (current_function_decl);
8034 }
8035
8036 /* We keep a list of functions for which we have already built stubs
8037 in build_mips16_call_stub. */
8038
8039 struct mips16_stub
8040 {
8041 struct mips16_stub *next;
8042 char *name;
8043 int fpret;
8044 };
8045
8046 static struct mips16_stub *mips16_stubs;
8047
8048 /* Build a call stub for a mips16 call. A stub is needed if we are
8049 passing any floating point values which should go into the floating
8050 point registers. If we are, and the call turns out to be to a 32
8051 bit function, the stub will be used to move the values into the
8052 floating point registers before calling the 32 bit function. The
8053 linker will magically adjust the function call to either the 16 bit
8054 function or the 32 bit stub, depending upon where the function call
8055 is actually defined.
8056
8057 Similarly, we need a stub if the return value might come back in a
8058 floating point register.
8059
8060 RETVAL is the location of the return value, or null if this is
8061 a call rather than a call_value. FN is the address of the
8062 function and ARG_SIZE is the size of the arguments. FP_CODE
8063 is the code built by function_arg. This function returns a nonzero
8064 value if it builds the call instruction itself. */
8065
8066 int
build_mips16_call_stub(rtx retval,rtx fn,rtx arg_size,int fp_code)8067 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8068 {
8069 int fpret;
8070 const char *fnname;
8071 char *secname, *stubname;
8072 struct mips16_stub *l;
8073 tree stubid, stubdecl;
8074 int need_comma;
8075 unsigned int f;
8076
8077 /* We don't need to do anything if we aren't in mips16 mode, or if
8078 we were invoked with the -msoft-float option. */
8079 if (! TARGET_MIPS16 || ! mips16_hard_float)
8080 return 0;
8081
8082 /* Figure out whether the value might come back in a floating point
8083 register. */
8084 fpret = (retval != 0
8085 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8086 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8087
8088 /* We don't need to do anything if there were no floating point
8089 arguments and the value will not be returned in a floating point
8090 register. */
8091 if (fp_code == 0 && ! fpret)
8092 return 0;
8093
8094 /* We don't need to do anything if this is a call to a special
8095 mips16 support function. */
8096 if (GET_CODE (fn) == SYMBOL_REF
8097 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8098 return 0;
8099
8100 /* This code will only work for o32 and o64 abis. The other ABI's
8101 require more sophisticated support. */
8102 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8103 abort ();
8104
8105 /* We can only handle SFmode and DFmode floating point return
8106 values. */
8107 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8108 abort ();
8109
8110 /* If we're calling via a function pointer, then we must always call
8111 via a stub. There are magic stubs provided in libgcc.a for each
8112 of the required cases. Each of them expects the function address
8113 to arrive in register $2. */
8114
8115 if (GET_CODE (fn) != SYMBOL_REF)
8116 {
8117 char buf[30];
8118 tree id;
8119 rtx stub_fn, insn;
8120
8121 /* ??? If this code is modified to support other ABI's, we need
8122 to handle PARALLEL return values here. */
8123
8124 sprintf (buf, "__mips16_call_stub_%s%d",
8125 (fpret
8126 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8127 : ""),
8128 fp_code);
8129 id = get_identifier (buf);
8130 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
8131
8132 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
8133
8134 if (retval == NULL_RTX)
8135 insn = gen_call_internal (stub_fn, arg_size);
8136 else
8137 insn = gen_call_value_internal (retval, stub_fn, arg_size);
8138 insn = emit_call_insn (insn);
8139
8140 /* Put the register usage information on the CALL. */
8141 if (GET_CODE (insn) != CALL_INSN)
8142 abort ();
8143 CALL_INSN_FUNCTION_USAGE (insn) =
8144 gen_rtx (EXPR_LIST, VOIDmode,
8145 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
8146 CALL_INSN_FUNCTION_USAGE (insn));
8147
8148 /* If we are handling a floating point return value, we need to
8149 save $18 in the function prologue. Putting a note on the
8150 call will mean that regs_ever_live[$18] will be true if the
8151 call is not eliminated, and we can check that in the prologue
8152 code. */
8153 if (fpret)
8154 CALL_INSN_FUNCTION_USAGE (insn) =
8155 gen_rtx (EXPR_LIST, VOIDmode,
8156 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8157 CALL_INSN_FUNCTION_USAGE (insn));
8158
8159 /* Return 1 to tell the caller that we've generated the call
8160 insn. */
8161 return 1;
8162 }
8163
8164 /* We know the function we are going to call. If we have already
8165 built a stub, we don't need to do anything further. */
8166
8167 fnname = XSTR (fn, 0);
8168 for (l = mips16_stubs; l != NULL; l = l->next)
8169 if (strcmp (l->name, fnname) == 0)
8170 break;
8171
8172 if (l == NULL)
8173 {
8174 /* Build a special purpose stub. When the linker sees a
8175 function call in mips16 code, it will check where the target
8176 is defined. If the target is a 32 bit call, the linker will
8177 search for the section defined here. It can tell which
8178 symbol this section is associated with by looking at the
8179 relocation information (the name is unreliable, since this
8180 might be a static function). If such a section is found, the
8181 linker will redirect the call to the start of the magic
8182 section.
8183
8184 If the function does not return a floating point value, the
8185 special stub section is named
8186 .mips16.call.FNNAME
8187
8188 If the function does return a floating point value, the stub
8189 section is named
8190 .mips16.call.fp.FNNAME
8191 */
8192
8193 secname = (char *) alloca (strlen (fnname) + 40);
8194 sprintf (secname, ".mips16.call.%s%s",
8195 fpret ? "fp." : "",
8196 fnname);
8197 stubname = (char *) alloca (strlen (fnname) + 20);
8198 sprintf (stubname, "__call_stub_%s%s",
8199 fpret ? "fp_" : "",
8200 fnname);
8201 stubid = get_identifier (stubname);
8202 stubdecl = build_decl (FUNCTION_DECL, stubid,
8203 build_function_type (void_type_node, NULL_TREE));
8204 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8205
8206 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8207 (fpret
8208 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8209 : ""),
8210 fnname);
8211 need_comma = 0;
8212 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8213 {
8214 fprintf (asm_out_file, "%s%s",
8215 need_comma ? ", " : "",
8216 (f & 3) == 1 ? "float" : "double");
8217 need_comma = 1;
8218 }
8219 fprintf (asm_out_file, ")\n");
8220
8221 fprintf (asm_out_file, "\t.set\tnomips16\n");
8222 assemble_start_function (stubdecl, stubname);
8223
8224 if (!FUNCTION_NAME_ALREADY_DECLARED)
8225 {
8226 fputs ("\t.ent\t", asm_out_file);
8227 assemble_name (asm_out_file, stubname);
8228 fputs ("\n", asm_out_file);
8229
8230 assemble_name (asm_out_file, stubname);
8231 fputs (":\n", asm_out_file);
8232 }
8233
8234 /* We build the stub code by hand. That's the only way we can
8235 do it, since we can't generate 32 bit code during a 16 bit
8236 compilation. */
8237
8238 /* We don't want the assembler to insert any nops here. */
8239 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8240
8241 mips16_fp_args (asm_out_file, fp_code, 0);
8242
8243 if (! fpret)
8244 {
8245 fprintf (asm_out_file, "\t.set\tnoat\n");
8246 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8247 fnname);
8248 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8249 fprintf (asm_out_file, "\t.set\tat\n");
8250 /* Unfortunately, we can't fill the jump delay slot. We
8251 can't fill with one of the mtc1 instructions, because the
8252 result is not available for one instruction, so if the
8253 very first instruction in the function refers to the
8254 register, it will see the wrong value. */
8255 fprintf (asm_out_file, "\tnop\n");
8256 }
8257 else
8258 {
8259 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8260 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8261 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8262 /* As above, we can't fill the delay slot. */
8263 fprintf (asm_out_file, "\tnop\n");
8264 if (GET_MODE (retval) == SFmode)
8265 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8266 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8267 else
8268 {
8269 if (TARGET_BIG_ENDIAN)
8270 {
8271 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8272 reg_names[GP_REG_FIRST + 2],
8273 reg_names[FP_REG_FIRST + 1]);
8274 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8275 reg_names[GP_REG_FIRST + 3],
8276 reg_names[FP_REG_FIRST + 0]);
8277 }
8278 else
8279 {
8280 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8281 reg_names[GP_REG_FIRST + 2],
8282 reg_names[FP_REG_FIRST + 0]);
8283 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8284 reg_names[GP_REG_FIRST + 3],
8285 reg_names[FP_REG_FIRST + 1]);
8286 }
8287 }
8288 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8289 /* As above, we can't fill the delay slot. */
8290 fprintf (asm_out_file, "\tnop\n");
8291 }
8292
8293 fprintf (asm_out_file, "\t.set\treorder\n");
8294
8295 #ifdef ASM_DECLARE_FUNCTION_SIZE
8296 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8297 #endif
8298
8299 if (!FUNCTION_NAME_ALREADY_DECLARED)
8300 {
8301 fputs ("\t.end\t", asm_out_file);
8302 assemble_name (asm_out_file, stubname);
8303 fputs ("\n", asm_out_file);
8304 }
8305
8306 fprintf (asm_out_file, "\t.set\tmips16\n");
8307
8308 /* Record this stub. */
8309 l = (struct mips16_stub *) xmalloc (sizeof *l);
8310 l->name = xstrdup (fnname);
8311 l->fpret = fpret;
8312 l->next = mips16_stubs;
8313 mips16_stubs = l;
8314 }
8315
8316 /* If we expect a floating point return value, but we've built a
8317 stub which does not expect one, then we're in trouble. We can't
8318 use the existing stub, because it won't handle the floating point
8319 value. We can't build a new stub, because the linker won't know
8320 which stub to use for the various calls in this object file.
8321 Fortunately, this case is illegal, since it means that a function
8322 was declared in two different ways in a single compilation. */
8323 if (fpret && ! l->fpret)
8324 error ("can not handle inconsistent calls to `%s'", fnname);
8325
8326 /* If we are calling a stub which handles a floating point return
8327 value, we need to arrange to save $18 in the prologue. We do
8328 this by marking the function call as using the register. The
8329 prologue will later see that it is used, and emit code to save
8330 it. */
8331
8332 if (l->fpret)
8333 {
8334 rtx insn;
8335
8336 if (retval == NULL_RTX)
8337 insn = gen_call_internal (fn, arg_size);
8338 else
8339 insn = gen_call_value_internal (retval, fn, arg_size);
8340 insn = emit_call_insn (insn);
8341
8342 if (GET_CODE (insn) != CALL_INSN)
8343 abort ();
8344
8345 CALL_INSN_FUNCTION_USAGE (insn) =
8346 gen_rtx (EXPR_LIST, VOIDmode,
8347 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8348 CALL_INSN_FUNCTION_USAGE (insn));
8349
8350 /* Return 1 to tell the caller that we've generated the call
8351 insn. */
8352 return 1;
8353 }
8354
8355 /* Return 0 to let the caller generate the call insn. */
8356 return 0;
8357 }
8358
8359 /* We keep a list of constants we which we have to add to internal
8360 constant tables in the middle of large functions. */
8361
8362 struct constant
8363 {
8364 struct constant *next;
8365 rtx value;
8366 rtx label;
8367 enum machine_mode mode;
8368 };
8369
8370 /* Add a constant to the list in *PCONSTANTS. */
8371
8372 static rtx
add_constant(struct constant ** pconstants,rtx val,enum machine_mode mode)8373 add_constant (struct constant **pconstants, rtx val, enum machine_mode mode)
8374 {
8375 struct constant *c;
8376
8377 for (c = *pconstants; c != NULL; c = c->next)
8378 if (mode == c->mode && rtx_equal_p (val, c->value))
8379 return c->label;
8380
8381 c = (struct constant *) xmalloc (sizeof *c);
8382 c->value = val;
8383 c->mode = mode;
8384 c->label = gen_label_rtx ();
8385 c->next = *pconstants;
8386 *pconstants = c;
8387 return c->label;
8388 }
8389
8390 /* Dump out the constants in CONSTANTS after INSN. */
8391
8392 static void
dump_constants(struct constant * constants,rtx insn)8393 dump_constants (struct constant *constants, rtx insn)
8394 {
8395 struct constant *c;
8396 int align;
8397
8398 c = constants;
8399 align = 0;
8400 while (c != NULL)
8401 {
8402 rtx r;
8403 struct constant *next;
8404
8405 switch (GET_MODE_SIZE (c->mode))
8406 {
8407 case 1:
8408 align = 0;
8409 break;
8410 case 2:
8411 if (align < 1)
8412 insn = emit_insn_after (gen_align_2 (), insn);
8413 align = 1;
8414 break;
8415 case 4:
8416 if (align < 2)
8417 insn = emit_insn_after (gen_align_4 (), insn);
8418 align = 2;
8419 break;
8420 default:
8421 if (align < 3)
8422 insn = emit_insn_after (gen_align_8 (), insn);
8423 align = 3;
8424 break;
8425 }
8426
8427 insn = emit_label_after (c->label, insn);
8428
8429 switch (c->mode)
8430 {
8431 case QImode:
8432 r = gen_consttable_qi (c->value);
8433 break;
8434 case HImode:
8435 r = gen_consttable_hi (c->value);
8436 break;
8437 case SImode:
8438 r = gen_consttable_si (c->value);
8439 break;
8440 case SFmode:
8441 r = gen_consttable_sf (c->value);
8442 break;
8443 case DImode:
8444 r = gen_consttable_di (c->value);
8445 break;
8446 case DFmode:
8447 r = gen_consttable_df (c->value);
8448 break;
8449 default:
8450 abort ();
8451 }
8452
8453 insn = emit_insn_after (r, insn);
8454
8455 next = c->next;
8456 free (c);
8457 c = next;
8458 }
8459
8460 emit_barrier_after (insn);
8461 }
8462
8463 /* Find the symbol in an address expression. */
8464
8465 static rtx
mips_find_symbol(rtx addr)8466 mips_find_symbol (rtx addr)
8467 {
8468 if (GET_CODE (addr) == MEM)
8469 addr = XEXP (addr, 0);
8470 while (GET_CODE (addr) == CONST)
8471 addr = XEXP (addr, 0);
8472 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
8473 return addr;
8474 if (GET_CODE (addr) == PLUS)
8475 {
8476 rtx l1, l2;
8477
8478 l1 = mips_find_symbol (XEXP (addr, 0));
8479 l2 = mips_find_symbol (XEXP (addr, 1));
8480 if (l1 != NULL_RTX && l2 == NULL_RTX)
8481 return l1;
8482 else if (l1 == NULL_RTX && l2 != NULL_RTX)
8483 return l2;
8484 }
8485 return NULL_RTX;
8486 }
8487
8488 /* In mips16 mode, we need to look through the function to check for
8489 PC relative loads that are out of range. */
8490
8491 static void
mips16_lay_out_constants(void)8492 mips16_lay_out_constants (void)
8493 {
8494 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
8495 rtx first, insn;
8496 struct constant *constants;
8497
8498 first = get_insns ();
8499
8500 /* Scan the function looking for PC relative loads which may be out
8501 of range. All such loads will either be from the constant table,
8502 or be getting the address of a constant string. If the size of
8503 the function plus the size of the constant table is less than
8504 0x8000, then all loads are in range. */
8505
8506 insns_len = 0;
8507 for (insn = first; insn; insn = NEXT_INSN (insn))
8508 {
8509 insns_len += get_attr_length (insn);
8510
8511 /* ??? We put switch tables in .text, but we don't define
8512 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8513 compute their lengths correctly. */
8514 if (GET_CODE (insn) == JUMP_INSN)
8515 {
8516 rtx body;
8517
8518 body = PATTERN (insn);
8519 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8520 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8521 * GET_MODE_SIZE (GET_MODE (body)));
8522 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
8523 }
8524 }
8525
8526 /* Store the original value of insns_len in cfun->machine, so
8527 that simple_memory_operand can look at it. */
8528 cfun->machine->insns_len = insns_len;
8529
8530 pool_size = get_pool_size ();
8531 if (insns_len + pool_size + mips_string_length < 0x8000)
8532 return;
8533
8534 /* Loop over the insns and figure out what the maximum internal pool
8535 size could be. */
8536 max_internal_pool_size = 0;
8537 for (insn = first; insn; insn = NEXT_INSN (insn))
8538 {
8539 if (GET_CODE (insn) == INSN
8540 && GET_CODE (PATTERN (insn)) == SET)
8541 {
8542 rtx src;
8543
8544 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8545 if (src == NULL_RTX)
8546 continue;
8547 if (CONSTANT_POOL_ADDRESS_P (src))
8548 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
8549 else if (SYMBOL_REF_FLAG (src))
8550 max_internal_pool_size += GET_MODE_SIZE (Pmode);
8551 }
8552 }
8553
8554 constants = NULL;
8555 addr = 0;
8556 first_constant_ref = -1;
8557
8558 for (insn = first; insn; insn = NEXT_INSN (insn))
8559 {
8560 if (GET_CODE (insn) == INSN
8561 && GET_CODE (PATTERN (insn)) == SET)
8562 {
8563 rtx val, src;
8564 enum machine_mode mode = VOIDmode;
8565
8566 val = NULL_RTX;
8567 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8568 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
8569 {
8570 /* ??? This is very conservative, which means that we
8571 will generate too many copies of the constant table.
8572 The only solution would seem to be some form of
8573 relaxing. */
8574 if (((insns_len - addr)
8575 + max_internal_pool_size
8576 + get_pool_offset (src))
8577 >= 0x8000)
8578 {
8579 val = get_pool_constant (src);
8580 mode = get_pool_mode (src);
8581 }
8582 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
8583 }
8584 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
8585 {
8586 /* Including all of mips_string_length is conservative,
8587 and so is including all of max_internal_pool_size. */
8588 if (((insns_len - addr)
8589 + max_internal_pool_size
8590 + pool_size
8591 + mips_string_length)
8592 >= 0x8000)
8593 {
8594 val = src;
8595 mode = Pmode;
8596 }
8597 max_internal_pool_size -= Pmode;
8598 }
8599
8600 if (val != NULL_RTX)
8601 {
8602 rtx lab, newsrc;
8603
8604 /* This PC relative load is out of range. ??? In the
8605 case of a string constant, we are only guessing that
8606 it is range, since we don't know the offset of a
8607 particular string constant. */
8608
8609 lab = add_constant (&constants, val, mode);
8610 newsrc = gen_rtx (MEM, mode,
8611 gen_rtx (LABEL_REF, VOIDmode, lab));
8612 RTX_UNCHANGING_P (newsrc) = 1;
8613 PATTERN (insn) = gen_rtx (SET, VOIDmode,
8614 SET_DEST (PATTERN (insn)),
8615 newsrc);
8616 INSN_CODE (insn) = -1;
8617
8618 if (first_constant_ref < 0)
8619 first_constant_ref = addr;
8620 }
8621 }
8622
8623 addr += get_attr_length (insn);
8624
8625 /* ??? We put switch tables in .text, but we don't define
8626 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8627 compute their lengths correctly. */
8628 if (GET_CODE (insn) == JUMP_INSN)
8629 {
8630 rtx body;
8631
8632 body = PATTERN (insn);
8633 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8634 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8635 * GET_MODE_SIZE (GET_MODE (body)));
8636 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
8637 }
8638
8639 if (GET_CODE (insn) == BARRIER)
8640 {
8641 /* Output any constants we have accumulated. Note that we
8642 don't need to change ADDR, since its only use is
8643 subtraction from INSNS_LEN, and both would be changed by
8644 the same amount.
8645 ??? If the instructions up to the next barrier reuse a
8646 constant, it would often be better to continue
8647 accumulating. */
8648 if (constants != NULL)
8649 dump_constants (constants, insn);
8650 constants = NULL;
8651 first_constant_ref = -1;
8652 }
8653
8654 if (constants != NULL
8655 && (NEXT_INSN (insn) == NULL
8656 || (first_constant_ref >= 0
8657 && (((addr - first_constant_ref)
8658 + 2 /* for alignment */
8659 + 2 /* for a short jump insn */
8660 + pool_size)
8661 >= 0x8000))))
8662 {
8663 /* If we haven't had a barrier within 0x8000 bytes of a
8664 constant reference or we are at the end of the function,
8665 emit a barrier now. */
8666
8667 rtx label, jump, barrier;
8668
8669 label = gen_label_rtx ();
8670 jump = emit_jump_insn_after (gen_jump (label), insn);
8671 JUMP_LABEL (jump) = label;
8672 LABEL_NUSES (label) = 1;
8673 barrier = emit_barrier_after (jump);
8674 emit_label_after (label, barrier);
8675 first_constant_ref = -1;
8676 }
8677 }
8678
8679 /* ??? If we output all references to a constant in internal
8680 constants table, we don't need to output the constant in the real
8681 constant table, but we have no way to prevent that. */
8682 }
8683
8684
8685 /* Subroutine of mips_reorg. If there is a hazard between INSN
8686 and a previous instruction, avoid it by inserting nops after
8687 instruction AFTER.
8688
8689 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8690 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8691 before using the value of that register. *HILO_DELAY counts the
8692 number of instructions since the last hilo hazard (that is,
8693 the number of instructions since the last mflo or mfhi).
8694
8695 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8696 for the next instruction.
8697
8698 LO_REG is an rtx for the LO register, used in dependence checking. */
8699
8700 static void
mips_avoid_hazard(rtx after,rtx insn,int * hilo_delay,rtx * delayed_reg,rtx lo_reg)8701 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8702 rtx *delayed_reg, rtx lo_reg)
8703 {
8704 rtx pattern, set;
8705 int nops, ninsns;
8706
8707 if (!INSN_P (insn))
8708 return;
8709
8710 pattern = PATTERN (insn);
8711
8712 /* Do not put the whole function in .set noreorder if it contains
8713 an asm statement. We don't know whether there will be hazards
8714 between the asm statement and the gcc-generated code. */
8715 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8716 cfun->machine->all_noreorder_p = false;
8717
8718 /* Ignore zero-length instructions (barriers and the like). */
8719 ninsns = get_attr_length (insn) / 4;
8720 if (ninsns == 0)
8721 return;
8722
8723 /* Work out how many nops are needed. Note that we only care about
8724 registers that are explicitly mentioned in the instruction's pattern.
8725 It doesn't matter that calls use the argument registers or that they
8726 clobber hi and lo. */
8727 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8728 nops = 2 - *hilo_delay;
8729 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8730 nops = 1;
8731 else
8732 nops = 0;
8733
8734 /* Insert the nops between this instruction and the previous one.
8735 Each new nop takes us further from the last hilo hazard. */
8736 *hilo_delay += nops;
8737 while (nops-- > 0)
8738 emit_insn_after (gen_hazard_nop (), after);
8739
8740 /* Set up the state for the next instruction. */
8741 *hilo_delay += ninsns;
8742 *delayed_reg = 0;
8743 if (INSN_CODE (insn) >= 0)
8744 switch (get_attr_hazard (insn))
8745 {
8746 case HAZARD_NONE:
8747 break;
8748
8749 case HAZARD_HILO:
8750 *hilo_delay = 0;
8751 break;
8752
8753 case HAZARD_DELAY:
8754 set = single_set (insn);
8755 if (set == 0)
8756 abort ();
8757 *delayed_reg = SET_DEST (set);
8758 break;
8759 }
8760 }
8761
8762
8763 /* Go through the instruction stream and insert nops where necessary.
8764 See if the whole function can then be put into .set noreorder &
8765 .set nomacro. */
8766
8767 static void
mips_avoid_hazards(void)8768 mips_avoid_hazards (void)
8769 {
8770 rtx insn, last_insn, lo_reg, delayed_reg;
8771 int hilo_delay, i;
8772
8773 /* Force all instructions to be split into their final form. */
8774 split_all_insns_noflow ();
8775
8776 /* Recalculate instruction lengths without taking nops into account. */
8777 cfun->machine->ignore_hazard_length_p = true;
8778 shorten_branches (get_insns ());
8779
8780 /* The profiler code uses assembler macros. */
8781 cfun->machine->all_noreorder_p = !current_function_profile;
8782
8783 last_insn = 0;
8784 hilo_delay = 2;
8785 delayed_reg = 0;
8786 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8787
8788 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8789 if (INSN_P (insn))
8790 {
8791 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8792 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8793 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8794 &hilo_delay, &delayed_reg, lo_reg);
8795 else
8796 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8797 &delayed_reg, lo_reg);
8798
8799 last_insn = insn;
8800 }
8801 }
8802
8803
8804 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8805
8806 static void
mips_reorg(void)8807 mips_reorg (void)
8808 {
8809 if (TARGET_MIPS16)
8810 mips16_lay_out_constants ();
8811 else if (TARGET_EXPLICIT_RELOCS)
8812 {
8813 if (mips_flag_delayed_branch)
8814 dbr_schedule (get_insns (), rtl_dump_file);
8815 mips_avoid_hazards ();
8816 }
8817 }
8818
8819 /* We need to use a special set of functions to handle hard floating
8820 point code in mips16 mode. Also, allow for --enable-gofast. */
8821
8822 #include "config/gofast.h"
8823
8824 static void
mips_init_libfuncs(void)8825 mips_init_libfuncs (void)
8826 {
8827 if (TARGET_MIPS16 && mips16_hard_float)
8828 {
8829 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8830 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8831 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8832 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8833
8834 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8835 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8836 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8837 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8838 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8839 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8840
8841 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fixsfsi");
8842 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8843
8844 if (TARGET_DOUBLE_FLOAT)
8845 {
8846 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8847 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8848 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8849 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8850
8851 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8852 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8853 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8854 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8855 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8856 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8857
8858 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8859 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8860
8861 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fixdfsi");
8862 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8863 }
8864 }
8865 else
8866 gofast_maybe_init_libfuncs ();
8867 }
8868
8869 /* Return a number assessing the cost of moving a register in class
8870 FROM to class TO. The classes are expressed using the enumeration
8871 values such as `GENERAL_REGS'. A value of 2 is the default; other
8872 values are interpreted relative to that.
8873
8874 It is not required that the cost always equal 2 when FROM is the
8875 same as TO; on some machines it is expensive to move between
8876 registers if they are not general registers.
8877
8878 If reload sees an insn consisting of a single `set' between two
8879 hard registers, and if `REGISTER_MOVE_COST' applied to their
8880 classes returns a value of 2, reload does not check to ensure that
8881 the constraints of the insn are met. Setting a cost of other than
8882 2 will allow reload to verify that the constraints are met. You
8883 should do this if the `movM' pattern's constraints do not allow
8884 such copying.
8885
8886 ??? We make the cost of moving from HI/LO into general
8887 registers the same as for one of moving general registers to
8888 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8889 pseudo to HI/LO. This might hurt optimizations though, it
8890 isn't clear if it is wise. And it might not work in all cases. We
8891 could solve the DImode LO reg problem by using a multiply, just
8892 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8893 problem by using divide instructions. divu puts the remainder in
8894 the HI reg, so doing a divide by -1 will move the value in the HI
8895 reg for all values except -1. We could handle that case by using a
8896 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8897 a compare/branch to test the input value to see which instruction
8898 we need to use. This gets pretty messy, but it is feasible. */
8899
8900 int
mips_register_move_cost(enum machine_mode mode ATTRIBUTE_UNUSED,enum reg_class to,enum reg_class from)8901 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8902 enum reg_class to, enum reg_class from)
8903 {
8904 if (from == M16_REGS && GR_REG_CLASS_P (to))
8905 return 2;
8906 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
8907 return 2;
8908 else if (GR_REG_CLASS_P (from))
8909 {
8910 if (to == M16_REGS)
8911 return 2;
8912 else if (to == M16_NA_REGS)
8913 return 2;
8914 else if (GR_REG_CLASS_P (to))
8915 {
8916 if (TARGET_MIPS16)
8917 return 4;
8918 else
8919 return 2;
8920 }
8921 else if (to == FP_REGS)
8922 return 4;
8923 else if (to == HI_REG || to == LO_REG || to == MD_REGS)
8924 {
8925 if (TARGET_MIPS16)
8926 return 12;
8927 else
8928 return 6;
8929 }
8930 else if (COP_REG_CLASS_P (to))
8931 {
8932 return 5;
8933 }
8934 } /* GR_REG_CLASS_P (from) */
8935 else if (from == FP_REGS)
8936 {
8937 if (GR_REG_CLASS_P (to))
8938 return 4;
8939 else if (to == FP_REGS)
8940 return 2;
8941 else if (to == ST_REGS)
8942 return 8;
8943 } /* from == FP_REGS */
8944 else if (from == HI_REG || from == LO_REG || from == MD_REGS)
8945 {
8946 if (GR_REG_CLASS_P (to))
8947 {
8948 if (TARGET_MIPS16)
8949 return 12;
8950 else
8951 return 6;
8952 }
8953 } /* from == HI_REG, etc. */
8954 else if (from == ST_REGS && GR_REG_CLASS_P (to))
8955 return 4;
8956 else if (COP_REG_CLASS_P (from))
8957 {
8958 return 5;
8959 } /* COP_REG_CLASS_P (from) */
8960
8961 /* Fall through. */
8962
8963 return 12;
8964 }
8965
8966 /* Return the length of INSN. LENGTH is the initial length computed by
8967 attributes in the machine-description file. */
8968
8969 int
mips_adjust_insn_length(rtx insn,int length)8970 mips_adjust_insn_length (rtx insn, int length)
8971 {
8972 /* A unconditional jump has an unfilled delay slot if it is not part
8973 of a sequence. A conditional jump normally has a delay slot, but
8974 does not on MIPS16. */
8975 if (simplejump_p (insn)
8976 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
8977 || GET_CODE (insn) == CALL_INSN)))
8978 length += 4;
8979
8980 /* See how many nops might be needed to avoid hardware hazards. */
8981 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
8982 switch (get_attr_hazard (insn))
8983 {
8984 case HAZARD_NONE:
8985 break;
8986
8987 case HAZARD_DELAY:
8988 length += 4;
8989 break;
8990
8991 case HAZARD_HILO:
8992 length += 8;
8993 break;
8994 }
8995
8996 /* All MIPS16 instructions are a measly two bytes. */
8997 if (TARGET_MIPS16)
8998 length /= 2;
8999
9000 return length;
9001 }
9002
9003
9004 /* Return an asm sequence to start a noat block and load the address
9005 of a label into $1. */
9006
9007 const char *
mips_output_load_label(void)9008 mips_output_load_label (void)
9009 {
9010 if (TARGET_EXPLICIT_RELOCS)
9011 switch (mips_abi)
9012 {
9013 case ABI_N32:
9014 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9015
9016 case ABI_64:
9017 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9018
9019 default:
9020 if (ISA_HAS_LOAD_DELAY)
9021 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9022 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9023 }
9024 else
9025 {
9026 if (Pmode == DImode)
9027 return "%[dla\t%@,%0";
9028 else
9029 return "%[la\t%@,%0";
9030 }
9031 }
9032
9033
9034 /* Output assembly instructions to peform a conditional branch.
9035
9036 INSN is the branch instruction. OPERANDS[0] is the condition.
9037 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9038 of the first operand to the condition. If TWO_OPERANDS_P is
9039 nonzero the comparison takes two operands; OPERANDS[3] will be the
9040 second operand.
9041
9042 If INVERTED_P is nonzero we are to branch if the condition does
9043 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
9044
9045 LENGTH is the length (in bytes) of the sequence we are to generate.
9046 That tells us whether to generate a simple conditional branch, or a
9047 reversed conditional branch around a `jr' instruction. */
9048 const char *
mips_output_conditional_branch(rtx insn,rtx * operands,int two_operands_p,int float_p,int inverted_p,int length)9049 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
9050 int float_p, int inverted_p, int length)
9051 {
9052 static char buffer[200];
9053 /* The kind of comparison we are doing. */
9054 enum rtx_code code = GET_CODE (operands[0]);
9055 /* Nonzero if the opcode for the comparison needs a `z' indicating
9056 that it is a comparison against zero. */
9057 int need_z_p;
9058 /* A string to use in the assembly output to represent the first
9059 operand. */
9060 const char *op1 = "%z2";
9061 /* A string to use in the assembly output to represent the second
9062 operand. Use the hard-wired zero register if there's no second
9063 operand. */
9064 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9065 /* The operand-printing string for the comparison. */
9066 const char *const comp = (float_p ? "%F0" : "%C0");
9067 /* The operand-printing string for the inverted comparison. */
9068 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
9069
9070 /* The MIPS processors (for levels of the ISA at least two), have
9071 "likely" variants of each branch instruction. These instructions
9072 annul the instruction in the delay slot if the branch is not
9073 taken. */
9074 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9075
9076 if (!two_operands_p)
9077 {
9078 /* To compute whether than A > B, for example, we normally
9079 subtract B from A and then look at the sign bit. But, if we
9080 are doing an unsigned comparison, and B is zero, we don't
9081 have to do the subtraction. Instead, we can just check to
9082 see if A is nonzero. Thus, we change the CODE here to
9083 reflect the simpler comparison operation. */
9084 switch (code)
9085 {
9086 case GTU:
9087 code = NE;
9088 break;
9089
9090 case LEU:
9091 code = EQ;
9092 break;
9093
9094 case GEU:
9095 /* A condition which will always be true. */
9096 code = EQ;
9097 op1 = "%.";
9098 break;
9099
9100 case LTU:
9101 /* A condition which will always be false. */
9102 code = NE;
9103 op1 = "%.";
9104 break;
9105
9106 default:
9107 /* Not a special case. */
9108 break;
9109 }
9110 }
9111
9112 /* Relative comparisons are always done against zero. But
9113 equality comparisons are done between two operands, and therefore
9114 do not require a `z' in the assembly language output. */
9115 need_z_p = (!float_p && code != EQ && code != NE);
9116 /* For comparisons against zero, the zero is not provided
9117 explicitly. */
9118 if (need_z_p)
9119 op2 = "";
9120
9121 /* Begin by terminating the buffer. That way we can always use
9122 strcat to add to it. */
9123 buffer[0] = '\0';
9124
9125 switch (length)
9126 {
9127 case 4:
9128 case 8:
9129 /* Just a simple conditional branch. */
9130 if (float_p)
9131 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
9132 inverted_p ? inverted_comp : comp);
9133 else
9134 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
9135 inverted_p ? inverted_comp : comp,
9136 need_z_p ? "z" : "",
9137 op1,
9138 op2);
9139 return buffer;
9140
9141 case 12:
9142 case 16:
9143 case 24:
9144 case 28:
9145 {
9146 /* Generate a reversed conditional branch around ` j'
9147 instruction:
9148
9149 .set noreorder
9150 .set nomacro
9151 bc l
9152 delay_slot or #nop
9153 j target
9154 #nop
9155 l:
9156 .set macro
9157 .set reorder
9158
9159 If the original branch was a likely branch, the delay slot
9160 must be executed only if the branch is taken, so generate:
9161
9162 .set noreorder
9163 .set nomacro
9164 bc l
9165 #nop
9166 j target
9167 delay slot or #nop
9168 l:
9169 .set macro
9170 .set reorder
9171
9172 When generating non-embedded PIC, instead of:
9173
9174 j target
9175
9176 we emit:
9177
9178 .set noat
9179 la $at, target
9180 jr $at
9181 .set at
9182 */
9183
9184 rtx orig_target;
9185 rtx target = gen_label_rtx ();
9186
9187 orig_target = operands[1];
9188 operands[1] = target;
9189 /* Generate the reversed comparison. This takes four
9190 bytes. */
9191 if (float_p)
9192 sprintf (buffer, "%%*b%s\t%%Z2%%1",
9193 inverted_p ? comp : inverted_comp);
9194 else
9195 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
9196 inverted_p ? comp : inverted_comp,
9197 need_z_p ? "z" : "",
9198 op1,
9199 op2);
9200 output_asm_insn (buffer, operands);
9201
9202 if (length != 16 && length != 28 && ! mips_branch_likely)
9203 {
9204 /* Output delay slot instruction. */
9205 rtx insn = final_sequence;
9206 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9207 optimize, 0, 1, NULL);
9208 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9209 }
9210 else
9211 output_asm_insn ("%#", 0);
9212
9213 if (length <= 16)
9214 output_asm_insn ("j\t%0", &orig_target);
9215 else
9216 {
9217 output_asm_insn (mips_output_load_label (), &orig_target);
9218 output_asm_insn ("jr\t%@%]", 0);
9219 }
9220
9221 if (length != 16 && length != 28 && mips_branch_likely)
9222 {
9223 /* Output delay slot instruction. */
9224 rtx insn = final_sequence;
9225 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9226 optimize, 0, 1, NULL);
9227 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9228 }
9229 else
9230 output_asm_insn ("%#", 0);
9231
9232 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9233 CODE_LABEL_NUMBER (target));
9234
9235 return "";
9236 }
9237
9238 default:
9239 abort ();
9240 }
9241
9242 /* NOTREACHED */
9243 return 0;
9244 }
9245
9246 /* Used to output div or ddiv instruction DIVISION, which has the
9247 operands given by OPERANDS. If we need a divide-by-zero check,
9248 output the instruction and return an asm string that traps if
9249 operand 2 is zero. Otherwise just return DIVISION itself. */
9250
9251 const char *
mips_output_division(const char * division,rtx * operands)9252 mips_output_division (const char *division, rtx *operands)
9253 {
9254 if (TARGET_CHECK_ZERO_DIV)
9255 {
9256 output_asm_insn (division, operands);
9257
9258 if (TARGET_MIPS16)
9259 return "bnez\t%2,1f\n\tbreak\t7\n1:";
9260 else
9261 return "bne\t%2,%.,1f%#\n\tbreak\t7\n1:";
9262 }
9263 return division;
9264 }
9265
9266 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9267 with a final "000" replaced by "k". Ignore case.
9268
9269 Note: this function is shared between GCC and GAS. */
9270
9271 static bool
mips_strict_matching_cpu_name_p(const char * canonical,const char * given)9272 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9273 {
9274 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9275 given++, canonical++;
9276
9277 return ((*given == 0 && *canonical == 0)
9278 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9279 }
9280
9281
9282 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9283 CPU name. We've traditionally allowed a lot of variation here.
9284
9285 Note: this function is shared between GCC and GAS. */
9286
9287 static bool
mips_matching_cpu_name_p(const char * canonical,const char * given)9288 mips_matching_cpu_name_p (const char *canonical, const char *given)
9289 {
9290 /* First see if the name matches exactly, or with a final "000"
9291 turned into "k". */
9292 if (mips_strict_matching_cpu_name_p (canonical, given))
9293 return true;
9294
9295 /* If not, try comparing based on numerical designation alone.
9296 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9297 if (TOLOWER (*given) == 'r')
9298 given++;
9299 if (!ISDIGIT (*given))
9300 return false;
9301
9302 /* Skip over some well-known prefixes in the canonical name,
9303 hoping to find a number there too. */
9304 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9305 canonical += 2;
9306 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9307 canonical += 2;
9308 else if (TOLOWER (canonical[0]) == 'r')
9309 canonical += 1;
9310
9311 return mips_strict_matching_cpu_name_p (canonical, given);
9312 }
9313
9314
9315 /* Parse an option that takes the name of a processor as its argument.
9316 OPTION is the name of the option and CPU_STRING is the argument.
9317 Return the corresponding processor enumeration if the CPU_STRING is
9318 recognized, otherwise report an error and return null.
9319
9320 A similar function exists in GAS. */
9321
9322 static const struct mips_cpu_info *
mips_parse_cpu(const char * option,const char * cpu_string)9323 mips_parse_cpu (const char *option, const char *cpu_string)
9324 {
9325 const struct mips_cpu_info *p;
9326 const char *s;
9327
9328 /* In the past, we allowed upper-case CPU names, but it doesn't
9329 work well with the multilib machinery. */
9330 for (s = cpu_string; *s != 0; s++)
9331 if (ISUPPER (*s))
9332 {
9333 warning ("the cpu name must be lower case");
9334 break;
9335 }
9336
9337 /* 'from-abi' selects the most compatible architecture for the given
9338 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9339 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9340 version. Look first at the -mgp options, if given, otherwise base
9341 the choice on MASK_64BIT in TARGET_DEFAULT. */
9342 if (strcasecmp (cpu_string, "from-abi") == 0)
9343 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9344 : ABI_NEEDS_64BIT_REGS ? 3
9345 : (TARGET_64BIT ? 3 : 1));
9346
9347 /* 'default' has traditionally been a no-op. Probably not very useful. */
9348 if (strcasecmp (cpu_string, "default") == 0)
9349 return 0;
9350
9351 for (p = mips_cpu_info_table; p->name != 0; p++)
9352 if (mips_matching_cpu_name_p (p->name, cpu_string))
9353 return p;
9354
9355 error ("bad value (%s) for %s", cpu_string, option);
9356 return 0;
9357 }
9358
9359
9360 /* Return the processor associated with the given ISA level, or null
9361 if the ISA isn't valid. */
9362
9363 static const struct mips_cpu_info *
mips_cpu_info_from_isa(int isa)9364 mips_cpu_info_from_isa (int isa)
9365 {
9366 const struct mips_cpu_info *p;
9367
9368 for (p = mips_cpu_info_table; p->name != 0; p++)
9369 if (p->isa == isa)
9370 return p;
9371
9372 return 0;
9373 }
9374
9375 /* Adjust the cost of INSN based on the relationship between INSN that
9376 is dependent on DEP_INSN through the dependence LINK. The default
9377 is to make no adjustment to COST.
9378
9379 On the MIPS, ignore the cost of anti- and output-dependencies. */
9380 static int
mips_adjust_cost(rtx insn ATTRIBUTE_UNUSED,rtx link,rtx dep ATTRIBUTE_UNUSED,int cost)9381 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9382 rtx dep ATTRIBUTE_UNUSED, int cost)
9383 {
9384 if (REG_NOTE_KIND (link) != 0)
9385 return 0; /* Anti or output dependence. */
9386 return cost;
9387 }
9388
9389 /* Implement HARD_REGNO_NREGS. The size of FP registers are controlled
9390 by UNITS_PER_FPREG. All other registers are word sized. */
9391
9392 unsigned int
mips_hard_regno_nregs(int regno,enum machine_mode mode)9393 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9394 {
9395 if (! FP_REG_P (regno))
9396 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9397 else
9398 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9399 }
9400
9401 /* Implement RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9402 all BLKmode objects are returned in memory. Under the new (N32 and
9403 64-bit MIPS ABIs) small structures are returned in a register.
9404 Objects with varying size must still be returned in memory, of
9405 course. */
9406
9407 int
mips_return_in_memory(tree type)9408 mips_return_in_memory (tree type)
9409 {
9410 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
9411 return (TYPE_MODE (type) == BLKmode);
9412 else
9413 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9414 || (int_size_in_bytes (type) == -1));
9415 }
9416
9417 static int
mips_issue_rate(void)9418 mips_issue_rate (void)
9419 {
9420 switch (mips_tune)
9421 {
9422 case PROCESSOR_R5400:
9423 case PROCESSOR_R5500:
9424 case PROCESSOR_R7000:
9425 case PROCESSOR_R9000:
9426 return 2;
9427
9428 default:
9429 return 1;
9430 }
9431
9432 abort ();
9433
9434 }
9435
9436 /* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
9437 processors that have a DFA pipeline description. */
9438
9439 static int
mips_use_dfa_pipeline_interface(void)9440 mips_use_dfa_pipeline_interface (void)
9441 {
9442 switch (mips_tune)
9443 {
9444 case PROCESSOR_R5400:
9445 case PROCESSOR_R5500:
9446 case PROCESSOR_R7000:
9447 case PROCESSOR_R9000:
9448 case PROCESSOR_SR71000:
9449 return true;
9450
9451 default:
9452 return false;
9453 }
9454 }
9455
9456
9457 const char *
mips_emit_prefetch(rtx * operands)9458 mips_emit_prefetch (rtx *operands)
9459 {
9460 int write = INTVAL (operands[1]);
9461 int locality = INTVAL (operands[2]);
9462 int indexed = GET_CODE (operands[3]) == REG;
9463 int code;
9464 char buffer[30];
9465
9466 if (locality <= 0)
9467 code = (write ? 5 : 4); /* store_streamed / load_streamed. */
9468 else if (locality <= 2)
9469 code = (write ? 1 : 0); /* store / load. */
9470 else
9471 code = (write ? 7 : 6); /* store_retained / load_retained. */
9472
9473 sprintf (buffer, "%s\t%d,%%3(%%0)", indexed ? "prefx" : "pref", code);
9474 output_asm_insn (buffer, operands);
9475 return "";
9476 }
9477
9478
9479
9480 #if TARGET_IRIX
9481 /* Output assembly to switch to section NAME with attribute FLAGS. */
9482
9483 static void
irix_asm_named_section_1(const char * name,unsigned int flags,unsigned int align)9484 irix_asm_named_section_1 (const char *name, unsigned int flags,
9485 unsigned int align)
9486 {
9487 unsigned int sh_type, sh_flags, sh_entsize;
9488
9489 sh_flags = 0;
9490 if (!(flags & SECTION_DEBUG))
9491 sh_flags |= 2; /* SHF_ALLOC */
9492 if (flags & SECTION_WRITE)
9493 sh_flags |= 1; /* SHF_WRITE */
9494 if (flags & SECTION_CODE)
9495 sh_flags |= 4; /* SHF_EXECINSTR */
9496 if (flags & SECTION_SMALL)
9497 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
9498 if (strcmp (name, ".debug_frame") == 0)
9499 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
9500 if (flags & SECTION_DEBUG)
9501 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
9502 else if (flags & SECTION_BSS)
9503 sh_type = 8; /* SHT_NOBITS */
9504 else
9505 sh_type = 1; /* SHT_PROGBITS */
9506
9507 if (flags & SECTION_CODE)
9508 sh_entsize = 4;
9509 else
9510 sh_entsize = 0;
9511
9512 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
9513 name, sh_type, sh_flags, sh_entsize, align);
9514 }
9515
9516 static void
irix_asm_named_section(const char * name,unsigned int flags)9517 irix_asm_named_section (const char *name, unsigned int flags)
9518 {
9519 if (TARGET_SGI_O32_AS)
9520 default_no_named_section (name, flags);
9521 else if (mips_abi == ABI_32 && TARGET_GAS)
9522 default_elf_asm_named_section (name, flags);
9523 else
9524 irix_asm_named_section_1 (name, flags, 0);
9525 }
9526
9527 /* In addition to emitting a .align directive, record the maximum
9528 alignment requested for the current section. */
9529
9530 struct GTY (()) irix_section_align_entry
9531 {
9532 const char *name;
9533 unsigned int log;
9534 unsigned int flags;
9535 };
9536
9537 static htab_t irix_section_align_htab;
9538 static FILE *irix_orig_asm_out_file;
9539
9540 static int
irix_section_align_entry_eq(const void * p1,const void * p2)9541 irix_section_align_entry_eq (const void *p1, const void *p2)
9542 {
9543 const struct irix_section_align_entry *old = p1;
9544 const char *new = p2;
9545
9546 return strcmp (old->name, new) == 0;
9547 }
9548
9549 static hashval_t
irix_section_align_entry_hash(const void * p)9550 irix_section_align_entry_hash (const void *p)
9551 {
9552 const struct irix_section_align_entry *old = p;
9553 return htab_hash_string (old->name);
9554 }
9555
9556 void
irix_asm_output_align(FILE * file,unsigned int log)9557 irix_asm_output_align (FILE *file, unsigned int log)
9558 {
9559 const char *section = current_section_name ();
9560 struct irix_section_align_entry **slot, *entry;
9561
9562 if (mips_abi != ABI_32)
9563 {
9564 if (! section)
9565 abort ();
9566
9567 slot = (struct irix_section_align_entry **)
9568 htab_find_slot_with_hash (irix_section_align_htab, section,
9569 htab_hash_string (section), INSERT);
9570 entry = *slot;
9571 if (! entry)
9572 {
9573 entry = (struct irix_section_align_entry *)
9574 xmalloc (sizeof (struct irix_section_align_entry));
9575 *slot = entry;
9576 entry->name = section;
9577 entry->log = log;
9578 entry->flags = current_section_flags ();
9579 }
9580 else if (entry->log < log)
9581 entry->log = log;
9582 }
9583
9584 fprintf (file, "\t.align\t%u\n", log);
9585 }
9586
9587 /* The IRIX assembler does not record alignment from .align directives,
9588 but takes it from the first .section directive seen. Play file
9589 switching games so that we can emit a .section directive at the
9590 beginning of the file with the proper alignment attached. */
9591
9592 static void
irix_file_start(void)9593 irix_file_start (void)
9594 {
9595 mips_file_start ();
9596
9597 if (mips_abi == ABI_32)
9598 return;
9599
9600 irix_orig_asm_out_file = asm_out_file;
9601 asm_out_file = tmpfile ();
9602
9603 irix_section_align_htab = htab_create (31, irix_section_align_entry_hash,
9604 irix_section_align_entry_eq, NULL);
9605 }
9606
9607 static int
irix_section_align_1(void ** slot,void * data ATTRIBUTE_UNUSED)9608 irix_section_align_1 (void **slot, void *data ATTRIBUTE_UNUSED)
9609 {
9610 const struct irix_section_align_entry *entry
9611 = *(const struct irix_section_align_entry **) slot;
9612
9613 irix_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
9614 return 1;
9615 }
9616
9617 static void
copy_file_data(FILE * to,FILE * from)9618 copy_file_data (FILE *to, FILE *from)
9619 {
9620 char buffer[8192];
9621 size_t len;
9622 rewind (from);
9623 if (ferror (from))
9624 fatal_error ("can't rewind temp file: %m");
9625
9626 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
9627 if (fwrite (buffer, 1, len, to) != len)
9628 fatal_error ("can't write to output file: %m");
9629
9630 if (ferror (from))
9631 fatal_error ("can't read from temp file: %m");
9632
9633 if (fclose (from))
9634 fatal_error ("can't close temp file: %m");
9635 }
9636
9637 static void
irix_file_end(void)9638 irix_file_end (void)
9639 {
9640 if (mips_abi != ABI_32)
9641 {
9642 /* Emit section directives with the proper alignment at the top of the
9643 real output file. */
9644 FILE *temp = asm_out_file;
9645 asm_out_file = irix_orig_asm_out_file;
9646 htab_traverse (irix_section_align_htab, irix_section_align_1, NULL);
9647
9648 /* Copy the data emitted to the temp file to the real output file. */
9649 copy_file_data (asm_out_file, temp);
9650 }
9651
9652 mips_file_end ();
9653 }
9654
9655
9656 /* Implement TARGET_SECTION_TYPE_FLAGS. Make sure that .sdata and
9657 .sbss sections get the SECTION_SMALL flag: this isn't set by the
9658 default code. */
9659
9660 static unsigned int
irix_section_type_flags(tree decl,const char * section,int relocs_p)9661 irix_section_type_flags (tree decl, const char *section, int relocs_p)
9662 {
9663 unsigned int flags;
9664
9665 flags = default_section_type_flags (decl, section, relocs_p);
9666
9667 if (strcmp (section, ".sdata") == 0
9668 || strcmp (section, ".sbss") == 0
9669 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9670 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9671 flags |= SECTION_SMALL;
9672
9673 return flags;
9674 }
9675
9676 #endif /* TARGET_IRIX */
9677
9678 #include "gt-mips.h"
9679