1 /* This file is part of the program psim. 2 3 Copyright 1994, 1995, 2002 Andrew Cagney <cagney@highland.com.au> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 19 */ 20 21 22 #ifndef _PSIM_CONFIG_H_ 23 #define _PSIM_CONFIG_H_ 24 25 26 /* endianness of the host/target: 27 28 If the build process is aware (at compile time) of the endianness 29 of the host/target it is able to eliminate slower generic endian 30 handling code. 31 32 Possible values are 0 (unknown), LITTLE_ENDIAN, BIG_ENDIAN */ 33 34 #ifndef WITH_HOST_BYTE_ORDER 35 #define WITH_HOST_BYTE_ORDER 0 /*unknown*/ 36 #endif 37 38 #ifndef WITH_TARGET_BYTE_ORDER 39 #define WITH_TARGET_BYTE_ORDER 0 /*unknown*/ 40 #endif 41 42 extern int current_host_byte_order; 43 #define CURRENT_HOST_BYTE_ORDER (WITH_HOST_BYTE_ORDER \ 44 ? WITH_HOST_BYTE_ORDER \ 45 : current_host_byte_order) 46 extern int current_target_byte_order; 47 #define CURRENT_TARGET_BYTE_ORDER (WITH_TARGET_BYTE_ORDER \ 48 ? WITH_TARGET_BYTE_ORDER \ 49 : current_target_byte_order) 50 51 52 /* PowerPC XOR endian. 53 54 In addition to the above, the simulator can support the PowerPC's 55 horrible XOR endian mode. This feature makes it possible to 56 control the endian mode of a processor using the MSR. */ 57 58 #ifndef WITH_XOR_ENDIAN 59 #define WITH_XOR_ENDIAN 8 60 #endif 61 62 63 /* Intel host BSWAP support: 64 65 Whether to use bswap on the 486 and pentiums rather than the 386 66 sequence that uses xchgb/rorl/xchgb */ 67 #ifndef WITH_BSWAP 68 #define WITH_BSWAP 0 69 #endif 70 71 72 /* SMP support: 73 74 Sets a limit on the number of processors that can be simulated. If 75 WITH_SMP is set to zero (0), the simulator is restricted to 76 suporting only on processor (and as a consequence leaves the SMP 77 code out of the build process). 78 79 The actual number of processors is taken from the device 80 /options/smp@<nr-cpu> */ 81 82 #ifndef WITH_SMP 83 #define WITH_SMP 5 84 #endif 85 #if WITH_SMP 86 #define MAX_NR_PROCESSORS WITH_SMP 87 #else 88 #define MAX_NR_PROCESSORS 1 89 #endif 90 91 92 /* Word size of host/target: 93 94 Set these according to your host and target requirements. At this 95 point in time, I've only compiled (not run) for a 64bit and never 96 built for a 64bit host. This will always remain a compile time 97 option */ 98 99 #ifndef WITH_TARGET_WORD_BITSIZE 100 #define WITH_TARGET_WORD_BITSIZE 32 /* compiled only */ 101 #endif 102 103 #ifndef WITH_HOST_WORD_BITSIZE 104 #define WITH_HOST_WORD_BITSIZE 32 /* 64bit ready? */ 105 #endif 106 107 108 /* Program environment: 109 110 Three environments are available - UEA (user), VEA (virtual) and 111 OEA (perating). The former two are environment that users would 112 expect to see (VEA includes things like coherency and the time 113 base) while OEA is what an operating system expects to see. By 114 setting these to specific values, the build process is able to 115 eliminate non relevent environment code 116 117 CURRENT_ENVIRONMENT specifies which of vea or oea is required for 118 the current runtime. */ 119 120 #define USER_ENVIRONMENT 1 121 #define VIRTUAL_ENVIRONMENT 2 122 #define OPERATING_ENVIRONMENT 3 123 124 #ifndef WITH_ENVIRONMENT 125 #define WITH_ENVIRONMENT 0 126 #endif 127 128 extern int current_environment; 129 #define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \ 130 ? WITH_ENVIRONMENT \ 131 : current_environment) 132 133 134 /* Optional VEA/OEA code: 135 136 The below, required for the OEA model may also be included in the 137 VEA model however, as far as I can tell only make things 138 slower... */ 139 140 141 /* Events. Devices modeling real H/W need to be able to efficiently 142 schedule things to do at known times in the future. The event 143 queue implements this. Unfortunatly this adds the need to check 144 for any events once each full instruction cycle. */ 145 146 #define WITH_EVENTS (WITH_ENVIRONMENT != USER_ENVIRONMENT) 147 148 149 /* Time base: 150 151 The PowerPC architecture includes the addition of both a time base 152 register and a decrement timer. Like events adds to the overhead 153 of of some instruction cycles. */ 154 155 #ifndef WITH_TIME_BASE 156 #define WITH_TIME_BASE (WITH_ENVIRONMENT != USER_ENVIRONMENT) 157 #endif 158 159 160 /* Callback/Default Memory. 161 162 Core includes a builtin memory type (raw_memory) that is 163 implemented using an array. raw_memory does not require any 164 additional functions etc. 165 166 Callback memory is where the core calls a core device for the data 167 it requires. 168 169 Default memory is an extenstion of this where for addresses that do 170 not map into either a callback or core memory range a default map 171 can be used. 172 173 The OEA model uses callback memory for devices and default memory 174 for buses. 175 176 The VEA model uses callback memory to capture `page faults'. 177 178 While it may be possible to eliminate callback/default memory (and 179 hence also eliminate an additional test per memory fetch) it 180 probably is not worth the effort. 181 182 BTW, while raw_memory could have been implemented as a callback, 183 profiling has shown that there is a biger win (at least for the 184 x86) in eliminating a function call for the most common 185 (raw_memory) case. */ 186 187 #define WITH_CALLBACK_MEMORY 1 188 189 190 /* Alignment: 191 192 The PowerPC may or may not handle miss aligned transfers. An 193 implementation normally handles miss aligned transfers in big 194 endian mode but generates an exception in little endian mode. 195 196 This model. Instead allows both little and big endian modes to 197 either take exceptions or handle miss aligned transfers. 198 199 If 0 is specified then for big-endian mode miss alligned accesses 200 are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the 201 processor will fault on them (STRICT_ALIGNMENT). */ 202 203 #define NONSTRICT_ALIGNMENT 1 204 #define STRICT_ALIGNMENT 2 205 206 #ifndef WITH_ALIGNMENT 207 #define WITH_ALIGNMENT 0 208 #endif 209 210 extern int current_alignment; 211 #define CURRENT_ALIGNMENT (WITH_ALIGNMENT \ 212 ? WITH_ALIGNMENT \ 213 : current_alignment) 214 215 216 /* Floating point suport: 217 218 Still under development. */ 219 220 #define SOFT_FLOATING_POINT 1 221 #define HARD_FLOATING_POINT 2 222 223 #ifndef WITH_FLOATING_POINT 224 #define WITH_FLOATING_POINT HARD_FLOATING_POINT 225 #endif 226 extern int current_floating_point; 227 #define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \ 228 ? WITH_FLOATING_POINT \ 229 : current_floating_point) 230 231 232 /* Debugging: 233 234 Control the inclusion of debugging code. */ 235 236 /* Include the tracing code. Disabling this eliminates all tracing 237 code */ 238 239 #ifndef WITH_TRACE 240 #define WITH_TRACE 1 241 #endif 242 243 /* include code that checks assertions scattered through out the 244 program */ 245 246 #ifndef WITH_ASSERT 247 #define WITH_ASSERT 1 248 #endif 249 250 /* Whether to check instructions for reserved bits being set */ 251 252 #ifndef WITH_RESERVED_BITS 253 #define WITH_RESERVED_BITS 1 254 #endif 255 256 /* include monitoring code */ 257 258 #define MONITOR_INSTRUCTION_ISSUE 1 259 #define MONITOR_LOAD_STORE_UNIT 2 260 #ifndef WITH_MON 261 #define WITH_MON (MONITOR_LOAD_STORE_UNIT \ 262 | MONITOR_INSTRUCTION_ISSUE) 263 #endif 264 265 /* Current CPU model (models are in the generated models.h include file) */ 266 #ifndef WITH_MODEL 267 #define WITH_MODEL 0 268 #endif 269 270 #define CURRENT_MODEL (WITH_MODEL \ 271 ? WITH_MODEL \ 272 : current_model) 273 274 #ifndef WITH_DEFAULT_MODEL 275 #define WITH_DEFAULT_MODEL DEFAULT_MODEL 276 #endif 277 278 #define MODEL_ISSUE_IGNORE (-1) 279 #define MODEL_ISSUE_PROCESS 1 280 281 #ifndef WITH_MODEL_ISSUE 282 #define WITH_MODEL_ISSUE 0 283 #endif 284 285 extern int current_model_issue; 286 #define CURRENT_MODEL_ISSUE (WITH_MODEL_ISSUE \ 287 ? WITH_MODEL_ISSUE \ 288 : current_model_issue) 289 290 /* Whether or not input/output just uses stdio, or uses printf_filtered for 291 output, and polling input for input. */ 292 293 #define DONT_USE_STDIO 2 294 #define DO_USE_STDIO 1 295 296 #ifndef WITH_STDIO 297 #define WITH_STDIO 0 298 #endif 299 300 extern int current_stdio; 301 #define CURRENT_STDIO (WITH_STDIO \ 302 ? WITH_STDIO \ 303 : current_stdio) 304 305 306 307 /* INLINE CODE SELECTION: 308 309 GCC -O3 attempts to inline any function or procedure in scope. The 310 options below facilitate fine grained control over what is and what 311 isn't made inline. For instance it can control things down to a 312 specific modules static routines. Doing this allows the compiler 313 to both eliminate the overhead of function calls and (as a 314 consequence) also eliminate further dead code. 315 316 On a CISC (x86) I've found that I can achieve an order of magintude 317 speed improvement (x3-x5). In the case of RISC (sparc) while the 318 performance gain isn't as great it is still significant. 319 320 Each module is controled by the macro <module>_INLINE which can 321 have the values described below 322 323 0 Do not inline any thing for the given module 324 325 The following additional values are `bit fields' and can be 326 combined. 327 328 REVEAL_MODULE: 329 330 Include the C file for the module into the file being compiled 331 but do not make the functions within the module inline. 332 333 While of no apparent benefit, this makes it possible for the 334 included module, when compiled to inline its calls to what 335 would otherwize be external functions. 336 337 INLINE_MODULE: 338 339 Make external functions within the module `inline'. Thus if 340 the module is included into a file being compiled, calls to 341 its funtions can be eliminated. 2 implies 1. 342 343 PSIM_INLINE_LOCALS: 344 345 Make internal (static) functions within the module `inline'. 346 347 The following abreviations are available: 348 349 INCLUDE_MODULE == (REVEAL_MODULE | INLINE_MODULE) 350 351 ALL_INLINE == (REVEAL_MODULE | INLINE_MODULE | PSIM_INLINE_LOCALS) 352 353 In addition to this, modules have been put into two categories. 354 355 Simple modules - eg sim-endian.h bits.h 356 357 Because these modules are small and simple and do not have 358 any complex interpendencies they are configured, if 359 <module>_INLINE is so enabled, to inline themselves in all 360 modules that include those files. 361 362 For the default build, this is a real win as all byte 363 conversion and bit manipulation functions are inlined. 364 365 Complex modules - the rest 366 367 These are all handled using the files inline.h and inline.c. 368 psim.c includes the above which in turn include any remaining 369 code. 370 371 IMPLEMENTATION: 372 373 The inline ability is enabled by prefixing every data / function 374 declaration and definition with one of the following: 375 376 377 INLINE_<module> 378 379 Prefix to any global function that is a candidate for being 380 inline. 381 382 values - `', `static', `static INLINE' 383 384 385 EXTERN_<module> 386 387 Prefix to any global data structures for the module. Global 388 functions that are not to be inlined shall also be prefixed 389 with this. 390 391 values - `', `static', `static' 392 393 394 STATIC_INLINE_<module> 395 396 Prefix to any local (static) function that is a candidate for 397 being made inline. 398 399 values - `static', `static INLINE' 400 401 402 static 403 404 Prefix all local data structures. Local functions that are not 405 to be inlined shall also be prefixed with this. 406 407 values - `static', `static' 408 409 nb: will not work for modules that are being inlined for every 410 use (white lie). 411 412 413 extern 414 #ifndef _INLINE_C_ 415 #endif 416 417 Prefix to any declaration of a global object (function or 418 variable) that should not be inlined and should have only one 419 definition. The #ifndef wrapper goes around the definition 420 propper to ensure that only one copy is generated. 421 422 nb: this will not work when a module is being inlined for every 423 use. 424 425 426 STATIC_<module> 427 428 Replaced by either `static' or `EXTERN_MODULE'. 429 430 431 REALITY CHECK: 432 433 This is not for the faint hearted. I've seen GCC get up to 500mb 434 trying to compile what this can create. 435 436 Some of the modules do not yet implement the WITH_INLINE_STATIC 437 option. Instead they use the macro STATIC_INLINE to control their 438 local function. 439 440 Because of the way that GCC parses __attribute__(), the macro's 441 need to be adjacent to the function name rather than at the start 442 of the line vis: 443 444 int STATIC_INLINE_MODULE f(void); 445 void INLINE_MODULE *g(void); 446 447 */ 448 449 #define REVEAL_MODULE 1 450 #define INLINE_MODULE 2 451 #define INCLUDE_MODULE (INLINE_MODULE | REVEAL_MODULE) 452 #define PSIM_INLINE_LOCALS 4 453 #define ALL_INLINE 7 454 455 /* Your compilers inline reserved word */ 456 457 #ifndef INLINE 458 #if defined(__GNUC__) && defined(__OPTIMIZE__) 459 #define INLINE __inline__ 460 #else 461 #define INLINE /*inline*/ 462 #endif 463 #endif 464 465 466 /* Your compilers pass parameters in registers reserved word */ 467 468 #ifndef WITH_REGPARM 469 #define WITH_REGPARM 0 470 #endif 471 472 /* Your compilers use an alternative calling sequence reserved word */ 473 474 #ifndef WITH_STDCALL 475 #define WITH_STDCALL 0 476 #endif 477 478 #if !defined REGPARM 479 #if defined(__GNUC__) && (defined(__i386__) || defined(__i486__) || defined(__i586__) || defined(__i686__)) 480 #if (WITH_REGPARM && WITH_STDCALL) 481 #define REGPARM __attribute__((__regparm__(WITH_REGPARM),__stdcall__)) 482 #else 483 #if (WITH_REGPARM && !WITH_STDCALL) 484 #define REGPARM __attribute__((__regparm__(WITH_REGPARM))) 485 #else 486 #if (!WITH_REGPARM && WITH_STDCALL) 487 #define REGPARM __attribute__((__stdcall__)) 488 #endif 489 #endif 490 #endif 491 #endif 492 #endif 493 494 #if !defined REGPARM 495 #define REGPARM 496 #endif 497 498 499 500 /* Default prefix for static functions */ 501 502 #ifndef STATIC_INLINE 503 #define STATIC_INLINE static INLINE 504 #endif 505 506 /* Default macro to simplify control several of key the inlines */ 507 508 #ifndef DEFAULT_INLINE 509 #define DEFAULT_INLINE PSIM_INLINE_LOCALS 510 #endif 511 512 /* Code that converts between hosts and target byte order. Used on 513 every memory access (instruction and data). See sim-endian.h for 514 additional byte swapping configuration information. This module 515 can inline for all callers */ 516 517 #ifndef SIM_ENDIAN_INLINE 518 #define SIM_ENDIAN_INLINE (DEFAULT_INLINE ? ALL_INLINE : 0) 519 #endif 520 521 /* Low level bit manipulation routines. This module can inline for all 522 callers */ 523 524 #ifndef BITS_INLINE 525 #define BITS_INLINE (DEFAULT_INLINE ? ALL_INLINE : 0) 526 #endif 527 528 /* Code that gives access to various CPU internals such as registers. 529 Used every time an instruction is executed */ 530 531 #ifndef CPU_INLINE 532 #define CPU_INLINE (DEFAULT_INLINE ? ALL_INLINE : 0) 533 #endif 534 535 /* Code that translates between an effective and real address. Used 536 by every load or store. */ 537 538 #ifndef VM_INLINE 539 #define VM_INLINE DEFAULT_INLINE 540 #endif 541 542 /* Code that loads/stores data to/from the memory data structure. 543 Used by every load or store */ 544 545 #ifndef CORE_INLINE 546 #define CORE_INLINE DEFAULT_INLINE 547 #endif 548 549 /* Code to check for and process any events scheduled in the future. 550 Called once per instruction cycle */ 551 552 #ifndef EVENTS_INLINE 553 #define EVENTS_INLINE (DEFAULT_INLINE ? ALL_INLINE : 0) 554 #endif 555 556 /* Code monotoring the processors performance. It counts events on 557 every instruction cycle */ 558 559 #ifndef MON_INLINE 560 #define MON_INLINE (DEFAULT_INLINE ? ALL_INLINE : 0) 561 #endif 562 563 /* Code called on the rare occasions that an interrupt occures. */ 564 565 #ifndef INTERRUPTS_INLINE 566 #define INTERRUPTS_INLINE DEFAULT_INLINE 567 #endif 568 569 /* Code called on the rare occasion that either gdb or the device tree 570 need to manipulate a register within a processor */ 571 572 #ifndef REGISTERS_INLINE 573 #define REGISTERS_INLINE DEFAULT_INLINE 574 #endif 575 576 /* Code called on the rare occasion that a processor is manipulating 577 real hardware instead of RAM. 578 579 Also, most of the functions in devices.c are always called through 580 a jump table. */ 581 582 #ifndef DEVICE_INLINE 583 #define DEVICE_INLINE (DEFAULT_INLINE ? PSIM_INLINE_LOCALS : 0) 584 #endif 585 586 /* Code called used while the device tree is being built. 587 588 Inlining this is of no benefit */ 589 590 #ifndef TREE_INLINE 591 #define TREE_INLINE (DEFAULT_INLINE ? PSIM_INLINE_LOCALS : 0) 592 #endif 593 594 /* Code called whenever information on a Special Purpose Register is 595 required. Called by the mflr/mtlr pseudo instructions */ 596 597 #ifndef SPREG_INLINE 598 #define SPREG_INLINE DEFAULT_INLINE 599 #endif 600 601 /* Functions modeling the semantics of each instruction. Two cases to 602 consider, firstly of idecode is implemented with a switch then this 603 allows the idecode function to inline each semantic function 604 (avoiding a call). The second case is when idecode is using a 605 table, even then while the semantic functions can't be inlined, 606 setting it to one still enables each semantic function to inline 607 anything they call (if that code is marked for being inlined). 608 609 WARNING: you need lots (like 200mb of swap) of swap. Setting this 610 to 1 is useful when using a table as it enables the sematic code to 611 inline all of their called functions */ 612 613 #ifndef SEMANTICS_INLINE 614 #define SEMANTICS_INLINE (DEFAULT_INLINE & ~INLINE_MODULE) 615 #endif 616 617 /* When using the instruction cache, code to decode an instruction and 618 install it into the cache. Normally called when ever there is a 619 miss in the instruction cache. */ 620 621 #ifndef ICACHE_INLINE 622 #define ICACHE_INLINE (DEFAULT_INLINE & ~INLINE_MODULE) 623 #endif 624 625 /* General functions called by semantics functions but part of the 626 instruction table. Although called by the semantic functions the 627 frequency of calls is low. Consequently the need to inline this 628 code is reduced. */ 629 630 #ifndef SUPPORT_INLINE 631 #define SUPPORT_INLINE PSIM_INLINE_LOCALS 632 #endif 633 634 /* Model specific code used in simulating functional units. Note, it actaully 635 pays NOT to inline the PowerPC model functions (at least on the x86). This 636 is because if it is inlined, each PowerPC instruction gets a separate copy 637 of the code, which is not friendly to the cache. */ 638 639 #ifndef MODEL_INLINE 640 #define MODEL_INLINE (DEFAULT_INLINE & ~INLINE_MODULE) 641 #endif 642 643 /* Code to print out what options we were compiled with. Because this 644 is called at process startup, it doesn't have to be inlined, but 645 if it isn't brought in and the model routines are inline, the model 646 routines will be pulled in twice. */ 647 648 #ifndef OPTIONS_INLINE 649 #define OPTIONS_INLINE MODEL_INLINE 650 #endif 651 652 /* idecode acts as the hub of the system, everything else is imported 653 into this file */ 654 655 #ifndef IDECOCE_INLINE 656 #define IDECODE_INLINE PSIM_INLINE_LOCALS 657 #endif 658 659 /* psim, isn't actually inlined */ 660 661 #ifndef PSIM_INLINE 662 #define PSIM_INLINE PSIM_INLINE_LOCALS 663 #endif 664 665 /* Code to emulate os or rom compatibility. This code is called via a 666 table and hence there is little benefit in making it inline */ 667 668 #ifndef OS_EMUL_INLINE 669 #define OS_EMUL_INLINE 0 670 #endif 671 672 #endif /* _PSIM_CONFIG_H */ 673