1# sh testcase for ldrc, strc 2# mach: shdsp 3# as(shdsp): -defsym sim_cpu=1 -dsp 4 5 .include "testutils.inc" 6 7 start 8 9setrc_imm: 10 set_grs_a5a5 11 # Test setrc 12 # 13 ldrs lstart 14 ldre lend 15 setrc #0xff 16 get_sr r1 17 shlr16 r1 18 set_greg 0xfff, r0 19 and r0, r1 20 assertreg 0xff, r1 21 22 stc rs, r0 ! rs unchanged 23 assertreg0 lstart 24 stc re, r0 ! re unchanged 25 assertreg0 lend 26 27 set_greg 0xa5a5a5a5, r0 28 set_greg 0xa5a5a5a5, r1 29 30 test_grs_a5a5 31 32setrc_reg: 33 set_grs_a5a5 34 # Test setrc 35 # 36 ldrs lstart 37 ldre lend 38 set_greg 0xfff, r0 39 setrc r0 40 get_sr r1 41 shlr16 r1 42 set_greg 0xfff, r0 43 and r0, r1 44 assertreg 0xfff, r1 45 46 stc rs, r0 ! rs unchanged 47 assertreg0 lstart 48 stc re, r0 ! re unchanged 49 assertreg0 lend 50 51 set_greg 0xa5a5a5a5, r0 52 set_greg 0xa5a5a5a5, r1 53 54 test_grs_a5a5 55 56 bra ldrc_imm 57 58 .global lstart 59 .align 2 60lstart: nop 61 nop 62 nop 63 nop 64 .global lend 65 .align 2 66lend: nop 67 nop 68 nop 69 nop 70 71ldrc_imm: 72 set_grs_a5a5 73 # Test ldrc 74 setrc #0x0 ! zero rc 75 ldrc #0xa5 76 get_sr r1 77 shlr16 r1 78 set_greg 0xfff, r0 79 and r0, r1 80 assertreg 0xa5, r1 81 stc rs, r0 ! rs unchanged 82 assertreg0 lstart 83 stc re, r0 84 assertreg0 lend+1 ! bit 0 set in re 85 86 # fix up re for next test 87 dt r0 ! Ugh! No DEC insn! 88 ldc r0, re 89 90 set_greg 0xa5a5a5a5, r0 91 set_greg 0xa5a5a5a5, r1 92 93 test_grs_a5a5 94 95ldrc_reg: 96 set_grs_a5a5 97 # Test ldrc 98 setrc #0x0 ! zero rc 99 set_greg 0xa5a, r0 100 ldrc r0 101 get_sr r1 102 shlr16 r1 103 set_greg 0xfff, r0 104 and r0, r1 105 assertreg 0xa5a, r1 106 stc rs, r0 ! rs unchanged 107 assertreg0 lstart 108 stc re, r0 109 assertreg0 lend+1 ! bit 0 set in re 110 111 set_greg 0xa5a5a5a5, r0 112 set_greg 0xa5a5a5a5, r1 113 114 test_grs_a5a5 115 116 pass 117 exit 0 118 119