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README.i860H A D11-Oct-20121.5 KiB3526

bitwise.dH A D11-Oct-20125.2 KiB142138

bitwise.sH A D11-Oct-20122.7 KiB151136

branch.dH A D11-Oct-20122.7 KiB8278

branch.sH A D11-Oct-2012846 8672

bte.dH A D11-Oct-20123.1 KiB6358

bte.sH A D11-Oct-20121.1 KiB5650

dir-align01.dH A D11-Oct-2012424 1814

dir-align01.sH A D11-Oct-2012260 129

dir-intel01.dH A D11-Oct-2012499 2016

dir-intel01.sH A D11-Oct-2012331 2013

dir-intel02.dH A D11-Oct-2012358 1612

dir-intel02.sH A D11-Oct-2012201 147

dir-intel03-err.lH A D11-Oct-2012310 65

dir-intel03-err.sH A D11-Oct-2012235 1510

dual01.dH A D11-Oct-2012570 2218

dual01.sH A D11-Oct-2012378 1816

dual02-err.lH A D11-Oct-201274 32

dual02-err.sH A D11-Oct-2012187 107

dual03.dH A D11-Oct-20121.7 KiB5446

dual03.sH A D11-Oct-2012836 4740

fldst01.dH A D11-Oct-20122.8 KiB7470

fldst01.sH A D11-Oct-20121.6 KiB7670

fldst02.dH A D11-Oct-20122.9 KiB7470

fldst02.sH A D11-Oct-20121.6 KiB7670

fldst03.dH A D11-Oct-20122.9 KiB7470

fldst03.sH A D11-Oct-20121.6 KiB7670

fldst04.dH A D11-Oct-20122.8 KiB7470

fldst04.sH A D11-Oct-20121.6 KiB7670

fldst05.dH A D11-Oct-20122.9 KiB7470

fldst05.sH A D11-Oct-20121.6 KiB7670

fldst06.dH A D11-Oct-20122.9 KiB7470

fldst06.sH A D11-Oct-20121.6 KiB7670

fldst07.dH A D11-Oct-20122.9 KiB7470

fldst07.sH A D11-Oct-20121.7 KiB7670

fldst08.dH A D11-Oct-20122.9 KiB7470

fldst08.sH A D11-Oct-20121.7 KiB7670

float01.dH A D11-Oct-20122.5 KiB7066

float01.sH A D11-Oct-20121.2 KiB8566

float02.dH A D11-Oct-20121.2 KiB4036

float02.sH A D11-Oct-2012517 4334

float03.dH A D11-Oct-20121.7 KiB5248

float03.sH A D11-Oct-2012860 6548

float04.dH A D11-Oct-20121.3 KiB4036

float04.sH A D11-Oct-2012726 5037

form.dH A D11-Oct-20121.9 KiB6460

form.sH A D11-Oct-2012812 6760

i860.expH A D11-Oct-20121.5 KiB5954

iarith.dH A D11-Oct-20123.4 KiB9894

iarith.sH A D11-Oct-20121.8 KiB10392

ldst01.dH A D11-Oct-20121.3 KiB4036

ldst01.sH A D11-Oct-2012668 3632

ldst02.dH A D11-Oct-20121.3 KiB4036

ldst02.sH A D11-Oct-2012668 3632

ldst03.dH A D11-Oct-20121.5 KiB4440

ldst03.sH A D11-Oct-2012753 4036

ldst04.dH A D11-Oct-2012735 2521

ldst04.sH A D11-Oct-2012355 2017

ldst05.dH A D11-Oct-2012735 2521

ldst05.sH A D11-Oct-2012355 2017

ldst06.dH A D11-Oct-2012900 2925

ldst06.sH A D11-Oct-2012439 2321

pfam.dH A D11-Oct-20125.8 KiB154150

pfam.sH A D11-Oct-20122.7 KiB183148

pfmam.dH A D11-Oct-20125.9 KiB154150

pfmam.sH A D11-Oct-20122.8 KiB183148

pfmsm.dH A D11-Oct-20125.9 KiB154150

pfmsm.sH A D11-Oct-20122.8 KiB183148

pfsm.dH A D11-Oct-20125.8 KiB154150

pfsm.sH A D11-Oct-20122.7 KiB183148

pseudo-ops01.dH A D11-Oct-2012314 1511

pseudo-ops01.sH A D11-Oct-2012168 118

regress01.dH A D11-Oct-2012630 2218

regress01.sH A D11-Oct-2012430 2014

shift.dH A D11-Oct-20122.9 KiB8783

shift.sH A D11-Oct-20121.6 KiB9181

simd.dH A D11-Oct-20123.8 KiB106102

simd.sH A D11-Oct-20121.8 KiB120102

system.dH A D11-Oct-20122.4 KiB7369

system.sH A D11-Oct-20121.2 KiB7768

xp.dH A D11-Oct-20128.7 KiB242238

xp.sH A D11-Oct-20124.7 KiB267247

README.i860

1
2Testsuite for the i860 version of the GNU assembler
3---------------------------------------------------
4
5This is a simple testsuite for the i860 assembler.  It currently
6consists mostly of testcases for checking that every instruction is
7parsed correctly and that correct object code is generated (these
8are called "blah.s").  The files called "blah-err.s" test for error
9conditions.
10
11The suite includes testcases for the base i860XR instruction set as well
12as the enhanced i860XP instructions and control registers.
13
14The expected results files were generated using the UNIX System V/i860
15Release 4 vendor assembler (/usr/ccs/bin/as -V reports version
16"Standard C Development Environment  (SCDE) 5.0 12/08/89").  This
17way GAS/i860 is tested against a known good assembler.
18
19TODO:
20 - Relocation testing is basically non-existent.
21 - pst.d (pixel store) is the only instruction with no testcase.
22 - Some pseudo instructions need testcases (mov, all pfmov, etc.).
23 - More tests for dual instruction mode: check that dual mode has a
24   proper pair (FLOP/core) of instructions, and other error conditions.
25 - Most current testcases use the default AT&T/SVR4 syntax; a few simple
26   tests of the Intel syntax should be added to prevent bitrot (including
27   relocatable expression syntax, etc).  Test file dual03.s uses Intel
28   syntax lightly (i.e., register names without '%' prefix).
29
30Contact me (Jason Eckhardt, jle@rice.edu) if you'd like to help.
31
32Known testsuite failures:
33  - none.
34
35