1# frv testcase for cmsubhus $FRi,$FRj,$FRj,$CCi,$cond 2# mach: frv fr500 fr400 3 4 .include "testutils.inc" 5 6 start 7 8 .global cmsubhus 9cmsubhus: 10 set_spr_immed 0x1b1b,cccr 11 12 set_fr_iimmed 0x0000,0x0000,fr10 13 set_fr_iimmed 0x0000,0x0000,fr11 14 cmsubhus fr10,fr11,fr12,cc0,1 15 test_fr_limmed 0x0000,0x0000,fr12 16 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 17 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 18 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 19 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 20 21 set_fr_iimmed 0xdead,0xbeef,fr10 22 set_fr_iimmed 0x0000,0x0000,fr11 23 cmsubhus fr10,fr11,fr12,cc0,1 24 test_fr_limmed 0xdead,0xbeef,fr12 25 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 26 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 27 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 28 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 29 30 set_fr_iimmed 0x1234,0x5678,fr10 31 set_fr_iimmed 0x1111,0x1111,fr11 32 cmsubhus fr10,fr11,fr12,cc0,1 33 test_fr_limmed 0x0123,0x4567,fr12 34 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 35 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 36 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 37 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 38 39 set_fr_iimmed 0x7ffe,0x7ffe,fr10 40 set_fr_iimmed 0x0002,0x0001,fr11 41 cmsubhus fr10,fr11,fr12,cc0,1 42 test_fr_limmed 0x7ffc,0x7ffd,fr12 43 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 44 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 45 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 46 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 47 48 set_fr_iimmed 0x0001,0x0001,fr10 49 set_fr_iimmed 0x0001,0x0002,fr11 50 cmsubhus fr10,fr11,fr12,cc4,1 51 test_fr_limmed 0x0000,0x0000,fr12 52 test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set 53 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 54 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 55 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 56 57 set_spr_immed 0,msr0 58 set_fr_iimmed 0x0001,0x0001,fr10 59 set_fr_iimmed 0x0002,0x0001,fr11 60 cmsubhus fr10,fr11,fr12,cc4,1 61 test_fr_limmed 0x0000,0x0000,fr12 62 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set 63 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 64 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 65 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 66 67 set_spr_immed 0,msr0 68 set_spr_immed 0,msr1 69 set_fr_iimmed 0x0001,0x0001,fr10 70 set_fr_iimmed 0x0002,0x0002,fr11 71 cmsubhus.p fr10,fr10,fr12,cc4,1 72 cmsubhus fr10,fr11,fr13,cc4,1 73 test_fr_limmed 0x0000,0x0000,fr12 74 test_fr_limmed 0x0000,0x0000,fr13 75 test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear 76 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 77 test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set 78 test_spr_bits 2,1,1,msr1 ; msr1.ovf set 79 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 80 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 81 82 set_spr_immed 0,msr0 83 set_spr_immed 0,msr1 84 set_fr_iimmed 0x0000,0x0000,fr10 85 set_fr_iimmed 0x0000,0x0000,fr11 86 cmsubhus fr10,fr11,fr12,cc1,0 87 test_fr_limmed 0x0000,0x0000,fr12 88 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 89 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 90 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 91 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 92 93 set_fr_iimmed 0xdead,0xbeef,fr10 94 set_fr_iimmed 0x0000,0x0000,fr11 95 cmsubhus fr10,fr11,fr12,cc1,0 96 test_fr_limmed 0xdead,0xbeef,fr12 97 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 98 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 99 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 100 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 101 102 set_fr_iimmed 0x1234,0x5678,fr10 103 set_fr_iimmed 0x1111,0x1111,fr11 104 cmsubhus fr10,fr11,fr12,cc1,0 105 test_fr_limmed 0x0123,0x4567,fr12 106 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 107 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 108 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 109 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 110 111 set_fr_iimmed 0x7ffe,0x7ffe,fr10 112 set_fr_iimmed 0x0002,0x0001,fr11 113 cmsubhus fr10,fr11,fr12,cc1,0 114 test_fr_limmed 0x7ffc,0x7ffd,fr12 115 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 116 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 117 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 118 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 119 120 set_fr_iimmed 0x0001,0x0001,fr10 121 set_fr_iimmed 0x0001,0x0002,fr11 122 cmsubhus fr10,fr11,fr12,cc5,0 123 test_fr_limmed 0x0000,0x0000,fr12 124 test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is set 125 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 126 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 127 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 128 129 set_spr_immed 0,msr0 130 set_fr_iimmed 0x0001,0x0001,fr10 131 set_fr_iimmed 0x0002,0x0001,fr11 132 cmsubhus fr10,fr11,fr12,cc5,0 133 test_fr_limmed 0x0000,0x0000,fr12 134 test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is set 135 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 136 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 137 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 138 139 set_spr_immed 0,msr0 140 set_spr_immed 0,msr1 141 set_fr_iimmed 0x0001,0x0001,fr10 142 set_fr_iimmed 0x0002,0x0002,fr11 143 cmsubhus.p fr10,fr10,fr12,cc5,0 144 cmsubhus fr10,fr11,fr13,cc5,0 145 test_fr_limmed 0x0000,0x0000,fr12 146 test_fr_limmed 0x0000,0x0000,fr13 147 test_spr_bits 0x3c,2,0x0,msr0 ; msr0.sie is clear 148 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 149 test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set 150 test_spr_bits 2,1,1,msr1 ; msr1.ovf set 151 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 152 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 153 154 set_fr_iimmed 0xdead,0xbeef,fr12 155 set_spr_immed 0,msr0 156 set_spr_immed 0,msr1 157 set_fr_iimmed 0x0000,0x0000,fr10 158 set_fr_iimmed 0x0000,0x0000,fr11 159 cmsubhus fr10,fr11,fr12,cc0,0 160 test_fr_limmed 0xdead,0xbeef,fr12 161 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 162 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 163 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 164 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 165 166 set_fr_iimmed 0xbeef,0xdead,fr10 167 set_fr_iimmed 0x0000,0x0000,fr11 168 cmsubhus fr10,fr11,fr12,cc0,0 169 test_fr_limmed 0xdead,0xbeef,fr12 170 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 171 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 172 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 173 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 174 175 set_fr_iimmed 0x1234,0x5678,fr10 176 set_fr_iimmed 0x1111,0x1111,fr11 177 cmsubhus fr10,fr11,fr12,cc0,0 178 test_fr_limmed 0xdead,0xbeef,fr12 179 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 180 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 181 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 182 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 183 184 set_fr_iimmed 0x7ffe,0x7ffe,fr10 185 set_fr_iimmed 0x0002,0x0001,fr11 186 cmsubhus fr10,fr11,fr12,cc0,0 187 test_fr_limmed 0xdead,0xbeef,fr12 188 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 189 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 190 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 191 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 192 193 set_fr_iimmed 0x0001,0x0001,fr10 194 set_fr_iimmed 0x0001,0x0002,fr11 195 cmsubhus fr10,fr11,fr12,cc4,0 196 test_fr_limmed 0xdead,0xbeef,fr12 197 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 198 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 199 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 200 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 201 202 set_spr_immed 0,msr0 203 set_fr_iimmed 0x0001,0x0001,fr10 204 set_fr_iimmed 0x0002,0x0001,fr11 205 cmsubhus fr10,fr11,fr12,cc4,0 206 test_fr_limmed 0xdead,0xbeef,fr12 207 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 208 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 209 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 210 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 211 212 set_fr_iimmed 0xbeef,0xdead,fr13 213 set_spr_immed 0,msr0 214 set_spr_immed 0,msr1 215 set_fr_iimmed 0x0001,0x0001,fr10 216 set_fr_iimmed 0x0002,0x0002,fr11 217 cmsubhus.p fr10,fr10,fr12,cc4,0 218 cmsubhus fr10,fr11,fr13,cc4,0 219 test_fr_limmed 0xdead,0xbeef,fr12 220 test_fr_limmed 0xbeef,0xdead,fr13 221 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 222 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 223 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 224 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 225 226 set_fr_iimmed 0xdead,0xbeef,fr12 227 set_spr_immed 0,msr0 228 set_spr_immed 0,msr1 229 set_fr_iimmed 0x0000,0x0000,fr10 230 set_fr_iimmed 0x0000,0x0000,fr11 231 cmsubhus fr10,fr11,fr12,cc1,1 232 test_fr_limmed 0xdead,0xbeef,fr12 233 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 234 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 235 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 236 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 237 238 set_fr_iimmed 0xbeef,0xdead,fr10 239 set_fr_iimmed 0x0000,0x0000,fr11 240 cmsubhus fr10,fr11,fr12,cc1,1 241 test_fr_limmed 0xdead,0xbeef,fr12 242 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 243 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 244 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 245 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 246 247 set_fr_iimmed 0x1234,0x5678,fr10 248 set_fr_iimmed 0x1111,0x1111,fr11 249 cmsubhus fr10,fr11,fr12,cc1,1 250 test_fr_limmed 0xdead,0xbeef,fr12 251 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 252 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 253 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 254 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 255 256 set_fr_iimmed 0x7ffe,0x7ffe,fr10 257 set_fr_iimmed 0x0002,0x0001,fr11 258 cmsubhus fr10,fr11,fr12,cc1,1 259 test_fr_limmed 0xdead,0xbeef,fr12 260 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 261 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 262 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 263 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 264 265 set_fr_iimmed 0x0001,0x0001,fr10 266 set_fr_iimmed 0x0001,0x0002,fr11 267 cmsubhus fr10,fr11,fr12,cc5,1 268 test_fr_limmed 0xdead,0xbeef,fr12 269 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 270 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 271 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 272 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 273 274 set_spr_immed 0,msr0 275 set_fr_iimmed 0x0001,0x0001,fr10 276 set_fr_iimmed 0x0002,0x0001,fr11 277 cmsubhus fr10,fr11,fr12,cc5,1 278 test_fr_limmed 0xdead,0xbeef,fr12 279 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 280 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 281 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 282 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 283 284 set_fr_iimmed 0xbeef,0xdead,fr13 285 set_spr_immed 0,msr0 286 set_spr_immed 0,msr1 287 set_fr_iimmed 0x0001,0x0001,fr10 288 set_fr_iimmed 0x0002,0x0002,fr11 289 cmsubhus.p fr10,fr10,fr12,cc5,1 290 cmsubhus fr10,fr11,fr13,cc5,1 291 test_fr_limmed 0xdead,0xbeef,fr12 292 test_fr_limmed 0xbeef,0xdead,fr13 293 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 294 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 295 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 296 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 297 298 set_fr_iimmed 0xdead,0xbeef,fr12 299 set_spr_immed 0,msr0 300 set_spr_immed 0,msr1 301 set_fr_iimmed 0x0000,0x0000,fr10 302 set_fr_iimmed 0x0000,0x0000,fr11 303 cmsubhus fr10,fr11,fr12,cc2,0 304 test_fr_limmed 0xdead,0xbeef,fr12 305 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 306 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 307 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 308 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 309 310 set_fr_iimmed 0xbeef,0xdead,fr10 311 set_fr_iimmed 0x0000,0x0000,fr11 312 cmsubhus fr10,fr11,fr12,cc2,1 313 test_fr_limmed 0xdead,0xbeef,fr12 314 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 315 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 316 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 317 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 318 319 set_fr_iimmed 0x1234,0x5678,fr10 320 set_fr_iimmed 0x1111,0x1111,fr11 321 cmsubhus fr10,fr11,fr12,cc2,0 322 test_fr_limmed 0xdead,0xbeef,fr12 323 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 324 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 325 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 326 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 327 328 set_fr_iimmed 0x7ffe,0x7ffe,fr10 329 set_fr_iimmed 0x0002,0x0001,fr11 330 cmsubhus fr10,fr11,fr12,cc2,1 331 test_fr_limmed 0xdead,0xbeef,fr12 332 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 333 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 334 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 335 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 336 337 set_fr_iimmed 0x0001,0x0001,fr10 338 set_fr_iimmed 0x0001,0x0002,fr11 339 cmsubhus fr10,fr11,fr12,cc6,0 340 test_fr_limmed 0xdead,0xbeef,fr12 341 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 342 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 343 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 344 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 345 346 set_spr_immed 0,msr0 347 set_fr_iimmed 0x0001,0x0001,fr10 348 set_fr_iimmed 0x0002,0x0001,fr11 349 cmsubhus fr10,fr11,fr12,cc6,1 350 test_fr_limmed 0xdead,0xbeef,fr12 351 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 352 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 353 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 354 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 355 356 set_fr_iimmed 0xbeef,0xdead,fr13 357 set_spr_immed 0,msr0 358 set_spr_immed 0,msr1 359 set_fr_iimmed 0x0001,0x0001,fr10 360 set_fr_iimmed 0x0002,0x0002,fr11 361 cmsubhus.p fr10,fr10,fr12,cc6,0 362 cmsubhus fr10,fr11,fr13,cc6,1 363 test_fr_limmed 0xdead,0xbeef,fr12 364 test_fr_limmed 0xbeef,0xdead,fr13 365 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 366 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 367 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 368 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 369; 370 set_fr_iimmed 0xdead,0xbeef,fr12 371 set_spr_immed 0,msr0 372 set_spr_immed 0,msr1 373 set_fr_iimmed 0x0000,0x0000,fr10 374 set_fr_iimmed 0x0000,0x0000,fr11 375 cmsubhus fr10,fr11,fr12,cc3,0 376 test_fr_limmed 0xdead,0xbeef,fr12 377 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 378 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 379 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 380 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 381 382 set_fr_iimmed 0xbeef,0xdead,fr10 383 set_fr_iimmed 0x0000,0x0000,fr11 384 cmsubhus fr10,fr11,fr12,cc3,1 385 test_fr_limmed 0xdead,0xbeef,fr12 386 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 387 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 388 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 389 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 390 391 set_fr_iimmed 0x1234,0x5678,fr10 392 set_fr_iimmed 0x1111,0x1111,fr11 393 cmsubhus fr10,fr11,fr12,cc3,0 394 test_fr_limmed 0xdead,0xbeef,fr12 395 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 396 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 397 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 398 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 399 400 set_fr_iimmed 0x7ffe,0x7ffe,fr10 401 set_fr_iimmed 0x0002,0x0001,fr11 402 cmsubhus fr10,fr11,fr12,cc3,1 403 test_fr_limmed 0xdead,0xbeef,fr12 404 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 405 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 406 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 407 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 408 409 set_fr_iimmed 0x0001,0x0001,fr10 410 set_fr_iimmed 0x0001,0x0002,fr11 411 cmsubhus fr10,fr11,fr12,cc7,0 412 test_fr_limmed 0xdead,0xbeef,fr12 413 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 414 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 415 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 416 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 417 418 set_spr_immed 0,msr0 419 set_fr_iimmed 0x0001,0x0001,fr10 420 set_fr_iimmed 0x0002,0x0001,fr11 421 cmsubhus fr10,fr11,fr12,cc7,1 422 test_fr_limmed 0xdead,0xbeef,fr12 423 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 424 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 425 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 426 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 427 428 set_fr_iimmed 0xbeef,0xdead,fr13 429 set_spr_immed 0,msr0 430 set_spr_immed 0,msr1 431 set_fr_iimmed 0x0001,0x0001,fr10 432 set_fr_iimmed 0x0002,0x0002,fr11 433 cmsubhus.p fr10,fr10,fr12,cc7,0 434 cmsubhus fr10,fr11,fr13,cc7,1 435 test_fr_limmed 0xdead,0xbeef,fr12 436 test_fr_limmed 0xbeef,0xdead,fr13 437 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 438 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 439 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 440 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 441 442 pass 443