1# frv testcase for fcbolr $FCCi,$ccond,$hint 2# mach: all 3 4 .include "testutils.inc" 5 6 start 7 8 .global fcbolr 9fcbolr: 10 ; ccond is true 11 set_spr_immed 128,lcr 12 set_spr_addr bad,lr 13 set_fcc 0x0 0 14 fcbolr fcc0,0,0 15 16 set_spr_addr bad,lr 17 set_fcc 0x1 1 18 fcbolr fcc1,0,1 19 20 set_spr_addr ok3,lr 21 set_fcc 0x2 2 22 fcbolr fcc2,0,2 23 fail 24ok3: 25 set_spr_addr ok4,lr 26 set_fcc 0x3 3 27 fcbolr fcc3,0,3 28 fail 29ok4: 30 set_spr_addr ok5,lr 31 set_fcc 0x4 0 32 fcbolr fcc0,0,0 33 fail 34ok5: 35 set_spr_addr ok6,lr 36 set_fcc 0x5 1 37 fcbolr fcc1,0,1 38 fail 39ok6: 40 set_spr_addr ok7,lr 41 set_fcc 0x6 2 42 fcbolr fcc2,0,2 43 fail 44ok7: 45 set_spr_addr ok8,lr 46 set_fcc 0x7 3 47 fcbolr fcc3,0,3 48 fail 49ok8: 50 set_spr_addr ok9,lr 51 set_fcc 0x8 0 52 fcbolr fcc0,0,0 53 fail 54ok9: 55 set_spr_addr oka,lr 56 set_fcc 0x9 1 57 fcbolr fcc1,0,1 58 fail 59oka: 60 set_spr_addr okb,lr 61 set_fcc 0xa 2 62 fcbolr fcc2,0,2 63 fail 64okb: 65 set_spr_addr okc,lr 66 set_fcc 0xb 3 67 fcbolr fcc3,0,3 68 fail 69okc: 70 set_spr_addr okd,lr 71 set_fcc 0xc 0 72 fcbolr fcc0,0,0 73 fail 74okd: 75 set_spr_addr oke,lr 76 set_fcc 0xd 1 77 fcbolr fcc1,0,1 78 fail 79oke: 80 set_spr_addr okf,lr 81 set_fcc 0xe 2 82 fcbolr fcc2,0,2 83 fail 84okf: 85 set_spr_addr okg,lr 86 set_fcc 0xf 3 87 fcbolr fcc3,0,3 88 fail 89okg: 90 91 ; ccond is true 92 set_spr_immed 1,lcr 93 set_spr_addr bad,lr 94 set_fcc 0x0 0 95 fcbolr fcc0,1,0 96 97 set_spr_immed 1,lcr 98 set_spr_addr bad,lr 99 set_fcc 0x1 1 100 fcbolr fcc1,1,1 101 102 set_spr_immed 1,lcr 103 set_spr_addr okj,lr 104 set_fcc 0x2 2 105 fcbolr fcc2,1,2 106 fail 107okj: 108 set_spr_immed 1,lcr 109 set_spr_addr okk,lr 110 set_fcc 0x3 3 111 fcbolr fcc3,1,3 112 fail 113okk: 114 set_spr_immed 1,lcr 115 set_spr_addr okl,lr 116 set_fcc 0x4 0 117 fcbolr fcc0,1,0 118 fail 119okl: 120 set_spr_immed 1,lcr 121 set_spr_addr okm,lr 122 set_fcc 0x5 1 123 fcbolr fcc1,1,1 124 fail 125okm: 126 set_spr_immed 1,lcr 127 set_spr_addr okn,lr 128 set_fcc 0x6 2 129 fcbolr fcc2,1,2 130 fail 131okn: 132 set_spr_immed 1,lcr 133 set_spr_addr oko,lr 134 set_fcc 0x7 3 135 fcbolr fcc3,1,3 136 fail 137oko: 138 set_spr_immed 1,lcr 139 set_spr_addr okp,lr 140 set_fcc 0x8 0 141 fcbolr fcc0,1,0 142 fail 143okp: 144 set_spr_immed 1,lcr 145 set_spr_addr okq,lr 146 set_fcc 0x9 1 147 fcbolr fcc1,1,1 148 fail 149okq: 150 set_spr_immed 1,lcr 151 set_spr_addr okr,lr 152 set_fcc 0xa 2 153 fcbolr fcc2,1,2 154 fail 155okr: 156 set_spr_immed 1,lcr 157 set_spr_addr oks,lr 158 set_fcc 0xb 3 159 fcbolr fcc3,1,3 160 fail 161oks: 162 set_spr_immed 1,lcr 163 set_spr_addr okt,lr 164 set_fcc 0xc 0 165 fcbolr fcc0,1,0 166 fail 167okt: 168 set_spr_immed 1,lcr 169 set_spr_addr oku,lr 170 set_fcc 0xd 1 171 fcbolr fcc1,1,1 172 fail 173oku: 174 set_spr_immed 1,lcr 175 set_spr_addr okv,lr 176 set_fcc 0xe 2 177 fcbolr fcc2,1,2 178 fail 179okv: 180 set_spr_immed 1,lcr 181 set_spr_addr okw,lr 182 set_fcc 0xf 3 183 fcbolr fcc3,1,3 184 fail 185okw: 186 ; ccond is false 187 set_spr_immed 128,lcr 188 189 set_fcc 0x0 0 190 fcbolr fcc0,1,0 191 set_fcc 0x1 1 192 fcbolr fcc1,1,1 193 set_fcc 0x2 2 194 fcbolr fcc2,1,2 195 set_fcc 0x3 3 196 fcbolr fcc3,1,3 197 set_fcc 0x4 0 198 fcbolr fcc0,1,0 199 set_fcc 0x5 1 200 fcbolr fcc1,1,1 201 set_fcc 0x6 2 202 fcbolr fcc2,1,2 203 set_fcc 0x7 3 204 fcbolr fcc3,1,3 205 set_fcc 0x8 0 206 fcbolr fcc0,1,0 207 set_fcc 0x9 1 208 fcbolr fcc1,1,1 209 set_fcc 0xa 2 210 fcbolr fcc2,1,2 211 set_fcc 0xb 3 212 fcbolr fcc3,1,3 213 set_fcc 0xc 0 214 fcbolr fcc0,1,0 215 set_fcc 0xd 1 216 fcbolr fcc1,1,1 217 set_fcc 0xe 2 218 fcbolr fcc2,1,2 219 set_fcc 0xf 3 220 fcbolr fcc3,1,3 221 222 ; ccond is false 223 set_spr_immed 1,lcr 224 set_fcc 0x0 0 225 fcbolr fcc0,0,0 226 set_spr_immed 1,lcr 227 set_fcc 0x1 1 228 fcbolr fcc1,0,1 229 set_spr_immed 1,lcr 230 set_fcc 0x2 2 231 fcbolr fcc2,0,2 232 set_spr_immed 1,lcr 233 set_fcc 0x3 3 234 fcbolr fcc3,0,3 235 set_spr_immed 1,lcr 236 set_fcc 0x4 0 237 fcbolr fcc0,0,0 238 set_spr_immed 1,lcr 239 set_fcc 0x5 1 240 fcbolr fcc1,0,1 241 set_spr_immed 1,lcr 242 set_fcc 0x6 2 243 fcbolr fcc2,0,2 244 set_spr_immed 1,lcr 245 set_fcc 0x7 3 246 fcbolr fcc3,0,3 247 set_spr_immed 1,lcr 248 set_fcc 0x8 0 249 fcbolr fcc0,0,0 250 set_spr_immed 1,lcr 251 set_fcc 0x9 1 252 fcbolr fcc1,0,1 253 set_spr_immed 1,lcr 254 set_fcc 0xa 2 255 fcbolr fcc2,0,2 256 set_spr_immed 1,lcr 257 set_fcc 0xb 3 258 fcbolr fcc3,0,3 259 set_spr_immed 1,lcr 260 set_fcc 0xc 0 261 fcbolr fcc0,0,0 262 set_spr_immed 1,lcr 263 set_fcc 0xd 1 264 fcbolr fcc1,0,1 265 set_spr_immed 1,lcr 266 set_fcc 0xe 2 267 fcbolr fcc2,0,2 268 set_spr_immed 1,lcr 269 set_fcc 0xf 3 270 fcbolr fcc3,0,3 271 272 pass 273bad: 274 fail 275