1# frv testcase for fcbullr $FCCi,$ccond,$hint 2# mach: all 3 4 .include "testutils.inc" 5 6 start 7 8 .global fcbullr 9fcbullr: 10 ; ccond is true 11 set_spr_immed 128,lcr 12 set_spr_addr bad,lr 13 set_fcc 0x0 0 14 fcbullr fcc0,0,0 15 16 set_spr_addr ok2,lr 17 set_fcc 0x1 1 18 fcbullr fcc1,0,1 19 fail 20ok2: 21 set_spr_addr bad,lr 22 set_fcc 0x2 2 23 fcbullr fcc2,0,2 24 25 set_spr_addr ok4,lr 26 set_fcc 0x3 3 27 fcbullr fcc3,0,3 28 fail 29ok4: 30 set_spr_addr ok5,lr 31 set_fcc 0x4 0 32 fcbullr fcc0,0,0 33 fail 34ok5: 35 set_spr_addr ok6,lr 36 set_fcc 0x5 1 37 fcbullr fcc1,0,1 38 fail 39ok6: 40 set_spr_addr ok7,lr 41 set_fcc 0x6 2 42 fcbullr fcc2,0,2 43 fail 44ok7: 45 set_spr_addr ok8,lr 46 set_fcc 0x7 3 47 fcbullr fcc3,0,3 48 fail 49ok8: 50 set_spr_addr bad,lr 51 set_fcc 0x8 0 52 fcbullr fcc0,0,0 53 54 set_spr_addr oka,lr 55 set_fcc 0x9 1 56 fcbullr fcc1,0,1 57 fail 58oka: 59 set_spr_addr bad,lr 60 set_fcc 0xa 2 61 fcbullr fcc2,0,2 62 63 set_spr_addr okc,lr 64 set_fcc 0xb 3 65 fcbullr fcc3,0,3 66 fail 67okc: 68 set_spr_addr okd,lr 69 set_fcc 0xc 0 70 fcbullr fcc0,0,0 71 fail 72okd: 73 set_spr_addr oke,lr 74 set_fcc 0xd 1 75 fcbullr fcc1,0,1 76 fail 77oke: 78 set_spr_addr okf,lr 79 set_fcc 0xe 2 80 fcbullr fcc2,0,2 81 fail 82okf: 83 set_spr_addr okg,lr 84 set_fcc 0xf 3 85 fcbullr fcc3,0,3 86 fail 87okg: 88 89 ; ccond is true 90 set_spr_immed 1,lcr 91 set_spr_addr bad,lr 92 set_fcc 0x0 0 93 fcbullr fcc0,1,0 94 95 set_spr_immed 1,lcr 96 set_spr_addr oki,lr 97 set_fcc 0x1 1 98 fcbullr fcc1,1,1 99 fail 100oki: 101 set_spr_immed 1,lcr 102 set_spr_addr bad,lr 103 set_fcc 0x2 2 104 fcbullr fcc2,1,2 105 106 set_spr_immed 1,lcr 107 set_spr_addr okk,lr 108 set_fcc 0x3 3 109 fcbullr fcc3,1,3 110 fail 111okk: 112 set_spr_immed 1,lcr 113 set_spr_addr okl,lr 114 set_fcc 0x4 0 115 fcbullr fcc0,1,0 116 fail 117okl: 118 set_spr_immed 1,lcr 119 set_spr_addr okm,lr 120 set_fcc 0x5 1 121 fcbullr fcc1,1,1 122 fail 123okm: 124 set_spr_immed 1,lcr 125 set_spr_addr okn,lr 126 set_fcc 0x6 2 127 fcbullr fcc2,1,2 128 fail 129okn: 130 set_spr_immed 1,lcr 131 set_spr_addr oko,lr 132 set_fcc 0x7 3 133 fcbullr fcc3,1,3 134 fail 135oko: 136 set_spr_immed 1,lcr 137 set_spr_addr bad,lr 138 set_fcc 0x8 0 139 fcbullr fcc0,1,0 140 141 set_spr_immed 1,lcr 142 set_spr_addr okq,lr 143 set_fcc 0x9 1 144 fcbullr fcc1,1,1 145 fail 146okq: 147 set_spr_immed 1,lcr 148 set_spr_addr bad,lr 149 set_fcc 0xa 2 150 fcbullr fcc2,1,2 151 152 set_spr_immed 1,lcr 153 set_spr_addr oks,lr 154 set_fcc 0xb 3 155 fcbullr fcc3,1,3 156 fail 157oks: 158 set_spr_immed 1,lcr 159 set_spr_addr okt,lr 160 set_fcc 0xc 0 161 fcbullr fcc0,1,0 162 fail 163okt: 164 set_spr_immed 1,lcr 165 set_spr_addr oku,lr 166 set_fcc 0xd 1 167 fcbullr fcc1,1,1 168 fail 169oku: 170 set_spr_immed 1,lcr 171 set_spr_addr okv,lr 172 set_fcc 0xe 2 173 fcbullr fcc2,1,2 174 fail 175okv: 176 set_spr_immed 1,lcr 177 set_spr_addr okw,lr 178 set_fcc 0xf 3 179 fcbullr fcc3,1,3 180 fail 181okw: 182 ; ccond is false 183 set_spr_immed 128,lcr 184 185 set_fcc 0x0 0 186 fcbullr fcc0,1,0 187 set_fcc 0x1 1 188 fcbullr fcc1,1,1 189 set_fcc 0x2 2 190 fcbullr fcc2,1,2 191 set_fcc 0x3 3 192 fcbullr fcc3,1,3 193 set_fcc 0x4 0 194 fcbullr fcc0,1,0 195 set_fcc 0x5 1 196 fcbullr fcc1,1,1 197 set_fcc 0x6 2 198 fcbullr fcc2,1,2 199 set_fcc 0x7 3 200 fcbullr fcc3,1,3 201 set_fcc 0x8 0 202 fcbullr fcc0,1,0 203 set_fcc 0x9 1 204 fcbullr fcc1,1,1 205 set_fcc 0xa 2 206 fcbullr fcc2,1,2 207 set_fcc 0xb 3 208 fcbullr fcc3,1,3 209 set_fcc 0xc 0 210 fcbullr fcc0,1,0 211 set_fcc 0xd 1 212 fcbullr fcc1,1,1 213 set_fcc 0xe 2 214 fcbullr fcc2,1,2 215 set_fcc 0xf 3 216 fcbullr fcc3,1,3 217 218 ; ccond is false 219 set_spr_immed 1,lcr 220 set_fcc 0x0 0 221 fcbullr fcc0,0,0 222 set_spr_immed 1,lcr 223 set_fcc 0x1 1 224 fcbullr fcc1,0,1 225 set_spr_immed 1,lcr 226 set_fcc 0x2 2 227 fcbullr fcc2,0,2 228 set_spr_immed 1,lcr 229 set_fcc 0x3 3 230 fcbullr fcc3,0,3 231 set_spr_immed 1,lcr 232 set_fcc 0x4 0 233 fcbullr fcc0,0,0 234 set_spr_immed 1,lcr 235 set_fcc 0x5 1 236 fcbullr fcc1,0,1 237 set_spr_immed 1,lcr 238 set_fcc 0x6 2 239 fcbullr fcc2,0,2 240 set_spr_immed 1,lcr 241 set_fcc 0x7 3 242 fcbullr fcc3,0,3 243 set_spr_immed 1,lcr 244 set_fcc 0x8 0 245 fcbullr fcc0,0,0 246 set_spr_immed 1,lcr 247 set_fcc 0x9 1 248 fcbullr fcc1,0,1 249 set_spr_immed 1,lcr 250 set_fcc 0xa 2 251 fcbullr fcc2,0,2 252 set_spr_immed 1,lcr 253 set_fcc 0xb 3 254 fcbullr fcc3,0,3 255 set_spr_immed 1,lcr 256 set_fcc 0xc 0 257 fcbullr fcc0,0,0 258 set_spr_immed 1,lcr 259 set_fcc 0xd 1 260 fcbullr fcc1,0,1 261 set_spr_immed 1,lcr 262 set_fcc 0xe 2 263 fcbullr fcc2,0,2 264 set_spr_immed 1,lcr 265 set_fcc 0xf 3 266 fcbullr fcc3,0,3 267 268 pass 269bad: 270 fail 271