1# frv testcase for ftilg $FCCi_2,$GRi,$s12 2# mach: all 3 4 .include "testutils.inc" 5 6 start 7 8 .global ftilg 9ftilg: 10 and_spr_immed -4081,tbr ; clear tbr.tt 11 set_gr_spr tbr,gr7 12 inc_gr_immed 2112,gr7 ; address of exception handler 13 set_bctrlr_0_0 gr7 ; bctrlr 0,0 14 15 set_spr_immed 128,lcr 16 set_gr_immed 0,gr7 17 18 set_spr_addr bad,lr 19 set_fcc 0x0 0 20 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 21 22 set_spr_addr bad,lr 23 set_fcc 0x1 0 24 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 25 26 set_psr_et 1 27 set_spr_addr ok2,lr 28 set_fcc 0x2 0 29 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 30 fail 31ok2: 32 set_psr_et 1 33 set_spr_addr ok3,lr 34 set_fcc 0x3 0 35 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 36 fail 37ok3: 38 set_psr_et 1 39 set_spr_addr ok4,lr 40 set_fcc 0x4 0 41 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 42 fail 43ok4: 44 set_psr_et 1 45 set_spr_addr ok5,lr 46 set_fcc 0x5 0 47 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 48 fail 49ok5: 50 set_psr_et 1 51 set_spr_addr ok6,lr 52 set_fcc 0x6 0 53 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 54 fail 55ok6: 56 set_psr_et 1 57 set_spr_addr ok7,lr 58 set_fcc 0x7 0 59 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 60 fail 61ok7: 62 set_spr_addr bad,lr 63 set_fcc 0x8 0 64 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 65 66 set_spr_addr bad,lr 67 set_fcc 0x9 0 68 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 69 70 set_psr_et 1 71 set_spr_addr oka,lr 72 set_fcc 0xa 0 73 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 74 fail 75oka: 76 set_psr_et 1 77 set_spr_addr okb,lr 78 set_fcc 0xb 0 79 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 80 fail 81okb: 82 set_psr_et 1 83 set_spr_addr okc,lr 84 set_fcc 0xc 0 85 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 86 fail 87okc: 88 set_psr_et 1 89 set_spr_addr okd,lr 90 set_fcc 0xd 0 91 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 92 fail 93okd: 94 set_psr_et 1 95 set_spr_addr oke,lr 96 set_fcc 0xe 0 97 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 98 fail 99oke: 100 set_psr_et 1 101 set_spr_addr okf,lr 102 set_fcc 0xf 0 103 ftilg fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 104 fail 105okf: 106 pass 107bad: 108 fail 109