1# frv testcase for mp_exception 2# mach: frv fr500 fr400 3 4 .include "testutils.inc" 5 6 start 7 8 .global mp_exception 9mpx: 10 and_spr_immed -4081,tbr ; clear tbr.tt 11 set_gr_spr tbr,gr7 12 inc_gr_immed 0x0e0,gr7 ; address of exception handler 13 set_bctrlr_0_0 gr7 14 set_spr_immed 128,lcr 15 set_spr_addr ok1,lr 16 set_psr_et 1 17 set_gr_immed 0,gr5 18 19 set_spr_immed 0,msr0 20 set_fr_iimmed 0x1234,0x5678,fr10 21 set_fr_iimmed 0x7ffe,0x7ffe,fr11 22 set_fr_iimmed 0xffff,0xffff,fr12 23 set_fr_iimmed 0x0002,0x0001,fr13 24 mqaddhss fr10,fr12,fr14 25 test_fr_limmed 0x1233,0x5677,fr14 26 test_fr_limmed 0x7fff,0x7fff,fr15 27 test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set 28 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 29 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 30 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 31 mtrap ; generate interrupt 32 test_gr_immed 1,gr5 33 34 and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields 35 mcmpsh fr10,fr11,fcc0 ; no exception 36 test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear 37 mtrap ; nop 38 test_gr_immed 1,gr5 39 40 pass 41 42; exception handler 43ok1: 44 test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set 45 test_spr_bits 2,1,1,msr0 ; msr0.ovf set 46 test_spr_bits 1,0,1,msr0 ; msr0.aovf set 47 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set 48 inc_gr_immed 1,gr5 49 rett 0 50 fail 51