1unit ATtiny48; 2 3{$goto on} 4 5interface 6 7var 8 // TIMER_COUNTER_1 9 TIMSK1 : byte absolute $00+$6F; // Timer/Counter Interrupt Mask Register 10 TIFR1 : byte absolute $00+$36; // Timer/Counter Interrupt Flag register 11 TCCR1A : byte absolute $00+$80; // Timer/Counter1 Control Register A 12 TCCR1B : byte absolute $00+$81; // Timer/Counter1 Control Register B 13 TCCR1C : byte absolute $00+$82; // Timer/Counter1 Control Register C 14 TCNT1 : word absolute $00+$84; // Timer/Counter1 Bytes 15 TCNT1L : byte absolute $00+$84; // Timer/Counter1 Bytes 16 TCNT1H : byte absolute $00+$84+1; // Timer/Counter1 Bytes 17 OCR1A : word absolute $00+$88; // Timer/Counter1 Output Compare Register Bytes 18 OCR1AL : byte absolute $00+$88; // Timer/Counter1 Output Compare Register Bytes 19 OCR1AH : byte absolute $00+$88+1; // Timer/Counter1 Output Compare Register Bytes 20 OCR1B : word absolute $00+$8A; // Timer/Counter1 Output Compare Register Bytes 21 OCR1BL : byte absolute $00+$8A; // Timer/Counter1 Output Compare Register Bytes 22 OCR1BH : byte absolute $00+$8A+1; // Timer/Counter1 Output Compare Register Bytes 23 ICR1 : word absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes 24 ICR1L : byte absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes 25 ICR1H : byte absolute $00+$86+1; // Timer/Counter1 Input Capture Register Bytes 26 GTCCR : byte absolute $00+$43; // General Timer/Counter Control Register 27 // ANALOG_COMPARATOR 28 ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register 29 DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 1 30 // PORTB 31 PORTB : byte absolute $00+$25; // Port B Data Register 32 DDRB : byte absolute $00+$24; // Port B Data Direction Register 33 PINB : byte absolute $00+$23; // Port B Input Pins 34 // PORTD 35 PORTD : byte absolute $00+$2B; // Port D Data Register 36 DDRD : byte absolute $00+$2A; // Port D Data Direction Register 37 PIND : byte absolute $00+$29; // Port D Input Pins 38 // SPI 39 SPDR : byte absolute $00+$4E; // SPI Data Register 40 SPSR : byte absolute $00+$4D; // SPI Status Register 41 SPCR : byte absolute $00+$4C; // SPI Control Register 42 // WATCHDOG 43 WDTCSR : byte absolute $00+$60; // Watchdog Timer Control Register 44 // CPU 45 PRR : byte absolute $00+$64; // Power Reduction Register 46 OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value 47 CLKPR : byte absolute $00+$61; // Clock Prescale Register 48 SREG : byte absolute $00+$5F; // Status Register 49 SPL : byte absolute $00+$5D; // Stack Pointe Low 50 SPH : byte absolute $00+$5E; // Stack Pointe High 51 SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register 52 MCUCR : byte absolute $00+$55; // MCU Control Register 53 MCUSR : byte absolute $00+$54; // MCU Status Register 54 SMCR : byte absolute $00+$53; // 55 GPIOR2 : byte absolute $00+$4B; // General Purpose I/O Register 2 56 GPIOR1 : byte absolute $00+$4A; // General Purpose I/O Register 1 57 GPIOR0 : byte absolute $00+$3E; // General Purpose I/O Register 0 58 PORTCR : byte absolute $00+$32; // Port Configuration Register 59 // TWI 60 TWHSR : byte absolute $00+$BE; // TWHSR 61 TWAMR : byte absolute $00+$BD; // TWI (Slave) Address Mask Register 62 TWBR : byte absolute $00+$B8; // TWI Bit Rate register 63 TWCR : byte absolute $00+$BC; // TWI Control Register 64 TWSR : byte absolute $00+$B9; // TWI Status Register 65 TWDR : byte absolute $00+$BB; // TWI Data register 66 TWAR : byte absolute $00+$BA; // TWI (Slave) Address register 67 // AD_CONVERTER 68 ADMUX : byte absolute $00+$7C; // The ADC multiplexer Selection Register 69 ADC : word absolute $00+$78; // ADC Data Register Bytes 70 ADCL : byte absolute $00+$78; // ADC Data Register Bytes 71 ADCH : byte absolute $00+$78+1; // ADC Data Register Bytes 72 ADCSRA : byte absolute $00+$7A; // The ADC Control and Status register A 73 ADCSRB : byte absolute $00+$7B; // The ADC Control and Status register B 74 DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0 75 // EXTERNAL_INTERRUPT 76 EICRA : byte absolute $00+$69; // External Interrupt Control Register 77 EIMSK : byte absolute $00+$3D; // External Interrupt Mask Register 78 EIFR : byte absolute $00+$3C; // External Interrupt Flag Register 79 PCICR : byte absolute $00+$68; // 80 PCMSK3 : byte absolute $00+$6A; // Pin Change Mask Register 3 81 PCMSK2 : byte absolute $00+$6D; // Pin Change Mask Register 2 82 PCMSK1 : byte absolute $00+$6C; // Pin Change Mask Register 1 83 PCMSK0 : byte absolute $00+$6B; // Pin Change Mask Register 0 84 PCIFR : byte absolute $00+$3B; // Pin Change Interrupt Flag Register 85 // PORTC 86 PORTC : byte absolute $00+$28; // Port C Data Register 87 DDRC : byte absolute $00+$27; // Port C Data Direction Register 88 PINC : byte absolute $00+$26; // Port C Input Pins 89 // PORTA 90 PORTA : byte absolute $00+$2E; // Port A Data Register 91 DDRA : byte absolute $00+$2D; // Port A Data Direction Register 92 PINA : byte absolute $00+$2C; // Port A Input Pins 93 // TIMER_COUNTER_0 94 OCR0B : byte absolute $00+$48; // Timer/Counter0 Output Compare Register 95 OCR0A : byte absolute $00+$47; // Timer/Counter0 Output Compare Register 96 TCNT0 : byte absolute $00+$46; // Timer/Counter0 97 TCCR0A : byte absolute $00+$45; // Timer/Counter Control Register A 98 TIMSK0 : byte absolute $00+$6E; // Timer/Counter0 Interrupt Mask Register 99 TIFR0 : byte absolute $00+$35; // Timer/Counter0 Interrupt Flag register 100 // EEPROM 101 EEARL : byte absolute $00+$41; // EEPROM Address Register Low Byte 102 EEDR : byte absolute $00+$40; // EEPROM Data Register 103 EECR : byte absolute $00+$3F; // EEPROM Control Register 104 105const 106 // TIMSK1 107 ICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable 108 OCIE1B = 2; // Timer/Counter1 Output CompareB Match Interrupt Enable 109 OCIE1A = 1; // Timer/Counter1 Output CompareA Match Interrupt Enable 110 TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable 111 // TIFR1 112 ICF1 = 5; // Input Capture Flag 1 113 OCF1B = 2; // Output Compare Flag 1B 114 OCF1A = 1; // Output Compare Flag 1A 115 TOV1 = 0; // Timer/Counter1 Overflow Flag 116 // TCCR1A 117 COM1A = 6; // Compare Output Mode 1A, bits 118 COM1B = 4; // Compare Output Mode 1B, bits 119 WGM1 = 0; // Waveform Generation Mode 120 // TCCR1B 121 ICNC1 = 7; // Input Capture 1 Noise Canceler 122 ICES1 = 6; // Input Capture 1 Edge Select 123 CS1 = 0; // Prescaler source of Timer/Counter 1 124 // TCCR1C 125 FOC1A = 7; // 126 FOC1B = 6; // 127 // GTCCR 128 TSM = 7; // Timer/Counter Synchronization Mode 129 PSRSYNC = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0 130 // ACSR 131 ACD = 7; // Analog Comparator Disable 132 ACBG = 6; // Analog Comparator Bandgap Select 133 ACO = 5; // Analog Compare Output 134 ACI = 4; // Analog Comparator Interrupt Flag 135 ACIE = 3; // Analog Comparator Interrupt Enable 136 ACIC = 2; // Analog Comparator Input Capture Enable 137 ACIS = 0; // Analog Comparator Interrupt Mode Select bits 138 // DIDR1 139 AIN1D = 1; // AIN1 Digital Input Disable 140 AIN0D = 0; // AIN0 Digital Input Disable 141 // SPSR 142 SPIF = 7; // SPI Interrupt Flag 143 WCOL = 6; // Write Collision Flag 144 SPI2X = 0; // Double SPI Speed Bit 145 // SPCR 146 SPIE = 7; // SPI Interrupt Enable 147 SPE = 6; // SPI Enable 148 DORD = 5; // Data Order 149 MSTR = 4; // Master/Slave Select 150 CPOL = 3; // Clock polarity 151 CPHA = 2; // Clock Phase 152 SPR = 0; // SPI Clock Rate Selects 153 // WDTCSR 154 WDIF = 7; // Watchdog Timeout Interrupt Flag 155 WDIE = 6; // Watchdog Timeout Interrupt Enable 156 WDP = 0; // Watchdog Timer Prescaler Bits 157 WDCE = 4; // Watchdog Change Enable 158 WDE = 3; // Watch Dog Enable 159 // PRR 160 PRTWI = 7; // Power Reduction TWI 161 PRTIM0 = 5; // Power Reduction Timer/Counter0 162 PRTIM1 = 3; // Power Reduction Timer/Counter1 163 PRSPI = 2; // Power Reduction Serial Peripheral Interface 164 PRADC = 0; // Power Reduction ADC 165 // CLKPR 166 CLKPCE = 7; // Clock Prescaler Change Enable 167 CLKPS = 0; // Clock Prescaler Select Bits 168 // SREG 169 I = 7; // Global Interrupt Enable 170 T = 6; // Bit Copy Storage 171 H = 5; // Half Carry Flag 172 S = 4; // Sign Bit 173 V = 3; // Two's Complement Overflow Flag 174 N = 2; // Negative Flag 175 Z = 1; // Zero Flag 176 C = 0; // Carry Flag 177 // SPMCSR 178 RWWSB = 6; // Read-While-Write Section Busy 179 CTPB = 4; // Clear Temporary Page Buffer 180 RFLB = 3; // Read Fuse and Lock Bits 181 PGWRT = 2; // Page Write 182 PGERS = 1; // Page Erase 183 SELFPRGEN = 0; // Self Programming Enable 184 // MCUCR 185 BODS = 6; // BOD Sleep 186 BODSE = 5; // BOD Sleep Enable 187 PUD = 4; // 188 // MCUSR 189 WDRF = 3; // Watchdog Reset Flag 190 BORF = 2; // Brown-out Reset Flag 191 EXTRF = 1; // External Reset Flag 192 PORF = 0; // Power-on reset flag 193 // SMCR 194 SM = 1; // 195 SE = 0; // 196 // PORTCR 197 BBMD = 7; // 198 BBMC = 6; // 199 BBMB = 5; // 200 BBMA = 4; // 201 PUDD = 3; // 202 PUDC = 2; // 203 PUDB = 1; // 204 PUDA = 0; // 205 // TWHSR 206 TWHS = 0; // 207 // TWAMR 208 TWAM = 1; // 209 // TWCR 210 TWINT = 7; // TWI Interrupt Flag 211 TWEA = 6; // TWI Enable Acknowledge Bit 212 TWSTA = 5; // TWI Start Condition Bit 213 TWSTO = 4; // TWI Stop Condition Bit 214 TWWC = 3; // TWI Write Collition Flag 215 TWEN = 2; // TWI Enable Bit 216 TWIE = 0; // TWI Interrupt Enable 217 // TWSR 218 TWS = 3; // TWI Status 219 TWPS = 0; // TWI Prescaler 220 // TWAR 221 TWA = 1; // TWI (Slave) Address register Bits 222 TWGCE = 0; // TWI General Call Recognition Enable Bit 223 // ADMUX 224 REFS0 = 6; // Reference Selection Bit 0 225 ADLAR = 5; // Left Adjust Result 226 MUX = 0; // Analog Channel and Gain Selection Bits 227 // ADCSRA 228 ADEN = 7; // ADC Enable 229 ADSC = 6; // ADC Start Conversion 230 ADATE = 5; // ADC Auto Trigger Enable 231 ADIF = 4; // ADC Interrupt Flag 232 ADIE = 3; // ADC Interrupt Enable 233 ADPS = 0; // ADC Prescaler Select Bits 234 // ADCSRB 235 ACME = 6; // 236 ADTS = 0; // ADC Auto Trigger Source bits 237 // DIDR1 238 // DIDR0 239 ADC7D = 7; // 240 ADC6D = 6; // 241 ADC5D = 5; // 242 ADC4D = 4; // 243 ADC3D = 3; // 244 ADC2D = 2; // 245 ADC1D = 1; // 246 ADC0D = 0; // 247 // EICRA 248 ISC1 = 2; // External Interrupt Sense Control 1 Bits 249 ISC0 = 0; // External Interrupt Sense Control 0 Bits 250 // EIMSK 251 INT = 0; // External Interrupt Request 1 Enable 252 // EIFR 253 INTF = 0; // External Interrupt Flags 254 // PCICR 255 PCIE = 0; // 256 // PCMSK3 257 PCINT = 0; // Pin Change Enable Masks 258 // PCMSK2 259 // PCMSK1 260 // PCMSK0 261 // PCIFR 262 PCIF = 0; // Pin Change Interrupt Flags 263 // TCCR0A 264 CTC0 = 3; // Clear Timer on Compare Match 265 CS0 = 0; // Clock Select 266 // TIMSK0 267 OCIE0B = 2; // Timer/Counter0 Output Compare Match B Interrupt Enable 268 OCIE0A = 1; // Timer/Counter0 Output Compare Match A Interrupt Enable 269 TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable 270 // TIFR0 271 OCF0B = 2; // Timer/Counter0 Output Compare Flag 0B 272 OCF0A = 1; // Timer/Counter0 Output Compare Flag 0A 273 TOV0 = 0; // Timer/Counter0 Overflow Flag 274 // GTCCR 275 // EECR 276 EEPM = 4; // EEPROM Programming Mode Bits 277 EERIE = 3; // EEPROM Ready Interrupt Enable 278 EEMPE = 2; // EEPROM Master Write Enable 279 EEPE = 1; // EEPROM Write Enable 280 EERE = 0; // EEPROM Read Enable 281 282implementation 283 284{$define RELBRANCHES} 285 286{$i avrcommon.inc} 287 288procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0 289procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1 290procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 3 Pin Change Interrupt Request 0 291procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 4 Pin Change Interrupt Request 1 292procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 5 Pin Change Interrupt Request 2 293procedure PCINT3_ISR; external name 'PCINT3_ISR'; // Interrupt 6 Pin Change Interrupt Request 3 294procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 7 Watchdog Time-out Interrupt 295procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 8 Timer/Counter1 Capture Event 296procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 9 Timer/Counter1 Compare Match A 297procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 10 Timer/Counter1 Compare Match B 298procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 11 Timer/Counter1 Overflow 299procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 12 TimerCounter0 Compare Match A 300procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 13 TimerCounter0 Compare Match B 301procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 14 Timer/Couner0 Overflow 302procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 15 SPI Serial Transfer Complete 303procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 16 ADC Conversion Complete 304procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 17 EEPROM Ready 305procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 18 Analog Comparator 306procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 19 Two-wire Serial Interface 307 308procedure _FPC_start; assembler; nostackframe; 309label 310 _start; 311 asm 312 .init 313 .globl _start 314 315 rjmp _start 316 rjmp INT0_ISR 317 rjmp INT1_ISR 318 rjmp PCINT0_ISR 319 rjmp PCINT1_ISR 320 rjmp PCINT2_ISR 321 rjmp PCINT3_ISR 322 rjmp WDT_ISR 323 rjmp TIMER1_CAPT_ISR 324 rjmp TIMER1_COMPA_ISR 325 rjmp TIMER1_COMPB_ISR 326 rjmp TIMER1_OVF_ISR 327 rjmp TIMER0_COMPA_ISR 328 rjmp TIMER0_COMPB_ISR 329 rjmp TIMER0_OVF_ISR 330 rjmp SPI_STC_ISR 331 rjmp ADC_ISR 332 rjmp EE_RDY_ISR 333 rjmp ANA_COMP_ISR 334 rjmp TWI_ISR 335 336 {$i start.inc} 337 338 .weak INT0_ISR 339 .weak INT1_ISR 340 .weak PCINT0_ISR 341 .weak PCINT1_ISR 342 .weak PCINT2_ISR 343 .weak PCINT3_ISR 344 .weak WDT_ISR 345 .weak TIMER1_CAPT_ISR 346 .weak TIMER1_COMPA_ISR 347 .weak TIMER1_COMPB_ISR 348 .weak TIMER1_OVF_ISR 349 .weak TIMER0_COMPA_ISR 350 .weak TIMER0_COMPB_ISR 351 .weak TIMER0_OVF_ISR 352 .weak SPI_STC_ISR 353 .weak ADC_ISR 354 .weak EE_RDY_ISR 355 .weak ANA_COMP_ISR 356 .weak TWI_ISR 357 358 .set INT0_ISR, Default_IRQ_handler 359 .set INT1_ISR, Default_IRQ_handler 360 .set PCINT0_ISR, Default_IRQ_handler 361 .set PCINT1_ISR, Default_IRQ_handler 362 .set PCINT2_ISR, Default_IRQ_handler 363 .set PCINT3_ISR, Default_IRQ_handler 364 .set WDT_ISR, Default_IRQ_handler 365 .set TIMER1_CAPT_ISR, Default_IRQ_handler 366 .set TIMER1_COMPA_ISR, Default_IRQ_handler 367 .set TIMER1_COMPB_ISR, Default_IRQ_handler 368 .set TIMER1_OVF_ISR, Default_IRQ_handler 369 .set TIMER0_COMPA_ISR, Default_IRQ_handler 370 .set TIMER0_COMPB_ISR, Default_IRQ_handler 371 .set TIMER0_OVF_ISR, Default_IRQ_handler 372 .set SPI_STC_ISR, Default_IRQ_handler 373 .set ADC_ISR, Default_IRQ_handler 374 .set EE_RDY_ISR, Default_IRQ_handler 375 .set ANA_COMP_ISR, Default_IRQ_handler 376 .set TWI_ISR, Default_IRQ_handler 377 end; 378 379end. 380