1# VHDL 2Title=VHDL 3CaseSensitive=No 4Delimiter=~`!@#$%^&*()-+=|\{}[]:;"',.<>/? 5LineComment=-- 6BlockComment= 7EscapeChar= 8StringChar=" 9DirectiveLeading= 10KeywordPrefix= 11SpecialWordPrefix= 12IndentChar= 13UnindentChar= 14BracePair=( ) { } [ ] 15AutoCompletePair=() [] {} "" 16 17# System Predefined Color & Style 18TextColor=Black 19TextBgColor=White 20TextStyle= 21 22DelimiterColor=SaddleBrown 23DelimiterBgColor= 24DelimiterStyle= 25 26SpaceColor=Aqua 27SpaceBgColor= 28SpaceStyle= 29 30NumberColor=Blue 31NumberBgColor= 32NumberStyle= 33 34StringColor=Red 35StringBgColor= 36StringStyle= 37 38CommentColor=Teal 39CommentBgColor= 40CommentStyle= 41 42DirectiveColor=Green 43DirectiveBgColor= 44DirectiveStyle= 45 46SpecialWordColor=Navy 47SpecialWordBgColor= 48SpecialWordStyle= 49 50LineNumberColor=White 51LineNumberBgColor=A0A0A0 52LineNumberStyle= 53 54ActiveLineColor=Fuchsia 55BookmarkColor=C0FFFF 56 57# User Defined Keywords 58[1.ReservedWords] 59Color=Black 60BgColor= 61Style=Bold 62InRange=0 63Keyword=abs access after alias all and architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map mod nand new next nor not null of on open or others out package port postponed procedure process pure range record register reject rem report return rol ror select severity signal shared sla sll sra srl subtype then to transport type unaffected untis until use variable wait when while with xnor xor 64 65[2.Attributes] 66Color=DarkBlue 67BgColor= 68Style=Bold 69InRange=0 70Keyword=active ascending ascending base delayed driving driving_value event falling_edge high image instance_name last_active last_event last_value left leftof length low path_name pos pred quiet reverse_range right rightof rising_edge simple_name stable succ transaction val value 71 72[3.Types] 73Color=ForestGreen 74BgColor= 75Style=Bold 76InRange=0 77Keyword=bit bit_vector boolean character integer line natural positive real signed std_logic std_logic_vector string text time unsigned 78 79[4.Procedures] 80Color=DarkOrchid 81BgColor= 82Style=Bold 83InRange=0 84Keyword=endfile file_close file_open read readline write writeline 85