1 /* 2001 MJ */
2 
3 #ifndef REGISTERS_H
4 #define REGISTERS_H
5 
6 #include "sysdeps.h"
7 #include "spcflags.h"
8 typedef char flagtype;
9 
10 
11 struct xttrx {
12     uae_u32 log_addr_base : 8;
13     uae_u32 log_addr_mask : 8;
14     uae_u32 enable : 1;
15     uae_u32 s_field : 2;
16     uae_u32 : 3;
17     uae_u32 usr1 : 1;
18     uae_u32 usr0 : 1;
19     uae_u32 : 1;
20     uae_u32 cmode : 2;
21     uae_u32 : 2;
22     uae_u32 write : 1;
23     uae_u32 : 2;
24 };
25 
26 struct mmusr_t {
27    uae_u32 phys_addr : 20;
28    uae_u32 bus_err : 1;
29    uae_u32 global : 1;
30    uae_u32 usr1 : 1;
31    uae_u32 usr0 : 1;
32    uae_u32 super : 1;
33    uae_u32 cmode : 2;
34    uae_u32 modif : 1;
35    uae_u32 : 1;
36    uae_u32 write : 1;
37    uae_u32 ttrhit : 1;
38    uae_u32 resident : 1;
39 };
40 
41 struct log_addr4 {
42    uae_u32 rif : 7;
43    uae_u32 pif : 7;
44    uae_u32 paif : 6;
45    uae_u32 poff : 12;
46 };
47 
48 struct log_addr8 {
49   uae_u32 rif : 7;
50   uae_u32 pif : 7;
51   uae_u32 paif : 5;
52   uae_u32 poff : 13;
53 };
54 
55 extern struct regstruct
56 {
57     uae_u32 regs[16];
58     uaecptr  usp,isp,msp;
59     uae_u16 sr;
60     flagtype t1;
61     flagtype t0;
62     flagtype s;
63     flagtype m;
64     flagtype x;
65     flagtype stopped;
66     int intmask;
67 
68     uae_u32 pc;
69     uae_u32 fault_pc;
70     uae_u8 *pc_p;
71     uae_u8 *pc_oldp;
72 
73     uae_u32 vbr,sfc,dfc;
74 
75     volatile uae_u32 spcflags;
76 
77 #if 0
78     uae_u32 kick_mask;
79 
80     /* Fellow sources say this is 4 longwords. That's impossible. It needs
81      * to be at least a longword. The HRM has some cryptic comment about two
82      * instructions being on the same longword boundary.
83      * The way this is implemented now seems like a good compromise.
84      */
85     uae_u32 prefetch;
86 #endif
87 
88     /* MMU reg*/
89     uae_u32 urp,srp;
90     uae_u32 tc;
91 
92     int mmu_enabled;		/* flagtype tce; */
93     int mmu_pagesize_8k;	/*  flagtype tcp; */
94 
95     uae_u32 dtt0,dtt1,itt0,itt1;
96     uae_u32 mmusr;
97 
98     uae_u32 mmu_fslw, mmu_fault_addr;
99     uae_u16 mmu_ssw;
100     uae_u32 wb3_data;
101     uae_u16 wb3_status;
102 
103     /* Cache reg*/
104     uae_u32 cacr,caar;
105 } regs;
106 
m68k_getpc(void)107 static inline uaecptr m68k_getpc (void)
108 {
109 #ifdef FULLMMU
110     return regs.pc;
111 #else
112     return regs.pc + ((char *)regs.pc_p - (char *)regs.pc_oldp);
113 #endif
114 }
115 
116 #endif
117