1 /* This file is part of the dynarmic project.
2  * Copyright (c) 2016 MerryMage
3  * SPDX-License-Identifier: 0BSD
4  */
5 
6 #include <dynarmic/A32/config.h>
7 
8 #include "frontend/A32/translate/impl/translate_arm.h"
9 
10 namespace Dynarmic::A32 {
11 
12 // BKPT #<imm16>
arm_BKPT(Cond cond,Imm<12>,Imm<4>)13 bool ArmTranslatorVisitor::arm_BKPT(Cond cond, Imm<12> /*imm12*/, Imm<4> /*imm4*/) {
14     if (cond != Cond::AL && !options.define_unpredictable_behaviour) {
15         return UnpredictableInstruction();
16     }
17     // UNPREDICTABLE: The instruction executes conditionally.
18 
19     if (!ConditionPassed(cond)) {
20         return true;
21     }
22 
23     ir.ExceptionRaised(Exception::Breakpoint);
24     ir.SetTerm(IR::Term::CheckHalt{IR::Term::ReturnToDispatch{}});
25     return false;
26 }
27 
28 // SVC<c> #<imm24>
arm_SVC(Cond cond,Imm<24> imm24)29 bool ArmTranslatorVisitor::arm_SVC(Cond cond, Imm<24> imm24) {
30     if (!ConditionPassed(cond)) {
31         return true;
32     }
33 
34     const u32 imm32 = imm24.ZeroExtend();
35     ir.PushRSB(ir.current_location.AdvancePC(4));
36     ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
37     ir.CallSupervisor(ir.Imm32(imm32));
38     ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}});
39     return false;
40 }
41 
42 // UDF<c> #<imm16>
arm_UDF()43 bool ArmTranslatorVisitor::arm_UDF() {
44 #if ARCHITECTURE_x86_64
45     return UndefinedInstruction();
46 #else
47     return InterpretThisInstruction();
48 #endif
49 }
50 
51 } // namespace Dynarmic::A32
52