1 // Copyright 2017 Citra Emulator Project 2 // Licensed under GPLv2 or any later version 3 // Refer to the license.txt file included. 4 5 #pragma once 6 7 #include <array> 8 #include "common/assert.h" 9 #include "common/bit_field.h" 10 #include "common/common_funcs.h" 11 #include "common/common_types.h" 12 13 namespace Pica { 14 15 struct PipelineRegs { 16 enum class VertexAttributeFormat : u32 { 17 BYTE = 0, 18 UBYTE = 1, 19 SHORT = 2, 20 FLOAT = 3, 21 }; 22 23 struct { 24 BitField<1, 28, u32> base_address; 25 GetPhysicalBaseAddressPipelineRegs::__anon72da46f2010826 PAddr GetPhysicalBaseAddress() const { 27 return base_address * 16; 28 } 29 30 // Descriptor for internal vertex attributes 31 union { 32 BitField<0, 2, VertexAttributeFormat> format0; // size of one element 33 BitField<2, 2, u32> size0; // number of elements minus 1 34 BitField<4, 2, VertexAttributeFormat> format1; 35 BitField<6, 2, u32> size1; 36 BitField<8, 2, VertexAttributeFormat> format2; 37 BitField<10, 2, u32> size2; 38 BitField<12, 2, VertexAttributeFormat> format3; 39 BitField<14, 2, u32> size3; 40 BitField<16, 2, VertexAttributeFormat> format4; 41 BitField<18, 2, u32> size4; 42 BitField<20, 2, VertexAttributeFormat> format5; 43 BitField<22, 2, u32> size5; 44 BitField<24, 2, VertexAttributeFormat> format6; 45 BitField<26, 2, u32> size6; 46 BitField<28, 2, VertexAttributeFormat> format7; 47 BitField<30, 2, u32> size7; 48 }; 49 50 union { 51 BitField<0, 2, VertexAttributeFormat> format8; 52 BitField<2, 2, u32> size8; 53 BitField<4, 2, VertexAttributeFormat> format9; 54 BitField<6, 2, u32> size9; 55 BitField<8, 2, VertexAttributeFormat> format10; 56 BitField<10, 2, u32> size10; 57 BitField<12, 2, VertexAttributeFormat> format11; 58 BitField<14, 2, u32> size11; 59 60 BitField<16, 12, u32> attribute_mask; 61 62 // number of total attributes minus 1 63 BitField<28, 4, u32> max_attribute_index; 64 }; 65 GetFormatPipelineRegs::__anon72da46f2010866 VertexAttributeFormat GetFormat(std::size_t n) const { 67 VertexAttributeFormat formats[] = {format0, format1, format2, format3, 68 format4, format5, format6, format7, 69 format8, format9, format10, format11}; 70 return formats[n]; 71 } 72 GetNumElementsPipelineRegs::__anon72da46f2010873 u32 GetNumElements(std::size_t n) const { 74 u32 sizes[] = {size0, size1, size2, size3, size4, size5, 75 size6, size7, size8, size9, size10, size11}; 76 return sizes[n] + 1; 77 } 78 GetElementSizeInBytesPipelineRegs::__anon72da46f2010879 u32 GetElementSizeInBytes(std::size_t n) const { 80 return (GetFormat(n) == VertexAttributeFormat::FLOAT) 81 ? 4 82 : (GetFormat(n) == VertexAttributeFormat::SHORT) ? 2 : 1; 83 } 84 GetStridePipelineRegs::__anon72da46f2010885 u32 GetStride(std::size_t n) const { 86 return GetNumElements(n) * GetElementSizeInBytes(n); 87 } 88 IsDefaultAttributePipelineRegs::__anon72da46f2010889 bool IsDefaultAttribute(std::size_t id) const { 90 return (id >= 12) || (attribute_mask & (1ULL << id)) != 0; 91 } 92 GetNumTotalAttributesPipelineRegs::__anon72da46f2010893 u32 GetNumTotalAttributes() const { 94 return max_attribute_index + 1; 95 } 96 97 // Attribute loaders map the source vertex data to input attributes 98 // This e.g. allows to load different attributes from different memory locations 99 struct { 100 // Source attribute data offset from the base address 101 BitField<0, 28, u32> data_offset; 102 103 union { 104 BitField<0, 4, u32> comp0; 105 BitField<4, 4, u32> comp1; 106 BitField<8, 4, u32> comp2; 107 BitField<12, 4, u32> comp3; 108 BitField<16, 4, u32> comp4; 109 BitField<20, 4, u32> comp5; 110 BitField<24, 4, u32> comp6; 111 BitField<28, 4, u32> comp7; 112 }; 113 114 union { 115 BitField<0, 4, u32> comp8; 116 BitField<4, 4, u32> comp9; 117 BitField<8, 4, u32> comp10; 118 BitField<12, 4, u32> comp11; 119 120 // bytes for a single vertex in this loader 121 BitField<16, 8, u32> byte_count; 122 123 BitField<28, 4, u32> component_count; 124 }; 125 GetComponentPipelineRegs::__anon72da46f20108::__anon72da46f20408126 u32 GetComponent(std::size_t n) const { 127 u32 components[] = {comp0, comp1, comp2, comp3, comp4, comp5, 128 comp6, comp7, comp8, comp9, comp10, comp11}; 129 return components[n]; 130 } 131 } attribute_loaders[12]; 132 } vertex_attributes; 133 134 struct { 135 enum IndexFormat : u32 { 136 BYTE = 0, 137 SHORT = 1, 138 }; 139 140 union { 141 BitField<0, 28, u32> offset; // relative to base attribute address 142 BitField<28, 3, u32> unused; 143 BitField<31, 1, IndexFormat> format; 144 }; 145 } index_array; 146 147 // Number of vertices to render 148 u32 num_vertices; 149 150 enum class UseGS : u32 { 151 No = 0, 152 Yes = 2, 153 }; 154 155 union { 156 BitField<0, 2, UseGS> use_gs; 157 BitField<31, 1, u32> variable_primitive; 158 }; 159 160 // The index of the first vertex to render 161 u32 vertex_offset; 162 163 INSERT_PADDING_WORDS(0x3); 164 165 // These two trigger rendering of triangles 166 u32 trigger_draw; 167 u32 trigger_draw_indexed; 168 169 INSERT_PADDING_WORDS(0x2); 170 171 // These registers are used to setup the default "fall-back" vertex shader attributes 172 struct { 173 // Index of the current default attribute 174 u32 index; 175 176 // Writing to these registers sets the "current" default attribute. 177 u32 set_value[3]; 178 } vs_default_attributes_setup; 179 180 INSERT_PADDING_WORDS(0x2); 181 182 struct { 183 // There are two channels that can be used to configure the next command buffer, which can 184 // be then executed by writing to the "trigger" registers. There are two reasons why a game 185 // might use this feature: 186 // 1) With this, an arbitrary number of additional command buffers may be executed in 187 // sequence without requiring any intervention of the CPU after the initial one is 188 // kicked off. 189 // 2) Games can configure these registers to provide a command list subroutine mechanism. 190 191 // TODO: verify the bit length of these two fields 192 // According to 3dbrew, the bit length of them are 21 and 29, respectively 193 BitField<0, 20, u32> size[2]; ///< Size (in bytes / 8) of each channel's command buffer 194 BitField<0, 28, u32> addr[2]; ///< Physical address / 8 of each channel's command buffer 195 u32 trigger[2]; ///< Triggers execution of the channel's command buffer when written to 196 GetSizePipelineRegs::__anon72da46f20b08197 unsigned GetSize(unsigned index) const { 198 ASSERT(index < 2); 199 return 8 * size[index]; 200 } 201 GetPhysicalAddressPipelineRegs::__anon72da46f20b08202 PAddr GetPhysicalAddress(unsigned index) const { 203 ASSERT(index < 2); 204 return (PAddr)(8 * addr[index]); 205 } 206 } command_buffer; 207 208 INSERT_PADDING_WORDS(4); 209 210 /// Number of input attributes to the vertex shader minus 1 211 BitField<0, 4, u32> max_input_attrib_index; 212 213 INSERT_PADDING_WORDS(1); 214 215 // The shader unit 3, which can be used for both vertex and geometry shader, gets its 216 // configuration depending on this register. If this is not set, unit 3 will share some 217 // configuration with other units. It is known that program code and swizzle pattern uploaded 218 // via regs.vs will be also uploaded to unit 3 if this is not set. Although very likely, it is 219 // still unclear whether uniforms and other configuration can be also shared. 220 BitField<0, 1, u32> gs_unit_exclusive_configuration; 221 222 enum class GPUMode : u32 { 223 Drawing = 0, 224 Configuring = 1, 225 }; 226 227 GPUMode gpu_mode; 228 229 INSERT_PADDING_WORDS(0x4); 230 BitField<0, 4, u32> vs_outmap_total_minus_1_a; 231 INSERT_PADDING_WORDS(0x6); 232 BitField<0, 4, u32> vs_outmap_total_minus_1_b; 233 234 enum class GSMode : u32 { 235 Point = 0, 236 VariablePrimitive = 1, 237 FixedPrimitive = 2, 238 }; 239 240 union { 241 BitField<0, 8, GSMode> mode; 242 BitField<8, 4, u32> fixed_vertex_num_minus_1; 243 BitField<12, 4, u32> stride_minus_1; 244 BitField<16, 4, u32> start_index; 245 } gs_config; 246 247 INSERT_PADDING_WORDS(0x1); 248 249 u32 variable_vertex_main_num_minus_1; 250 251 INSERT_PADDING_WORDS(0x9); 252 253 enum class TriangleTopology : u32 { 254 List = 0, 255 Strip = 1, 256 Fan = 2, 257 Shader = 3, // Programmable setup unit implemented in a geometry shader 258 }; 259 260 BitField<8, 2, TriangleTopology> triangle_topology; 261 262 u32 restart_primitive; 263 264 INSERT_PADDING_WORDS(0x20); 265 }; 266 267 static_assert(sizeof(PipelineRegs) == 0x80 * sizeof(u32), "PipelineRegs struct has incorrect size"); 268 269 } // namespace Pica 270