1 // SPDX-License-Identifier: BSD-3-Clause
2 //
3 // copyright-holders:Nicola Salmoria
4 /***************************************************************************
5
6 sn76496.c
7 by Nicola Salmoria
8 with contributions by others
9
10 Routines to emulate the:
11 Texas Instruments SN76489, SN76489A, SN76494/SN76496
12 ( Also known as, or at least compatible with, the TMS9919 and SN94624.)
13 and the Sega 'PSG' used on the Master System, Game Gear, and Megadrive/Genesis
14 This chip is known as the Programmable Sound Generator, or PSG, and is a 4
15 channel sound generator, with three squarewave channels and a noise/arbitrary
16 duty cycle channel.
17
18 Noise emulation for all verified chips should be accurate:
19
20 ** SN76489 uses a 15-bit shift register with taps on bits D and E, output on E,
21 XOR function.
22 It uses a 15-bit ring buffer for periodic noise/arbitrary duty cycle.
23 Its output is inverted.
24 ** SN94624 is the same as SN76489 but lacks the /8 divider on its clock input.
25 ** SN76489A uses a 15-bit shift register with taps on bits D and E, output on F,
26 XOR function.
27 It uses a 15-bit ring buffer for periodic noise/arbitrary duty cycle.
28 Its output is not inverted.
29 ** SN76494 is the same as SN76489A but lacks the /8 divider on its clock input.
30 ** SN76496 is identical in operation to the SN76489A, but the audio input on pin 9 is
31 documented.
32 All the TI-made PSG chips have an audio input line which is mixed with the 4 channels
33 of output. (It is undocumented and may not function properly on the sn76489, 76489a
34 and 76494; the sn76489a input is mentioned in datasheets for the tms5200)
35 All the TI-made PSG chips act as if the frequency was set to 0x400 if 0 is
36 written to the frequency register.
37 ** Sega Master System III/MD/Genesis PSG uses a 16-bit shift register with taps
38 on bits C and F, output on F
39 It uses a 16-bit ring buffer for periodic noise/arbitrary duty cycle.
40 (whether it uses an XOR or XNOR needs to be verified, assumed XOR)
41 (whether output is inverted or not needs to be verified, assumed to be inverted)
42 ** Sega Game Gear PSG is identical to the SMS3/MD/Genesis one except it has an
43 extra register for mapping which channels go to which speaker.
44 The register, connected to a z80 port, means:
45 for bits 7 6 5 4 3 2 1 0
46 L3 L2 L1 L0 R3 R2 R1 R0
47 Noise is an XOR function, and audio output is negated before being output.
48 All the Sega-made PSG chips act as if the frequency was set to 0 if 0 is written
49 to the frequency register.
50 ** NCR8496 (as used on the Tandy 1000) is similar to the SN76489 but with a
51 different noise LFSR pattern: taps on bits A and E, output on E, XNOR function
52 It uses a 15-bit ring buffer for periodic noise/arbitrary duty cycle.
53 Its output is inverted.
54 ** PSSJ-3 (as used on the later Tandy 1000 series computers) is the same as the
55 NCR8496 with the exception that its output is not inverted.
56
57 28/03/2005 : Sebastien Chevalier
58 Update th SN76496Write func, according to SN76489 doc found on SMSPower.
59 - On write with 0x80 set to 0, when LastRegister is other then TONE,
60 the function is similar than update with 0x80 set to 1
61
62 23/04/2007 : Lord Nightmare
63 Major update, implement all three different noise generation algorithms and a
64 set_variant call to discern among them.
65
66 28/04/2009 : Lord Nightmare
67 Add READY line readback; cleaned up struct a bit. Cleaned up comments.
68 Add more TODOs. Fixed some unsaved savestate related stuff.
69
70 04/11/2009 : Lord Nightmare
71 Changed the way that the invert works (it now selects between XOR and XNOR
72 for the taps), and added R->OldNoise to simulate the extra 0 that is always
73 output before the noise LFSR contents are after an LFSR reset.
74 This fixes SN76489/A to match chips. Added SN94624.
75
76 14/11/2009 : Lord Nightmare
77 Removed STEP mess, vastly simplifying the code. Made output bipolar rather
78 than always above the 0 line, but disabled that code due to pending issues.
79
80 16/11/2009 : Lord Nightmare
81 Fix screeching in regulus: When summing together four equal channels, the
82 size of the max amplitude per channel should be 1/4 of the max range, not
83 1/3. Added NCR8496.
84
85 18/11/2009 : Lord Nightmare
86 Modify Init functions to support negating the audio output. The gamegear
87 psg does this. Change gamegear and sega psgs to use XOR rather than XNOR
88 based on testing. Got rid of R->OldNoise and fixed taps accordingly.
89 Added stereo support for game gear.
90
91 15/01/2010 : Lord Nightmare
92 Fix an issue with SN76489 and SN76489A having the wrong periodic noise periods.
93 Note that properly emulating the noise cycle bit timing accurately may require
94 extensive rewriting.
95
96 24/01/2010: Lord Nightmare
97 Implement periodic noise as forcing one of the XNOR or XOR taps to 1 or 0 respectively.
98 Thanks to PlgDavid for providing samples which helped immensely here.
99 Added true clock divider emulation, so sn94624 and sn76494 run 8x faster than
100 the others, as in real life.
101
102 15/02/2010: Lord Nightmare & Michael Zapf (additional testing by PlgDavid)
103 Fix noise period when set to mirror channel 3 and channel 3 period is set to 0 (tested on hardware for noise, wave needs tests) - MZ
104 Fix phase of noise on sn94624 and sn76489; all chips use a standard XOR, the only inversion is the output itself - LN, Plgdavid
105 Thanks to PlgDavid and Michael Zapf for providing samples which helped immensely here.
106
107 23/02/2011: Lord Nightmare & Enik
108 Made it so the Sega PSG chips have a frequency of 0 if 0 is written to the
109 frequency register, while the others have 0x400 as before. Should fix a bug
110 or two on sega games, particularly Vigilante on Sega Master System. Verified
111 on SMS hardware.
112
113 27/06/2012: Michael Zapf
114 Converted to modern device, legacy devices were gradually removed afterwards.
115
116 16/09/2015: Lord Nightmare
117 Fix PSG chips to have volume reg inited on reset to 0x0 based on tests by
118 ValleyBell. Made Sega PSG chips start up with register 0x3 selected (volume
119 for channel 2) based on hardware tests by Nemesis.
120
121 26/08/2018: Lord Nightmare, Qbix, ValleyBell, NewRisingSun
122 * renamed the NCR8496 to its correct name, based on chip pictures on VGMPF
123 * fixed NCR8496 behavior on write to mirrored registers; unlike any of the
124 other variants, the NCR8496 seems to ignore writes to regs 1,3,5,6,7 if 0x80
125 is not set.
126 ***TODO: the above is NOT verified yet!***
127 * fixed NCR8496's noise lfsr behavior so it is only reset if the mode bit in
128 register 6 is changed.
129 * NCR8496's LFSR feedback function is an XNOR, which is now supported
130 * NCR8496's output is inverted (though PSSJ-3's output is not)
131 * add PSSJ-3 support for the later Tandy computers.
132
133 TODO: * Implement the TMS9919 - any difference to sn94624?
134 * Implement the T6W28; has registers in a weird order, needs writes
135 to be 'sanitized' first. Also is stereo, similar to game gear.
136 * Factor out common code so that the SAA1099 can share some code.
137
138 ***************************************************************************/
139
140 #include "emu.h"
141 #include "sn76496.h"
142
143 #define MAX_OUTPUT 0x7fff
144 //When you go over this create sample
145 #define RATE_MAX ( 1 << 30)
146
sn76496_base_device(const machine_config & mconfig,device_type type,const char * tag,int feedbackmask,int noisetap1,int noisetap2,bool negate,bool stereo,int clockdivider,bool ncr,bool sega,device_t * owner,uint32_t clock)147 sn76496_base_device::sn76496_base_device(const machine_config &mconfig,
148 device_type type,
149 const char *tag,
150 int feedbackmask,
151 int noisetap1,
152 int noisetap2,
153 bool negate,
154 bool stereo,
155 int clockdivider,
156 bool ncr,
157 bool sega,
158 device_t *owner,
159 uint32_t clock)
160 : device_t(mconfig, type, tag, owner, clock),
161 device_sound_interface(mconfig, *this),
162 m_ready_state(false),
163 m_feedback_mask(feedbackmask),
164 m_whitenoise_tap1(noisetap1),
165 m_whitenoise_tap2(noisetap2),
166 m_negate(negate),
167 m_stereo(stereo),
168 m_clock_divider(clockdivider),
169 m_ncr_style_psg(ncr),
170 m_sega_style_psg(sega),
171 m_last_register(0),
172 m_RNG(0),
173 m_current_clock(0),
174 m_stereo_mask(0x0),
175 m_cycles_to_ready(0),
176 sample_rate(0),
177 rate_add(0),
178 rate_counter(0)
179 {}
180
sn76496_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)181 sn76496_device::sn76496_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
182 : sn76496_base_device(mconfig, SN76496, tag, 0x10000, 0x04, 0x08, false, false, 8, false, true, owner, clock)
183 {
184 }
185
u8106_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)186 u8106_device::u8106_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
187 : sn76496_base_device(mconfig, U8106, tag, 0x4000, 0x01, 0x02, true, false, 8, false, true, owner, clock)
188 {
189 }
190
y2404_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)191 y2404_device::y2404_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
192 : sn76496_base_device(mconfig, Y2404, tag, 0x10000, 0x04, 0x08, false, false, 8, false, true, owner, clock)
193 {
194 }
195
sn76489_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)196 sn76489_device::sn76489_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
197 : sn76496_base_device(mconfig, SN76489, tag, 0x4000, 0x01, 0x02, true, false, 8, false, true, owner, clock)
198 {
199 }
200
sn76489a_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)201 sn76489a_device::sn76489a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
202 : sn76496_base_device(mconfig, SN76489A, tag, 0x10000, 0x04, 0x08, false, false, 8, false, true, owner, clock)
203 {
204 }
205
sn76494_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)206 sn76494_device::sn76494_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
207 : sn76496_base_device(mconfig, SN76494, tag, 0x10000, 0x04, 0x08, false, false, 1, false, true, owner, clock)
208 {
209 }
210
sn94624_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)211 sn94624_device::sn94624_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
212 : sn76496_base_device(mconfig, SN94624, tag, 0x4000, 0x01, 0x02, true, false, 1, false, true, owner, clock)
213 {
214 }
215
ncr8496_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)216 ncr8496_device::ncr8496_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
217 : sn76496_base_device(mconfig, NCR8496, tag, 0x8000, 0x02, 0x20, true, false, 8, true, true, owner, clock)
218 {
219 }
220
pssj3_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)221 pssj3_device::pssj3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
222 : sn76496_base_device(mconfig, PSSJ3, tag, 0x8000, 0x02, 0x20, false, false, 8, true, true, owner, clock)
223 {
224 }
225
gamegear_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)226 gamegear_device::gamegear_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
227 : sn76496_base_device(mconfig, GAMEGEAR, tag, 0x8000, 0x01, 0x08, true, true, 8, false, false, owner, clock)
228 {
229 }
230
segapsg_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)231 segapsg_device::segapsg_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
232 : sn76496_base_device(mconfig, SEGAPSG, tag, 0x8000, 0x01, 0x08, true, false, 8, false, false, owner, clock)
233 {
234 }
235
device_start()236 void sn76496_base_device::device_start()
237 {
238 sample_rate = clock()/2;
239 rate_add = RATE_MAX;
240 rate_counter = 0;
241
242 int i;
243 double out;
244 int gain;
245
246 //m_ready_handler.resolve_safe();
247
248 //m_sound = machine().sound().stream_alloc(*this, 0, (m_stereo? 2:1), sample_rate);
249
250 for (i = 0; i < 4; i++) m_volume[i] = 0;
251
252 m_last_register = m_sega_style_psg?3:0; // Sega VDP PSG defaults to selected period reg for 2nd channel
253 for (i = 0; i < 8; i+=2)
254 {
255 m_register[i] = 0;
256 m_register[i + 1] = 0x0; // volume = 0x0 (max volume) on reset; this needs testing on chips other than SN76489A and Sega VDP PSG
257 }
258
259 for (i = 0; i < 4; i++)
260 {
261 m_output[i] = 0;
262 m_period[i] = 0;
263 m_count[i] = 0;
264 }
265
266 m_RNG = m_feedback_mask;
267 m_output[3] = m_RNG & 1;
268
269 m_cycles_to_ready = 1; // assume ready is not active immediately on init. is this correct?
270 m_stereo_mask = 0xFF; // all channels enabled
271 m_current_clock = m_clock_divider-1;
272
273 // set gain
274 gain = 0;
275
276 gain &= 0xff;
277
278 // increase max output basing on gain (0.2 dB per step)
279 out = MAX_OUTPUT / 4; // four channels, each gets 1/4 of the total range
280 while (gain-- > 0)
281 out *= 1.023292992; // = (10 ^ (0.2/20))
282
283 // build volume table (2dB per step)
284 for (i = 0; i < 15; i++)
285 {
286 // limit volume to avoid clipping
287 if (out > MAX_OUTPUT / 4) m_vol_table[i] = MAX_OUTPUT / 4;
288 else m_vol_table[i] = static_cast<int32_t>(out);
289
290 out /= 1.258925412; /* = 10 ^ (2/20) = 2dB */
291 }
292 m_vol_table[15] = 0;
293
294 m_ready_state = true;
295
296 //register_for_save_states();
297 }
298
device_clock_changed()299 void sn76496_base_device::device_clock_changed()
300 {
301 // m_sound->set_sample_rate(clock()/2);
302 }
303
WRITE8_MEMBER(sn76496_base_device::stereo_w)304 WRITE8_MEMBER( sn76496_base_device::stereo_w )
305 {
306 // m_sound->update();
307 // if (m_stereo) m_stereo_mask = data;
308 // else fatalerror("sn76496_base_device: Call to stereo write with mono chip!\n");
309 }
310
write(uint8_t data)311 void sn76496_base_device::write(uint8_t data)
312 {
313 int n, r, c;
314
315 // update the output buffer before changing the registers
316 // m_sound->update();
317
318 // set number of cycles until READY is active; this is always one
319 // 'sample', i.e. it equals the clock divider exactly
320 m_cycles_to_ready = 1;
321
322 if (data & 0x80)
323 {
324 r = (data & 0x70) >> 4;
325 m_last_register = r;
326 if (((m_ncr_style_psg) && (r == 6)) && ((data&0x04) != (m_register[6]&0x04))) m_RNG = m_feedback_mask;
327 m_register[r] = (m_register[r] & 0x3f0) | (data & 0x0f);
328 }
329 else
330 {
331 r = m_last_register;
332 if ((m_ncr_style_psg) && ((r & 1) || (r == 6))) return; // NCR8496 ignores writes to regs 1, 3, 5, 6 and 7 with bit 7 clear
333 }
334
335 c = r >> 1;
336 switch (r)
337 {
338 case 0: // tone 0: frequency
339 case 2: // tone 1: frequency
340 case 4: // tone 2: frequency
341 if ((data & 0x80) == 0) m_register[r] = (m_register[r] & 0x0f) | ((data & 0x3f) << 4);
342 if ((m_register[r] != 0) || (!m_sega_style_psg)) m_period[c] = m_register[r];
343 else m_period[c] = 0x400;
344
345 if (r == 4)
346 {
347 // update noise shift frequency
348 if ((m_register[6] & 0x03) == 0x03) m_period[3] = m_period[2]<<1;
349 }
350 break;
351 case 1: // tone 0: volume
352 case 3: // tone 1: volume
353 case 5: // tone 2: volume
354 case 7: // noise: volume
355 m_volume[c] = m_vol_table[data & 0x0f];
356 if ((data & 0x80) == 0) m_register[r] = (m_register[r] & 0x3f0) | (data & 0x0f);
357 break;
358 case 6: // noise: frequency, mode
359 {
360 if ((data & 0x80) == 0) logerror("sn76496_base_device: write to reg 6 with bit 7 clear; data was %03x, new write is %02x! report this to LN!\n", m_register[6], data);
361 if ((data & 0x80) == 0) m_register[r] = (m_register[r] & 0x3f0) | (data & 0x0f);
362 n = m_register[6];
363 // N/512,N/1024,N/2048,Tone #3 output
364 m_period[3] = ((n&3) == 3)? (m_period[2]<<1) : (1 << (5+(n&3)));
365 if (!(m_ncr_style_psg)) m_RNG = m_feedback_mask;
366 }
367 break;
368 }
369 }
370
WRITE8_MEMBER(sn76496_base_device::write)371 WRITE8_MEMBER( sn76496_base_device::write )
372 {
373 write(data);
374 }
375
in_noise_mode()376 inline bool sn76496_base_device::in_noise_mode()
377 {
378 return ((m_register[6] & 4)!=0);
379 }
380
countdown_cycles()381 void sn76496_base_device::countdown_cycles()
382 {
383 if (m_cycles_to_ready > 0)
384 {
385 m_cycles_to_ready--;
386 //if (m_ready_state==true) m_ready_handler(CLEAR_LINE);
387 m_ready_state = false;
388 }
389 else
390 {
391 //if (m_ready_state==false) m_ready_handler(ASSERT_LINE);
392 m_ready_state = true;
393 }
394 }
395
sound_stream_update(sound_stream & stream,stream_sample_t ** inputs,stream_sample_t ** outputs,int samples)396 void sn76496_base_device::sound_stream_update([[maybe_unused]] sound_stream &stream, [[maybe_unused]] stream_sample_t **inputs, stream_sample_t **outputs, int samples)
397 {
398 int i;
399 stream_sample_t *lbuffer = outputs[0];
400 stream_sample_t *rbuffer = (m_stereo)? outputs[1] : 0;//nullptr;
401
402 int16_t out;
403 int16_t out2 = 0;
404
405 while (samples > 0)
406 {
407 // clock chip once
408 if (m_current_clock > 0) // not ready for new divided clock
409 {
410 m_current_clock--;
411 }
412 else // ready for new divided clock, make a new sample
413 {
414 m_current_clock = m_clock_divider-1;
415 // decrement Cycles to READY by one
416 countdown_cycles();
417
418 // handle channels 0,1,2
419 for (i = 0; i < 3; i++)
420 {
421 m_count[i]--;
422 if (m_count[i] <= 0)
423 {
424 m_output[i] ^= 1;
425 m_count[i] = m_period[i];
426 }
427 }
428
429 // handle channel 3
430 m_count[3]--;
431 if (m_count[3] <= 0)
432 {
433 // if noisemode is 1, both taps are enabled
434 // if noisemode is 0, the lower tap, whitenoisetap2, is held at 0
435 // The != was a bit-XOR (^) before
436 if (((m_RNG & m_whitenoise_tap1) != 0) != ((static_cast<int32_t>(m_RNG & m_whitenoise_tap2) != (m_ncr_style_psg ? m_whitenoise_tap2 : 0)) && in_noise_mode())) {
437 m_RNG >>= 1;
438 m_RNG |= m_feedback_mask;
439 } else {
440 m_RNG >>= 1;
441 }
442 m_output[3] = m_RNG & 1;
443
444 m_count[3] = m_period[3];
445 }
446 }
447
448 //Skip final generation if you don't need an actual sample
449 rate_counter += rate_add;
450 if (rate_counter < RATE_MAX)
451 continue;
452 rate_counter -= RATE_MAX;
453
454 if (m_stereo)
455 {
456 out = ((((m_stereo_mask & 0x10)!=0) && (m_output[0]!=0))? m_volume[0] : 0)
457 + ((((m_stereo_mask & 0x20)!=0) && (m_output[1]!=0))? m_volume[1] : 0)
458 + ((((m_stereo_mask & 0x40)!=0) && (m_output[2]!=0))? m_volume[2] : 0)
459 + ((((m_stereo_mask & 0x80)!=0) && (m_output[3]!=0))? m_volume[3] : 0);
460
461 out2= ((((m_stereo_mask & 0x1)!=0) && (m_output[0]!=0))? m_volume[0] : 0)
462 + ((((m_stereo_mask & 0x2)!=0) && (m_output[1]!=0))? m_volume[1] : 0)
463 + ((((m_stereo_mask & 0x4)!=0) && (m_output[2]!=0))? m_volume[2] : 0)
464 + ((((m_stereo_mask & 0x8)!=0) && (m_output[3]!=0))? m_volume[3] : 0);
465 }
466 else
467 {
468 out= ((m_output[0]!=0)? m_volume[0]:0)
469 +((m_output[1]!=0)? m_volume[1]:0)
470 +((m_output[2]!=0)? m_volume[2]:0)
471 +((m_output[3]!=0)? m_volume[3]:0);
472 }
473
474 if (m_negate) { out = -out; out2 = -out2; }
475 *(lbuffer++) = out;
476 if (m_stereo) *(rbuffer++) = out2;
477 samples--;
478 }
479 }
480
481
convert_samplerate(int32_t target_rate)482 void sn76496_base_device::convert_samplerate(int32_t target_rate) {
483 //Simple 10 bit shift for samplerate conversion
484 rate_add = (int32_t)( RATE_MAX * (target_rate / (double)sample_rate) );
485 rate_counter = 0;
486 }
487
register_for_save_states()488 void sn76496_base_device::register_for_save_states()
489 {
490 save_item(NAME(m_vol_table));
491 save_item(NAME(m_register));
492 save_item(NAME(m_last_register));
493 save_item(NAME(m_volume));
494 save_item(NAME(m_RNG));
495 // save_item(NAME(m_clock_divider));
496 save_item(NAME(m_current_clock));
497 // save_item(NAME(m_feedback_mask));
498 // save_item(NAME(m_whitenoise_tap1));
499 // save_item(NAME(m_whitenoise_tap2));
500 // save_item(NAME(m_negate));
501 // save_item(NAME(m_stereo));
502 save_item(NAME(m_stereo_mask));
503 save_item(NAME(m_period));
504 save_item(NAME(m_count));
505 save_item(NAME(m_output));
506 save_item(NAME(m_cycles_to_ready));
507 // save_item(NAME(m_sega_style_psg));
508 }
509
510 DEFINE_DEVICE_TYPE(SN76496, sn76496_device, "sn76496", "SN76496")
511 DEFINE_DEVICE_TYPE(U8106, u8106_device, "u8106", "U8106")
512 DEFINE_DEVICE_TYPE(Y2404, y2404_device, "y2404", "Y2404")
513 DEFINE_DEVICE_TYPE(SN76489, sn76489_device, "sn76489", "SN76489")
514 DEFINE_DEVICE_TYPE(SN76489A, sn76489a_device, "sn76489a", "SN76489A")
515 DEFINE_DEVICE_TYPE(SN76494, sn76494_device, "sn76494", "SN76494")
516 DEFINE_DEVICE_TYPE(SN94624, sn94624_device, "sn94624", "SN94624")
517 DEFINE_DEVICE_TYPE(NCR8496, ncr8496_device, "ncr8496", "NCR8496")
518 DEFINE_DEVICE_TYPE(PSSJ3, pssj3_device, "pssj3", "PSSJ-3")
519 DEFINE_DEVICE_TYPE(GAMEGEAR, gamegear_device, "gamegear_psg", "Game Gear PSG")
520 DEFINE_DEVICE_TYPE(SEGAPSG, segapsg_device, "segapsg", "Sega VDP PSG")
521
522