1 #ifndef UAE_CPU_PREFETCH_H
2 #define UAE_CPU_PREFETCH_H
3
4 #include "uae/types.h"
5
6 #ifdef CPUEMU_20
7
8 extern uae_u32 get_word_020_prefetch (int);
9 extern void continue_020_prefetch(void);
10
next_iword_020_prefetch(void)11 STATIC_INLINE uae_u32 next_iword_020_prefetch (void)
12 {
13 uae_u32 r = get_word_020_prefetch (0);
14 m68k_incpci (2);
15 return r;
16 }
next_ilong_020_prefetch(void)17 STATIC_INLINE uae_u32 next_ilong_020_prefetch (void)
18 {
19 uae_u32 r = next_iword_020_prefetch () << 16;
20 r |= next_iword_020_prefetch ();
21 return r;
22 }
23
get_long_020_prefetch(int o)24 STATIC_INLINE uae_u32 get_long_020_prefetch (int o)
25 {
26 uae_u32 r = get_word_020_prefetch (o) << 16;
27 r |= get_word_020_prefetch (o + 2);
28 return r;
29 }
30
31 #endif
32
33 #ifdef CPUEMU_21
34
limit_cycles_ce020(int clocks)35 STATIC_INLINE void limit_cycles_ce020(int clocks)
36 {
37 #if 0
38 int cycs = clocks * cpucycleunit;
39 int diff = regs.ce020endcycle - regs.ce020startcycle;
40 if (diff <= cycs)
41 return;
42 regs.ce020startcycle = regs.ce020endcycle - cycs;
43 #endif
44 }
45
limit_all_cycles_ce020(void)46 STATIC_INLINE void limit_all_cycles_ce020(void)
47 {
48 #if 0
49 regs.ce020startcycle = regs.ce020endcycle;
50 #endif
51 }
52
53 // only for CPU internal cycles
do_cycles_ce020_internal(int clocks)54 STATIC_INLINE void do_cycles_ce020_internal(int clocks)
55 {
56 //fprintf ( stderr , "do_cycles_ce020_internal %d sp=%d" , clocks , currprefs.m68k_speed );
57 if (currprefs.m68k_speed < 0) {
58 regs.ce020extracycles += clocks;
59 return;
60 }
61 int cycs = clocks * cpucycleunit;
62 //fprintf ( stderr , "do_cycles_ce020_internal %d %d" , cycs , regs.ce020memcycles );
63 int diff = regs.ce020endcycle - regs.ce020startcycle;
64 if (diff > 0) {
65 if (diff >= cycs) {
66 regs.ce020startcycle += cycs;
67 return;
68 }
69 regs.ce020startcycle = regs.ce020endcycle;
70 cycs -= diff;
71 }
72 #if 0
73 if (regs.ce020memcycles > 0) {
74 if (regs.ce020memcycles >= cycs) {
75 regs.ce020memcycles -= cycs;
76 return;
77 }
78 cycs = cycs - regs.ce020memcycles;
79 }
80 //fprintf ( stderr , " -> %d\n" , cycs );
81 regs.ce020memcycles = 0;
82 #endif
83 x_do_cycles (cycs);
84 }
85
do_cycles_ce020_mem(int clocks,uae_u32 val)86 STATIC_INLINE void do_cycles_ce020_mem (int clocks, uae_u32 val)
87 {
88 x_do_cycles_post (clocks * cpucycleunit, val);
89 }
90
91 #if 0
92 STATIC_INLINE void do_head_cycles_ce020 (int h)
93 {
94 if (regs.ce020_tail) {
95 int cycs = regs.ce020_tail_cycles - get_cycles ();
96 if (cycs < 0)
97 cycs = 0;
98 cycs -= h * cpucycleunit;
99 if (cycs)
100 x_do_cycles (cycs < 0 ? -cycs : cycs);
101 } else if (h > 0) {
102 do_cycles_ce020 (h);
103 }
104 }
105 #endif
106
get_long_ce020(uaecptr addr)107 STATIC_INLINE uae_u32 get_long_ce020 (uaecptr addr)
108 {
109 return mem_access_delay_long_read_ce020 (addr);
110 }
get_word_ce020(uaecptr addr)111 STATIC_INLINE uae_u32 get_word_ce020 (uaecptr addr)
112 {
113 return mem_access_delay_word_read_ce020 (addr);
114 }
get_byte_ce020(uaecptr addr)115 STATIC_INLINE uae_u32 get_byte_ce020 (uaecptr addr)
116 {
117 return mem_access_delay_byte_read_ce020 (addr);
118 }
119
put_long_ce020(uaecptr addr,uae_u32 v)120 STATIC_INLINE void put_long_ce020 (uaecptr addr, uae_u32 v)
121 {
122 mem_access_delay_long_write_ce020 (addr, v);
123 }
put_word_ce020(uaecptr addr,uae_u32 v)124 STATIC_INLINE void put_word_ce020 (uaecptr addr, uae_u32 v)
125 {
126 mem_access_delay_word_write_ce020 (addr, v);
127 }
put_byte_ce020(uaecptr addr,uae_u32 v)128 STATIC_INLINE void put_byte_ce020 (uaecptr addr, uae_u32 v)
129 {
130 mem_access_delay_byte_write_ce020 (addr, v);
131 }
132
133 extern void continue_ce020_prefetch(void);
134 extern uae_u32 get_word_ce020_prefetch(int);
135 extern uae_u32 get_word_ce020_prefetch_opcode(int);
136
get_long_ce020_prefetch(int o)137 STATIC_INLINE uae_u32 get_long_ce020_prefetch (int o)
138 {
139 uae_u32 v;
140 uae_u16 tmp;
141 v = get_word_ce020_prefetch (o) << 16;
142 tmp = regs.db;
143 v |= get_word_ce020_prefetch (o + 2);
144 regs.db = tmp;
145 return v;
146 }
147
next_iword_020ce(void)148 STATIC_INLINE uae_u32 next_iword_020ce (void)
149 {
150 uae_u32 r = get_word_ce020_prefetch (0);
151 m68k_incpci (2);
152 return r;
153 }
next_ilong_020ce(void)154 STATIC_INLINE uae_u32 next_ilong_020ce (void)
155 {
156 uae_u32 r = get_long_ce020_prefetch (0);
157 m68k_incpci (4);
158 return r;
159 }
160
m68k_do_bsr_ce020(uaecptr oldpc,uae_s32 offset)161 STATIC_INLINE void m68k_do_bsr_ce020 (uaecptr oldpc, uae_s32 offset)
162 {
163 m68k_areg (regs, 7) -= 4;
164 x_put_long (m68k_areg (regs, 7), oldpc);
165 m68k_incpci (offset);
166 }
m68k_do_rts_ce020(void)167 STATIC_INLINE void m68k_do_rts_ce020 (void)
168 {
169 m68k_setpci (x_get_long (m68k_areg (regs, 7)));
170 m68k_areg (regs, 7) += 4;
171 }
172
173
174 #endif
175
176 #ifdef CPUEMU_22
177
178 extern void continue_030_prefetch(void);
179 extern uae_u32 get_word_030_prefetch(int);
180
put_long_030(uaecptr addr,uae_u32 v)181 STATIC_INLINE void put_long_030(uaecptr addr, uae_u32 v)
182 {
183 write_data_030_lput(addr, v);
184 }
put_word_030(uaecptr addr,uae_u32 v)185 STATIC_INLINE void put_word_030(uaecptr addr, uae_u32 v)
186 {
187 write_data_030_wput(addr, v);
188 }
put_byte_030(uaecptr addr,uae_u32 v)189 STATIC_INLINE void put_byte_030(uaecptr addr, uae_u32 v)
190 {
191 write_data_030_bput(addr, v);
192 }
get_long_030(uaecptr addr)193 STATIC_INLINE uae_u32 get_long_030(uaecptr addr)
194 {
195 return read_data_030_lget(addr);
196 }
get_word_030(uaecptr addr)197 STATIC_INLINE uae_u32 get_word_030(uaecptr addr)
198 {
199 return read_data_030_wget(addr);
200 }
get_byte_030(uaecptr addr)201 STATIC_INLINE uae_u32 get_byte_030(uaecptr addr)
202 {
203 return read_data_030_bget(addr);
204 }
205
get_long_030_prefetch(int o)206 STATIC_INLINE uae_u32 get_long_030_prefetch(int o)
207 {
208 uae_u32 v;
209 v = get_word_030_prefetch(o) << 16;
210 v |= get_word_030_prefetch(o + 2);
211 return v;
212 }
213
next_iword_030_prefetch(void)214 STATIC_INLINE uae_u32 next_iword_030_prefetch(void)
215 {
216 uae_u32 r = get_word_030_prefetch(0);
217 m68k_incpci(2);
218 return r;
219 }
next_ilong_030_prefetch(void)220 STATIC_INLINE uae_u32 next_ilong_030_prefetch(void)
221 {
222 uae_u32 r = get_long_030_prefetch(0);
223 m68k_incpci(4);
224 return r;
225 }
226
m68k_do_bsr_030(uaecptr oldpc,uae_s32 offset)227 STATIC_INLINE void m68k_do_bsr_030(uaecptr oldpc, uae_s32 offset)
228 {
229 m68k_areg(regs, 7) -= 4;
230 put_long_030(m68k_areg(regs, 7), oldpc);
231 m68k_incpci(offset);
232 }
m68k_do_rts_030(void)233 STATIC_INLINE void m68k_do_rts_030(void)
234 {
235 m68k_setpc(get_long_030(m68k_areg(regs, 7)));
236 m68k_areg(regs, 7) += 4;
237 }
238
239 #endif
240
241 #ifdef CPUEMU_23
242
243 extern void continue_ce030_prefetch(void);
244 extern uae_u32 get_word_ce030_prefetch(int);
245 extern uae_u32 get_word_ce030_prefetch_opcode(int);
246
get_long_ce030(uaecptr addr)247 STATIC_INLINE uae_u32 get_long_ce030 (uaecptr addr)
248 {
249 return mem_access_delay_long_read_ce020 (addr);
250 }
get_word_ce030(uaecptr addr)251 STATIC_INLINE uae_u32 get_word_ce030 (uaecptr addr)
252 {
253 return mem_access_delay_word_read_ce020 (addr);
254 }
get_byte_ce030(uaecptr addr)255 STATIC_INLINE uae_u32 get_byte_ce030 (uaecptr addr)
256 {
257 return mem_access_delay_byte_read_ce020 (addr);
258 }
259
put_long_ce030(uaecptr addr,uae_u32 v)260 STATIC_INLINE void put_long_ce030 (uaecptr addr, uae_u32 v)
261 {
262 mem_access_delay_long_write_ce020 (addr, v);
263 }
put_word_ce030(uaecptr addr,uae_u32 v)264 STATIC_INLINE void put_word_ce030 (uaecptr addr, uae_u32 v)
265 {
266 mem_access_delay_word_write_ce020 (addr, v);
267 }
put_byte_ce030(uaecptr addr,uae_u32 v)268 STATIC_INLINE void put_byte_ce030 (uaecptr addr, uae_u32 v)
269 {
270 mem_access_delay_byte_write_ce020 (addr, v);
271 }
272
273
put_long_dc030(uaecptr addr,uae_u32 v)274 STATIC_INLINE void put_long_dc030 (uaecptr addr, uae_u32 v)
275 {
276 write_dcache030_lput(addr, v, (regs.s ? 4 : 0) | 1);
277 }
put_word_dc030(uaecptr addr,uae_u32 v)278 STATIC_INLINE void put_word_dc030 (uaecptr addr, uae_u32 v)
279 {
280 write_dcache030_wput(addr, v, (regs.s ? 4 : 0) | 1);
281 }
put_byte_dc030(uaecptr addr,uae_u32 v)282 STATIC_INLINE void put_byte_dc030 (uaecptr addr, uae_u32 v)
283 {
284 write_dcache030_bput(addr, v, (regs.s ? 4 : 0) | 1);
285 }
get_long_dc030(uaecptr addr)286 STATIC_INLINE uae_u32 get_long_dc030 (uaecptr addr)
287 {
288 return read_dcache030_lget(addr, (regs.s ? 4 : 0) | 1);
289 }
get_word_dc030(uaecptr addr)290 STATIC_INLINE uae_u32 get_word_dc030 (uaecptr addr)
291 {
292 return read_dcache030_wget(addr, (regs.s ? 4 : 0) | 1);
293 }
get_byte_dc030(uaecptr addr)294 STATIC_INLINE uae_u32 get_byte_dc030 (uaecptr addr)
295 {
296 return read_dcache030_bget(addr, (regs.s ? 4 : 0) | 1);
297 }
298
get_long_ce030_prefetch(int o)299 STATIC_INLINE uae_u32 get_long_ce030_prefetch (int o)
300 {
301 uae_u32 v;
302 v = get_word_ce030_prefetch (o) << 16;
303 v |= get_word_ce030_prefetch (o + 2);
304 return v;
305 }
306
next_iword_030ce(void)307 STATIC_INLINE uae_u32 next_iword_030ce (void)
308 {
309 uae_u32 r = get_word_ce030_prefetch (0);
310 m68k_incpci (2);
311 return r;
312 }
next_ilong_030ce(void)313 STATIC_INLINE uae_u32 next_ilong_030ce (void)
314 {
315 uae_u32 r = get_long_ce030_prefetch (0);
316 m68k_incpci (4);
317 return r;
318 }
319
m68k_do_bsr_ce030(uaecptr oldpc,uae_s32 offset)320 STATIC_INLINE void m68k_do_bsr_ce030 (uaecptr oldpc, uae_s32 offset)
321 {
322 m68k_areg (regs, 7) -= 4;
323 x_put_long (m68k_areg (regs, 7), oldpc);
324 m68k_incpci (offset);
325 }
m68k_do_rts_ce030(void)326 STATIC_INLINE void m68k_do_rts_ce030 (void)
327 {
328 m68k_setpc (x_get_long (m68k_areg (regs, 7)));
329 m68k_areg (regs, 7) += 4;
330 }
331
332 #endif
333
334 #ifdef CPUEMU_11
335
get_word_000_prefetch(int o)336 STATIC_INLINE uae_u32 get_word_000_prefetch(int o)
337 {
338 uae_u32 v = regs.irc;
339 regs.irc = regs.db = get_wordi (m68k_getpci () + o);
340 return v;
341 }
get_byte_000(uaecptr addr)342 STATIC_INLINE uae_u32 get_byte_000(uaecptr addr)
343 {
344 uae_u32 v = get_byte (addr);
345 regs.db = (v << 8) | v;
346 return v;
347 }
get_word_000(uaecptr addr)348 STATIC_INLINE uae_u32 get_word_000(uaecptr addr)
349 {
350 uae_u32 v = get_word (addr);
351 regs.db = v;
352 return v;
353 }
put_byte_000(uaecptr addr,uae_u32 v)354 STATIC_INLINE void put_byte_000(uaecptr addr, uae_u32 v)
355 {
356 regs.db = (v << 8) | v;
357 put_byte (addr, v);
358 }
put_word_000(uaecptr addr,uae_u32 v)359 STATIC_INLINE void put_word_000(uaecptr addr, uae_u32 v)
360 {
361 regs.db = v;
362 put_word (addr, v);
363 }
364 #endif
365
366 #ifdef CPUEMU_13
367
do_cycles_ce000_internal(int clocks)368 STATIC_INLINE void do_cycles_ce000_internal(int clocks)
369 {
370 if (currprefs.m68k_speed < 0)
371 return;
372 x_do_cycles (clocks * cpucycleunit);
373 }
do_cycles_ce000(int clocks)374 STATIC_INLINE void do_cycles_ce000 (int clocks)
375 {
376 x_do_cycles (clocks * cpucycleunit);
377 }
378
ipl_fetch(void)379 STATIC_INLINE void ipl_fetch (void)
380 {
381 regs.ipl = regs.ipl_pin;
382 }
383
384 uae_u32 mem_access_delay_word_read (uaecptr addr);
385 uae_u32 mem_access_delay_wordi_read (uaecptr addr);
386 uae_u32 mem_access_delay_byte_read (uaecptr addr);
387 void mem_access_delay_byte_write (uaecptr addr, uae_u32 v);
388 void mem_access_delay_word_write (uaecptr addr, uae_u32 v);
389
get_long_ce000(uaecptr addr)390 STATIC_INLINE uae_u32 get_long_ce000 (uaecptr addr)
391 {
392 uae_u32 v = mem_access_delay_word_read (addr) << 16;
393 v |= mem_access_delay_word_read (addr + 2);
394 return v;
395 }
get_word_ce000(uaecptr addr)396 STATIC_INLINE uae_u32 get_word_ce000 (uaecptr addr)
397 {
398 return mem_access_delay_word_read (addr);
399 }
get_wordi_ce000(int offset)400 STATIC_INLINE uae_u32 get_wordi_ce000 (int offset)
401 {
402 return mem_access_delay_wordi_read (m68k_getpci () + offset);
403 }
get_byte_ce000(uaecptr addr)404 STATIC_INLINE uae_u32 get_byte_ce000 (uaecptr addr)
405 {
406 return mem_access_delay_byte_read (addr);
407 }
get_word_ce000_prefetch(int o)408 STATIC_INLINE uae_u32 get_word_ce000_prefetch (int o)
409 {
410 uae_u32 v = regs.irc;
411 regs.irc = regs.db = x_get_iword (o);
412 return v;
413 }
414
put_long_ce000(uaecptr addr,uae_u32 v)415 STATIC_INLINE void put_long_ce000 (uaecptr addr, uae_u32 v)
416 {
417 mem_access_delay_word_write (addr, v >> 16);
418 mem_access_delay_word_write (addr + 2, v);
419 }
put_word_ce000(uaecptr addr,uae_u32 v)420 STATIC_INLINE void put_word_ce000 (uaecptr addr, uae_u32 v)
421 {
422 mem_access_delay_word_write (addr, v);
423 }
put_byte_ce000(uaecptr addr,uae_u32 v)424 STATIC_INLINE void put_byte_ce000 (uaecptr addr, uae_u32 v)
425 {
426 mem_access_delay_byte_write (addr, v);
427 }
428
m68k_do_rts_ce(void)429 STATIC_INLINE void m68k_do_rts_ce (void)
430 {
431 uaecptr pc;
432 pc = x_get_word (m68k_areg (regs, 7)) << 16;
433 pc |= x_get_word (m68k_areg (regs, 7) + 2);
434 m68k_areg (regs, 7) += 4;
435 m68k_setpci (pc);
436 }
437
m68k_do_bsr_ce(uaecptr oldpc,uae_s32 offset)438 STATIC_INLINE void m68k_do_bsr_ce (uaecptr oldpc, uae_s32 offset)
439 {
440 m68k_areg (regs, 7) -= 4;
441 x_put_word (m68k_areg (regs, 7), oldpc >> 16);
442 x_put_word (m68k_areg (regs, 7) + 2, oldpc);
443 m68k_incpci (offset);
444 }
445
m68k_do_jsr_ce(uaecptr oldpc,uaecptr dest)446 STATIC_INLINE void m68k_do_jsr_ce (uaecptr oldpc, uaecptr dest)
447 {
448 m68k_areg (regs, 7) -= 4;
449 x_put_word (m68k_areg (regs, 7), oldpc >> 16);
450 x_put_word (m68k_areg (regs, 7) + 2, oldpc);
451 m68k_setpci (dest);
452 }
453
454 #endif
455
get_disp_ea_000(uae_u32 base,uae_u32 dp)456 STATIC_INLINE uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp)
457 {
458 int reg = (dp >> 12) & 15;
459 uae_s32 regd = regs.regs[reg];
460 if ((dp & 0x800) == 0)
461 regd = (uae_s32)(uae_s16)regd;
462 return base + (uae_s8)dp + regd;
463 }
464
465 #endif /* UAE_CPU_PREFETCH_H */
466