1 /* GENERAL2.C (c) Copyright Roger Bowler, 1994-2009 */
2 /* ESA/390 CPU Emulator */
3 /* Instructions N-Z */
4
5 /* (c) Copyright Peter Kuschnerus, 1999-2009 (UPT & CFC)*/
6
7 /* Interpretive Execution - (c) Copyright Jan Jaeger, 1999-2009 */
8 /* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2009 */
9
10 /*-------------------------------------------------------------------*/
11 /* This module implements general instructions N-Z of the */
12 /* S/370 and ESA/390 architectures, as described in the manuals */
13 /* GA22-7000-03 System/370 Principles of Operation */
14 /* SA22-7201-06 ESA/390 Principles of Operation */
15 /*-------------------------------------------------------------------*/
16
17 /*-------------------------------------------------------------------*/
18 /* Additional credits: */
19 /* Corrections to shift instructions by Jay Maynard, Jan Jaeger */
20 /* Branch tracing by Jan Jaeger */
21 /* Instruction decode by macros - Jan Jaeger */
22 /* Prevent TOD from going backwards in time - Jan Jaeger */
23 /* Fix STCKE instruction - Bernard van der Helm */
24 /* Instruction decode rework - Jan Jaeger */
25 /* Make STCK update the TOD clock - Jay Maynard */
26 /* Fix address wraparound in MVO - Jan Jaeger */
27 /* PLO instruction - Jan Jaeger */
28 /* Modifications for Interpretive Execution (SIE) by Jan Jaeger */
29 /* Clear TEA on data exception - Peter Kuschnerus v209*/
30 /*-------------------------------------------------------------------*/
31
32 #include "hstdinc.h"
33
34 #if !defined(_HENGINE_DLL_)
35 #define _HENGINE_DLL_
36 #endif
37
38 #if !defined(_GENERAL2_C_)
39 #define _GENERAL2_C_
40 #endif
41
42 #include "hercules.h"
43 #include "opcode.h"
44 #include "inline.h"
45 #include "clock.h"
46
47
48 /*-------------------------------------------------------------------*/
49 /* 16 OR - Or Register [RR] */
50 /*-------------------------------------------------------------------*/
DEF_INST(or_register)51 DEF_INST(or_register)
52 {
53 int r1, r2; /* Values of R fields */
54
55 RR0(inst, regs, r1, r2);
56
57 /* OR second operand with first and set condition code */
58 regs->psw.cc = ( regs->GR_L(r1) |= regs->GR_L(r2) ) ? 1 : 0;
59 }
60
61
62 /*-------------------------------------------------------------------*/
63 /* 56 O - Or [RX] */
64 /*-------------------------------------------------------------------*/
DEF_INST(or)65 DEF_INST(or)
66 {
67 int r1; /* Value of R field */
68 int b2; /* Base of effective addr */
69 VADR effective_addr2; /* Effective address */
70 U32 n; /* 32-bit operand values */
71
72 RX(inst, regs, r1, b2, effective_addr2);
73
74 /* Load second operand from operand address */
75 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
76
77 /* OR second operand with first and set condition code */
78 regs->psw.cc = ( regs->GR_L(r1) |= n ) ? 1 : 0;
79 }
80
81
82 /*-------------------------------------------------------------------*/
83 /* 96 OI - Or Immediate [SI] */
84 /*-------------------------------------------------------------------*/
DEF_INST(or_immediate)85 DEF_INST(or_immediate)
86 {
87 BYTE i2; /* Immediate operand byte */
88 int b1; /* Base of effective addr */
89 VADR effective_addr1; /* Effective address */
90 BYTE *dest; /* Pointer to target byte */
91
92 SI(inst, regs, i2, b1, effective_addr1);
93
94 ITIMER_SYNC(effective_addr1,1,regs);
95 /* Get byte mainstor address */
96 dest = MADDR (effective_addr1, b1, regs, ACCTYPE_WRITE, regs->psw.pkey );
97
98 /* OR byte with immediate operand, setting condition code */
99 regs->psw.cc = ((*dest |= i2) != 0);
100 ITIMER_UPDATE(effective_addr1,1,regs);
101 }
102
103
104 /*-------------------------------------------------------------------*/
105 /* D6 OC - Or Characters [SS] */
106 /*-------------------------------------------------------------------*/
DEF_INST(or_character)107 DEF_INST(or_character)
108 {
109 int len, len2, len3; /* Lengths to copy */
110 int b1, b2; /* Base register numbers */
111 VADR addr1, addr2; /* Virtual addresses */
112 BYTE *dest1, *dest2; /* Destination addresses */
113 BYTE *source1, *source2; /* Source addresses */
114 BYTE *sk1, *sk2; /* Storage key addresses */
115 int i; /* Loop counter */
116 int cc = 0; /* Condition code */
117
118 SS_L(inst, regs, len, b1, addr1, b2, addr2);
119
120 ITIMER_SYNC(addr1,len,regs);
121 ITIMER_SYNC(addr2,len,regs);
122
123 /* Quick out for 1 byte (no boundary crossed) */
124 if (unlikely(len == 0))
125 {
126 source1 = MADDR (addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
127 dest1 = MADDR (addr1, b1, regs, ACCTYPE_WRITE, regs->psw.pkey);
128 *dest1 |= *source1;
129 regs->psw.cc = (*dest1 != 0);
130 ITIMER_UPDATE(addr1,len,regs);
131 return;
132 }
133
134 /* There are several scenarios (in optimal order):
135 * (1) dest boundary and source boundary not crossed
136 * (2) dest boundary not crossed and source boundary crossed
137 * (3) dest boundary crossed and source boundary not crossed
138 * (4) dest boundary and source boundary are crossed
139 * (a) dest and source boundary cross at the same time
140 * (b) dest boundary crossed first
141 * (c) source boundary crossed first
142 */
143
144 /* Translate addresses of leftmost operand bytes */
145 dest1 = MADDRL (addr1, len+1, b1, regs, ACCTYPE_WRITE_SKP, regs->psw.pkey);
146 sk1 = regs->dat.storkey;
147 source1 = MADDR (addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
148
149 if ( NOCROSS2K(addr1,len) )
150 {
151 if ( NOCROSS2K(addr2,len) )
152 {
153 /* (1) - No boundaries are crossed */
154 for (i = 0; i <= len; i++)
155 if ((*dest1++ |= *source1++)) cc = 1;
156
157 }
158 else
159 {
160 /* (2) - Second operand crosses a boundary */
161 len2 = 0x800 - (addr2 & 0x7FF);
162 source2 = MADDR ((addr2 + len2) & ADDRESS_MAXWRAP(regs),
163 b2, regs, ACCTYPE_READ, regs->psw.pkey);
164 for ( i = 0; i < len2; i++)
165 if ((*dest1++ |= *source1++)) cc = 1;
166 len2 = len - len2;
167 for ( i = 0; i <= len2; i++)
168 if ((*dest1++ |= *source2++)) cc = 1;
169 }
170 *sk1 |= (STORKEY_REF | STORKEY_CHANGE);
171 }
172 else
173 {
174 /* First operand crosses a boundary */
175 len2 = 0x800 - (addr1 & 0x7FF);
176 dest2 = MADDR ((addr1 + len2) & ADDRESS_MAXWRAP(regs),
177 b1, regs, ACCTYPE_WRITE_SKP, regs->psw.pkey);
178 sk2 = regs->dat.storkey;
179
180 if ( NOCROSS2K(addr2,len) )
181 {
182 /* (3) - First operand crosses a boundary */
183 for ( i = 0; i < len2; i++)
184 if ((*dest1++ |= *source1++)) cc = 1;
185 len2 = len - len2;
186 for ( i = 0; i <= len2; i++)
187 if ((*dest2++ |= *source1++)) cc = 1;
188 }
189 else
190 {
191 /* (4) - Both operands cross a boundary */
192 len3 = 0x800 - (addr2 & 0x7FF);
193 source2 = MADDR ((addr2 + len3) & ADDRESS_MAXWRAP(regs),
194 b2, regs, ACCTYPE_READ, regs->psw.pkey);
195 if (len2 == len3)
196 {
197 /* (4a) - Both operands cross at the same time */
198 for ( i = 0; i < len2; i++)
199 if ((*dest1++ |= *source1++)) cc = 1;
200 len2 = len - len2;
201 for ( i = 0; i <= len2; i++)
202 if ((*dest2++ |= *source2++)) cc = 1;
203 }
204 else if (len2 < len3)
205 {
206 /* (4b) - First operand crosses first */
207 for ( i = 0; i < len2; i++)
208 if ((*dest1++ |= *source1++)) cc = 1;
209 len2 = len3 - len2;
210 for ( i = 0; i < len2; i++)
211 if ((*dest2++ |= *source1++)) cc = 1;
212 len2 = len - len3;
213 for ( i = 0; i <= len2; i++)
214 if ((*dest2++ |= *source2++)) cc = 1;
215 }
216 else
217 {
218 /* (4c) - Second operand crosses first */
219 for ( i = 0; i < len3; i++)
220 if ((*dest1++ |= *source1++)) cc = 1;
221 len3 = len2 - len3;
222 for ( i = 0; i < len3; i++)
223 if ((*dest1++ |= *source2++)) cc = 1;
224 len3 = len - len2;
225 for ( i = 0; i <= len3; i++)
226 if ((*dest2++ |= *source2++)) cc = 1;
227 }
228 }
229 *sk1 |= (STORKEY_REF | STORKEY_CHANGE);
230 *sk2 |= (STORKEY_REF | STORKEY_CHANGE);
231 }
232
233 regs->psw.cc = cc;
234
235 ITIMER_UPDATE(addr1,len,regs);
236
237 } /* end DEF_INST(or_character) */
238
239
240 /*-------------------------------------------------------------------*/
241 /* F2 PACK - Pack [SS] */
242 /*-------------------------------------------------------------------*/
DEF_INST(pack)243 DEF_INST(pack)
244 {
245 int l1, l2; /* Lenght values */
246 int b1, b2; /* Values of base registers */
247 VADR effective_addr1,
248 effective_addr2; /* Effective addresses */
249 int i, j; /* Loop counters */
250 BYTE sbyte; /* Source operand byte */
251 BYTE dbyte; /* Destination operand byte */
252
253 SS(inst, regs, l1, l2, b1, effective_addr1,
254 b2, effective_addr2);
255
256 /* If operand 1 crosses a page, make sure both pages are accessable */
257 if((effective_addr1 & PAGEFRAME_PAGEMASK) !=
258 ((effective_addr1 + l1) & PAGEFRAME_PAGEMASK))
259 ARCH_DEP(validate_operand) (effective_addr1, b1, l1, ACCTYPE_WRITE_SKP, regs);
260
261 /* If operand 2 crosses a page, make sure both pages are accessable */
262 if((effective_addr2 & PAGEFRAME_PAGEMASK) !=
263 ((effective_addr2 + l2) & PAGEFRAME_PAGEMASK))
264 ARCH_DEP(validate_operand) (effective_addr2, b2, l2, ACCTYPE_READ, regs);
265
266 /* Exchange the digits in the rightmost byte */
267 effective_addr1 += l1;
268 effective_addr2 += l2;
269 sbyte = ARCH_DEP(vfetchb) ( effective_addr2, b2, regs );
270 dbyte = (sbyte << 4) | (sbyte >> 4);
271 ARCH_DEP(vstoreb) ( dbyte, effective_addr1, b1, regs );
272
273 /* Process remaining bytes from right to left */
274 for (i = l1, j = l2; i > 0; i--)
275 {
276 /* Fetch source bytes from second operand */
277 if (j-- > 0)
278 {
279 sbyte = ARCH_DEP(vfetchb) ( --effective_addr2, b2, regs );
280 dbyte = sbyte & 0x0F;
281
282 if (j-- > 0)
283 {
284 effective_addr2 &= ADDRESS_MAXWRAP(regs);
285 sbyte = ARCH_DEP(vfetchb) ( --effective_addr2, b2, regs );
286 dbyte |= sbyte << 4;
287 }
288 }
289 else
290 {
291 dbyte = 0;
292 }
293
294 /* Store packed digits at first operand address */
295 ARCH_DEP(vstoreb) ( dbyte, --effective_addr1, b1, regs );
296
297 /* Wraparound according to addressing mode */
298 effective_addr1 &= ADDRESS_MAXWRAP(regs);
299 effective_addr2 &= ADDRESS_MAXWRAP(regs);
300
301 } /* end for(i) */
302
303 }
304
305
306 #if defined(FEATURE_PERFORM_LOCKED_OPERATION)
307 /*-------------------------------------------------------------------*/
308 /* EE PLO - Perform Locked Operation [SS] */
309 /*-------------------------------------------------------------------*/
DEF_INST(perform_locked_operation)310 DEF_INST(perform_locked_operation)
311 {
312 int r1, r3; /* Lenght values */
313 int b2, b4; /* Values of base registers */
314 VADR effective_addr2,
315 effective_addr4; /* Effective addresses */
316
317 SS(inst, regs, r1, r3, b2, effective_addr2,
318 b4, effective_addr4);
319
320 if(regs->GR_L(0) & PLO_GPR0_RESV)
321 regs->program_interrupt(regs, PGM_SPECIFICATION_EXCEPTION);
322
323 if(regs->GR_L(0) & PLO_GPR0_T)
324 switch(regs->GR_L(0) & PLO_GPR0_FC)
325 {
326 case PLO_CL:
327 case PLO_CLG:
328 case PLO_CS:
329 case PLO_CSG:
330 case PLO_DCS:
331 case PLO_DCSG:
332 case PLO_CSST:
333 case PLO_CSSTG:
334 case PLO_CSDST:
335 case PLO_CSDSTG:
336 case PLO_CSTST:
337 case PLO_CSTSTG:
338 #if defined(FEATURE_ESAME)
339 case PLO_CLGR:
340 case PLO_CLX:
341 case PLO_CSGR:
342 case PLO_CSX:
343 case PLO_DCSGR:
344 case PLO_DCSX:
345 case PLO_CSSTGR:
346 case PLO_CSSTX:
347 case PLO_CSDSTGR:
348 case PLO_CSDSTX:
349 case PLO_CSTSTGR:
350 case PLO_CSTSTX:
351 #endif /*defined(FEATURE_ESAME)*/
352
353 /* Indicate function supported */
354 regs->psw.cc = 0;
355 break;
356
357 default:
358 PTT(PTT_CL_ERR,"*PLO",regs->GR_L(0),regs->GR_L(r1),regs->psw.IA_L);
359 /* indicate function not supported */
360 regs->psw.cc = 3;
361 break;
362 }
363 else
364 {
365 /* gpr1/ar1 indentify the program lock token, which is used
366 to select a lock from the model dependent number of locks
367 in the configuration. We simply use 1 lock which is the
368 main storage access lock which is also used by CS, CDS
369 and TS. *JJ */
370 OBTAIN_MAINLOCK(regs);
371
372 switch(regs->GR_L(0) & PLO_GPR0_FC)
373 {
374 case PLO_CL:
375 regs->psw.cc = ARCH_DEP(plo_cl) (r1, r3,
376 effective_addr2, b2, effective_addr4, b4, regs);
377 break;
378 case PLO_CLG:
379 regs->psw.cc = ARCH_DEP(plo_clg) (r1, r3,
380 effective_addr2, b2, effective_addr4, b4, regs);
381 break;
382 case PLO_CS:
383 regs->psw.cc = ARCH_DEP(plo_cs) (r1, r3,
384 effective_addr2, b2, effective_addr4, b4, regs);
385 break;
386 case PLO_CSG:
387 regs->psw.cc = ARCH_DEP(plo_csg) (r1, r3,
388 effective_addr2, b2, effective_addr4, b4, regs);
389 break;
390 case PLO_DCS:
391 regs->psw.cc = ARCH_DEP(plo_dcs) (r1, r3,
392 effective_addr2, b2, effective_addr4, b4, regs);
393 break;
394 case PLO_DCSG:
395 regs->psw.cc = ARCH_DEP(plo_dcsg) (r1, r3,
396 effective_addr2, b2, effective_addr4, b4, regs);
397 break;
398 case PLO_CSST:
399 regs->psw.cc = ARCH_DEP(plo_csst) (r1, r3,
400 effective_addr2, b2, effective_addr4, b4, regs);
401 break;
402 case PLO_CSSTG:
403 regs->psw.cc = ARCH_DEP(plo_csstg) (r1, r3,
404 effective_addr2, b2, effective_addr4, b4, regs);
405 break;
406 case PLO_CSDST:
407 regs->psw.cc = ARCH_DEP(plo_csdst) (r1, r3,
408 effective_addr2, b2, effective_addr4, b4, regs);
409 break;
410 case PLO_CSDSTG:
411 regs->psw.cc = ARCH_DEP(plo_csdstg) (r1, r3,
412 effective_addr2, b2, effective_addr4, b4, regs);
413 break;
414 case PLO_CSTST:
415 regs->psw.cc = ARCH_DEP(plo_cstst) (r1, r3,
416 effective_addr2, b2, effective_addr4, b4, regs);
417 break;
418 case PLO_CSTSTG:
419 regs->psw.cc = ARCH_DEP(plo_cststg) (r1, r3,
420 effective_addr2, b2, effective_addr4, b4, regs);
421 break;
422 #if defined(FEATURE_ESAME)
423 case PLO_CLGR:
424 regs->psw.cc = ARCH_DEP(plo_clgr) (r1, r3,
425 effective_addr2, b2, effective_addr4, b4, regs);
426 break;
427 case PLO_CLX:
428 regs->psw.cc = ARCH_DEP(plo_clx) (r1, r3,
429 effective_addr2, b2, effective_addr4, b4, regs);
430 break;
431 case PLO_CSGR:
432 regs->psw.cc = ARCH_DEP(plo_csgr) (r1, r3,
433 effective_addr2, b2, effective_addr4, b4, regs);
434 break;
435 case PLO_CSX:
436 regs->psw.cc = ARCH_DEP(plo_csx) (r1, r3,
437 effective_addr2, b2, effective_addr4, b4, regs);
438 break;
439 case PLO_DCSGR:
440 regs->psw.cc = ARCH_DEP(plo_dcsgr) (r1, r3,
441 effective_addr2, b2, effective_addr4, b4, regs);
442 break;
443 case PLO_DCSX:
444 regs->psw.cc = ARCH_DEP(plo_dcsx) (r1, r3,
445 effective_addr2, b2, effective_addr4, b4, regs);
446 break;
447 case PLO_CSSTGR:
448 regs->psw.cc = ARCH_DEP(plo_csstgr) (r1, r3,
449 effective_addr2, b2, effective_addr4, b4, regs);
450 break;
451 case PLO_CSSTX:
452 regs->psw.cc = ARCH_DEP(plo_csstx) (r1, r3,
453 effective_addr2, b2, effective_addr4, b4, regs);
454 break;
455 case PLO_CSDSTGR:
456 regs->psw.cc = ARCH_DEP(plo_csdstgr) (r1, r3,
457 effective_addr2, b2, effective_addr4, b4, regs);
458 break;
459 case PLO_CSDSTX:
460 regs->psw.cc = ARCH_DEP(plo_csdstx) (r1, r3,
461 effective_addr2, b2, effective_addr4, b4, regs);
462 break;
463 case PLO_CSTSTGR:
464 regs->psw.cc = ARCH_DEP(plo_cststgr) (r1, r3,
465 effective_addr2, b2, effective_addr4, b4, regs);
466 break;
467 case PLO_CSTSTX:
468 regs->psw.cc = ARCH_DEP(plo_cststx) (r1, r3,
469 effective_addr2, b2, effective_addr4, b4, regs);
470 break;
471 #endif /*defined(FEATURE_ESAME)*/
472
473
474 default:
475 regs->program_interrupt(regs, PGM_SPECIFICATION_EXCEPTION);
476
477 }
478
479 /* Release main-storage access lock */
480 RELEASE_MAINLOCK(regs);
481
482 if(regs->psw.cc && sysblk.cpus > 1)
483 {
484 PTT(PTT_CL_CSF,"*PLO",regs->GR_L(0),regs->GR_L(r1),regs->psw.IA_L);
485 sched_yield();
486 }
487
488 }
489 }
490 #endif /*defined(FEATURE_PERFORM_LOCKED_OPERATION)*/
491
492
493 #if defined(FEATURE_STRING_INSTRUCTION)
494 /*-------------------------------------------------------------------*/
495 /* B25E SRST - Search String [RRE] */
496 /*-------------------------------------------------------------------*/
DEF_INST(search_string)497 DEF_INST(search_string)
498 {
499 int r1, r2; /* Values of R fields */
500 int i; /* Loop counter */
501 VADR addr1, addr2; /* End/start addresses */
502 BYTE sbyte; /* String character */
503 BYTE termchar; /* Terminating character */
504
505 RRE(inst, regs, r1, r2);
506
507 /* Program check if bits 0-23 of register 0 not zero */
508 if ((regs->GR_L(0) & 0xFFFFFF00) != 0)
509 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
510
511 /* Load string terminating character from register 0 bits 24-31 */
512 termchar = regs->GR_LHLCL(0);
513
514 /* Determine the operand end and start addresses */
515 addr1 = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
516 addr2 = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
517
518 /* Search up to 256 bytes or until end of operand */
519 for (i = 0; i < 0x100; i++)
520 {
521 /* If operand end address has been reached, return condition
522 code 2 and leave the R1 and R2 registers unchanged */
523 if (addr2 == addr1)
524 {
525 regs->psw.cc = 2;
526 return;
527 }
528
529 /* Fetch a byte from the operand */
530 sbyte = ARCH_DEP(vfetchb) ( addr2, r2, regs );
531
532 /* If the terminating character was found, return condition
533 code 1 and load the address of the character into R1 */
534 if (sbyte == termchar)
535 {
536 SET_GR_A(r1, regs, addr2);
537 regs->psw.cc = 1;
538 return;
539 }
540
541 /* Increment operand address */
542 addr2++;
543 addr2 &= ADDRESS_MAXWRAP(regs);
544
545 } /* end for(i) */
546
547 /* Set R2 to point to next character of operand */
548 SET_GR_A(r2, regs, addr2);
549
550 /* Return condition code 3 */
551 regs->psw.cc = 3;
552
553 } /* end DEF_INST(search_string) */
554 #endif /*defined(FEATURE_STRING_INSTRUCTION)*/
555
556
557 #if defined(FEATURE_ACCESS_REGISTERS)
558 /*-------------------------------------------------------------------*/
559 /* B24E SAR - Set Access Register [RRE] */
560 /*-------------------------------------------------------------------*/
DEF_INST(set_access_register)561 DEF_INST(set_access_register)
562 {
563 int r1, r2; /* Values of R fields */
564
565 RRE0(inst, regs, r1, r2);
566
567 /* Copy R2 general register to R1 access register */
568 regs->AR(r1) = regs->GR_L(r2);
569 SET_AEA_AR(regs, r1);
570 }
571 #endif /*defined(FEATURE_ACCESS_REGISTERS)*/
572
573
574 /*-------------------------------------------------------------------*/
575 /* 04 SPM - Set Program Mask [RR] */
576 /*-------------------------------------------------------------------*/
DEF_INST(set_program_mask)577 DEF_INST(set_program_mask)
578 {
579 int r1, r2; /* Values of R fields */
580
581 RR0(inst, regs, r1, r2);
582
583 /* Set condition code from bits 2-3 of R1 register */
584 regs->psw.cc = ( regs->GR_L(r1) & 0x30000000 ) >> 28;
585
586 /* Set program mask from bits 4-7 of R1 register */
587 regs->psw.progmask = ( regs->GR_L(r1) >> 24) & PSW_PROGMASK;
588 }
589
590
591 /*-------------------------------------------------------------------*/
592 /* 8F SLDA - Shift Left Double [RS] */
593 /*-------------------------------------------------------------------*/
DEF_INST(shift_left_double)594 DEF_INST(shift_left_double)
595 {
596 int r1, r3; /* Register numbers */
597 int b2; /* effective address base */
598 VADR effective_addr2; /* effective address */
599 U32 n; /* 32-bit operand values */
600 U64 dreg; /* Double register work area */
601 U32 h, i, j, m; /* Integer work areas */
602
603 RS(inst, regs, r1, r3, b2, effective_addr2);
604
605 ODD_CHECK(r1, regs);
606
607 /* Use rightmost six bits of operand address as shift count */
608 n = effective_addr2 & 0x3F;
609
610 /* Load the signed value from the R1 and R1+1 registers */
611 dreg = (U64)regs->GR_L(r1) << 32 | regs->GR_L(r1+1);
612 m = ((S64)dreg < 0) ? 1 : 0;
613
614 /* Shift the numeric portion of the value */
615 for (i = 0, j = 0; i < n; i++)
616 {
617 /* Shift bits 1-63 left one bit position */
618 dreg <<= 1;
619
620 /* Overflow if bit shifted out is unlike the sign bit */
621 h = ((S64)dreg < 0) ? 1 : 0;
622 if (h != m)
623 j = 1;
624 }
625
626 /* Load updated value into the R1 and R1+1 registers */
627 regs->GR_L(r1) = (dreg >> 32) & 0x7FFFFFFF;
628 if (m)
629 regs->GR_L(r1) |= 0x80000000;
630 regs->GR_L(r1+1) = dreg & 0xFFFFFFFF;
631
632 /* Condition code 3 and program check if overflow occurred */
633 if (j)
634 {
635 regs->psw.cc = 3;
636 if ( FOMASK(®s->psw) )
637 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
638 return;
639 }
640
641 /* Set the condition code */
642 regs->psw.cc = (S64)dreg > 0 ? 2 : (S64)dreg < 0 ? 1 : 0;
643
644 }
645
646
647 /*-------------------------------------------------------------------*/
648 /* 8D SLDL - Shift Left Double Logical [RS] */
649 /*-------------------------------------------------------------------*/
DEF_INST(shift_left_double_logical)650 DEF_INST(shift_left_double_logical)
651 {
652 int r1, r3; /* Register numbers */
653 int b2; /* effective address base */
654 VADR effective_addr2; /* effective address */
655 U32 n; /* 32-bit operand values */
656 U64 dreg; /* Double register work area */
657
658 RS(inst, regs, r1, r3, b2, effective_addr2);
659
660 ODD_CHECK(r1, regs);
661
662 /* Use rightmost six bits of operand address as shift count */
663 n = effective_addr2 & 0x3F;
664
665 /* Shift the R1 and R1+1 registers */
666 dreg = (U64)regs->GR_L(r1) << 32 | regs->GR_L(r1+1);
667 dreg <<= n;
668 regs->GR_L(r1) = dreg >> 32;
669 regs->GR_L(r1+1) = dreg & 0xFFFFFFFF;
670
671 }
672
673
674 /*-------------------------------------------------------------------*/
675 /* 8B SLA - Shift Left Single [RS] */
676 /*-------------------------------------------------------------------*/
DEF_INST(shift_left_single)677 DEF_INST(shift_left_single)
678 {
679 int r1, r3; /* Register numbers */
680 int b2; /* effective address base */
681 VADR effective_addr2; /* effective address */
682 U32 n, n1, n2; /* 32-bit operand values */
683 U32 i, j; /* Integer work areas */
684
685 RS(inst, regs, r1, r3, b2, effective_addr2);
686
687 /* Use rightmost six bits of operand address as shift count */
688 n = effective_addr2 & 0x3F;
689
690 /* Fast path if no possible overflow */
691 if (regs->GR_L(r1) < 0x10000 && n < 16)
692 {
693 regs->GR_L(r1) <<= n;
694 regs->psw.cc = regs->GR_L(r1) ? 2 : 0;
695 return;
696 }
697
698 /* Load the numeric and sign portions from the R1 register */
699 n1 = regs->GR_L(r1) & 0x7FFFFFFF;
700 n2 = regs->GR_L(r1) & 0x80000000;
701
702 /* Shift the numeric portion left n positions */
703 for (i = 0, j = 0; i < n; i++)
704 {
705 /* Shift bits 1-31 left one bit position */
706 n1 <<= 1;
707
708 /* Overflow if bit shifted out is unlike the sign bit */
709 if ((n1 & 0x80000000) != n2)
710 j = 1;
711 }
712
713 /* Load the updated value into the R1 register */
714 regs->GR_L(r1) = (n1 & 0x7FFFFFFF) | n2;
715
716 /* Condition code 3 and program check if overflow occurred */
717 if (j)
718 {
719 regs->psw.cc = 3;
720 if ( FOMASK(®s->psw) )
721 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
722 return;
723 }
724
725 /* Set the condition code */
726 regs->psw.cc = (S32)regs->GR_L(r1) > 0 ? 2 :
727 (S32)regs->GR_L(r1) < 0 ? 1 : 0;
728
729 }
730
731
732 /*-------------------------------------------------------------------*/
733 /* 89 SLL - Shift Left Single Logical [RS] */
734 /*-------------------------------------------------------------------*/
DEF_INST(shift_left_single_logical)735 DEF_INST(shift_left_single_logical)
736 {
737 int r1, r3; /* Register numbers */
738 int b2; /* effective address base */
739 VADR effective_addr2; /* effective address */
740 U32 n; /* Integer work areas */
741
742 RS0(inst, regs, r1, r3, b2, effective_addr2);
743
744 /* Use rightmost six bits of operand address as shift count */
745 n = effective_addr2 & 0x3F;
746
747 /* Shift the R1 register */
748 regs->GR_L(r1) = n > 31 ? 0 : regs->GR_L(r1) << n;
749 }
750
751
752 /*-------------------------------------------------------------------*/
753 /* 8E SRDA - Shift Right Double [RS] */
754 /*-------------------------------------------------------------------*/
DEF_INST(shift_right_double)755 DEF_INST(shift_right_double)
756 {
757 int r1, r3; /* Register numbers */
758 int b2; /* effective address base */
759 VADR effective_addr2; /* effective address */
760 U32 n; /* 32-bit operand values */
761 U64 dreg; /* Double register work area */
762
763 RS(inst, regs, r1, r3, b2, effective_addr2);
764
765 ODD_CHECK(r1, regs);
766
767 /* Use rightmost six bits of operand address as shift count */
768 n = effective_addr2 & 0x3F;
769
770 /* Shift the R1 and R1+1 registers */
771 dreg = (U64)regs->GR_L(r1) << 32 | regs->GR_L(r1+1);
772 dreg = (U64)((S64)dreg >> n);
773 regs->GR_L(r1) = dreg >> 32;
774 regs->GR_L(r1+1) = dreg & 0xFFFFFFFF;
775
776 /* Set the condition code */
777 regs->psw.cc = (S64)dreg > 0 ? 2 : (S64)dreg < 0 ? 1 : 0;
778
779 }
780
781
782 /*-------------------------------------------------------------------*/
783 /* 8C SRDL - Shift Right Double Logical [RS] */
784 /*-------------------------------------------------------------------*/
DEF_INST(shift_right_double_logical)785 DEF_INST(shift_right_double_logical)
786 {
787 int r1, r3; /* Register numbers */
788 int b2; /* effective address base */
789 VADR effective_addr2; /* effective address */
790 U32 n; /* 32-bit operand values */
791 U64 dreg; /* Double register work area */
792
793 RS(inst, regs, r1, r3, b2, effective_addr2);
794
795 ODD_CHECK(r1, regs);
796
797 /* Use rightmost six bits of operand address as shift count */
798 n = effective_addr2 & 0x3F;
799
800 /* Shift the R1 and R1+1 registers */
801 dreg = (U64)regs->GR_L(r1) << 32 | regs->GR_L(r1+1);
802 dreg >>= n;
803 regs->GR_L(r1) = dreg >> 32;
804 regs->GR_L(r1+1) = dreg & 0xFFFFFFFF;
805
806 }
807
808
809 /*-------------------------------------------------------------------*/
810 /* 8A SRA - Shift Right Single [RS] */
811 /*-------------------------------------------------------------------*/
DEF_INST(shift_right_single)812 DEF_INST(shift_right_single)
813 {
814 int r1, r3; /* Register numbers */
815 int b2; /* effective address base */
816 VADR effective_addr2; /* effective address */
817 U32 n; /* Integer work areas */
818
819 RS0(inst, regs, r1, r3, b2, effective_addr2);
820
821 /* Use rightmost six bits of operand address as shift count */
822 n = effective_addr2 & 0x3F;
823
824 /* Shift the signed value of the R1 register */
825 regs->GR_L(r1) = n > 30 ?
826 ((S32)regs->GR_L(r1) < 0 ? -1 : 0) :
827 (S32)regs->GR_L(r1) >> n;
828
829 /* Set the condition code */
830 regs->psw.cc = ((S32)regs->GR_L(r1) > 0) ? 2 :
831 (((S32)regs->GR_L(r1) < 0) ? 1 : 0);
832 }
833
834
835 /*-------------------------------------------------------------------*/
836 /* 88 SRL - Shift Right Single Logical [RS] */
837 /*-------------------------------------------------------------------*/
DEF_INST(shift_right_single_logical)838 DEF_INST(shift_right_single_logical)
839 {
840 int r1, r3; /* Register numbers */
841 int b2; /* effective address base */
842 VADR effective_addr2; /* effective address */
843 U32 n; /* Integer work areas */
844
845 RS0(inst, regs, r1, r3, b2, effective_addr2);
846
847 /* Use rightmost six bits of operand address as shift count */
848 n = effective_addr2 & 0x3F;
849
850 /* Shift the R1 register */
851 regs->GR_L(r1) = n > 31 ? 0 : regs->GR_L(r1) >> n;
852 }
853
854
855 /*-------------------------------------------------------------------*/
856 /* 50 ST - Store [RX] */
857 /*-------------------------------------------------------------------*/
DEF_INST(store)858 DEF_INST(store)
859 {
860 int r1; /* Values of R fields */
861 int b2; /* Base of effective addr */
862 VADR effective_addr2; /* Effective address */
863 #if 0
864 U32 *p; /* Mainstor pointer */
865 #endif
866
867 RX(inst, regs, r1, b2, effective_addr2);
868
869 /* Store register contents at operand address */
870 /* FOLLOWING BLOCK COMMENTED OUT ISW 20060119 */
871 #if 0
872 if ((effective_addr2 & 3) == 0)
873 {
874 p = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
875 STORE_FW (p, regs->GR_L(r1));
876 ITIMER_UPDATE(effective_addr2, 4-1, regs);
877 }
878 else
879 #endif
880 ARCH_DEP(vstore4) ( regs->GR_L(r1), effective_addr2, b2, regs );
881
882 } /* end DEF_INST(store) */
883
884
885 #if defined(FEATURE_ACCESS_REGISTERS)
886 /*-------------------------------------------------------------------*/
887 /* 9B STAM - Store Access Multiple [RS] */
888 /*-------------------------------------------------------------------*/
DEF_INST(store_access_multiple)889 DEF_INST(store_access_multiple)
890 {
891 int r1, r3; /* Register numbers */
892 int b2; /* effective address base */
893 VADR effective_addr2; /* effective address */
894 int i, m, n; /* Integer work area */
895 U32 *p1, *p2 = NULL; /* Mainstor pointers */
896
897 RS(inst, regs, r1, r3, b2, effective_addr2);
898
899 FW_CHECK(effective_addr2, regs);
900
901 /* Calculate number of regs to store */
902 n = ((r3 - r1) & 0xF) + 1;
903
904 /* Calculate number of words to next boundary */
905 m = (0x800 - (effective_addr2 & 0x7ff)) >> 2;
906
907 /* Address of operand beginning */
908 p1 = (U32*)MADDRL(effective_addr2, n, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
909
910 /* Get address of next page if boundary crossed */
911 if (unlikely (m < n))
912 p2 = (U32*)MADDR(effective_addr2 + (m*4), b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
913 else
914 m = n;
915
916 /* Store to first page */
917 for (i = 0; i < m; i++)
918 store_fw (p1++, regs->AR((r1 + i) & 0xF));
919
920 /* Store to next page */
921 for ( ; i < n; i++)
922 store_fw (p2++, regs->AR((r1 + i) & 0xF));
923
924 }
925 #endif /*defined(FEATURE_ACCESS_REGISTERS)*/
926
927
928 /*-------------------------------------------------------------------*/
929 /* 42 STC - Store Character [RX] */
930 /*-------------------------------------------------------------------*/
DEF_INST(store_character)931 DEF_INST(store_character)
932 {
933 int r1; /* Value of R field */
934 int b2; /* Base of effective addr */
935 VADR effective_addr2; /* Effective address */
936
937 RX(inst, regs, r1, b2, effective_addr2);
938
939 /* Store rightmost byte of R1 register at operand address */
940 ARCH_DEP(vstoreb) ( regs->GR_LHLCL(r1), effective_addr2, b2, regs );
941 }
942
943
944 /*-------------------------------------------------------------------*/
945 /* BE STCM - Store Characters under Mask [RS] */
946 /*-------------------------------------------------------------------*/
DEF_INST(store_characters_under_mask)947 DEF_INST(store_characters_under_mask)
948 {
949 int r1, r3; /* Register numbers */
950 int b2; /* effective address base */
951 VADR effective_addr2; /* effective address */
952 int i; /* Integer work area */
953 BYTE rbyte[4]; /* Byte work area */
954
955 RS(inst, regs, r1, r3, b2, effective_addr2);
956
957 switch (r3) {
958
959 case 7:
960 /* Optimized case */
961 store_fw(rbyte, regs->GR_L(r1));
962 ARCH_DEP(vstorec) (rbyte+1, 2, effective_addr2, b2, regs);
963 break;
964
965 case 15:
966 /* Optimized case */
967 ARCH_DEP(vstore4) (regs->GR_L(r1), effective_addr2, b2, regs);
968 break;
969
970 default:
971 /* Extract value from register by mask */
972 i = 0;
973 if (r3 & 0x8) rbyte[i++] = (regs->GR_L(r1) >> 24) & 0xFF;
974 if (r3 & 0x4) rbyte[i++] = (regs->GR_L(r1) >> 16) & 0xFF;
975 if (r3 & 0x2) rbyte[i++] = (regs->GR_L(r1) >> 8) & 0xFF;
976 if (r3 & 0x1) rbyte[i++] = (regs->GR_L(r1) ) & 0xFF;
977
978 if (i)
979 ARCH_DEP(vstorec) (rbyte, i-1, effective_addr2, b2, regs);
980 #if defined(MODEL_DEPENDENT_STCM)
981 /* If the mask is all zero, we nevertheless access one byte
982 from the storage operand, because POP states that an
983 access exception may be recognized on the first byte */
984 else
985 ARCH_DEP(validate_operand) (effective_addr2, b2, 0,
986 ACCTYPE_WRITE, regs);
987 #endif
988 break;
989
990 } /* switch (r3) */
991 }
992
993
994 /*-------------------------------------------------------------------*/
995 /* B205 STCK - Store Clock [S] */
996 /* B27C STCKF - Store Clock Fast [S] */
997 /*-------------------------------------------------------------------*/
DEF_INST(store_clock)998 DEF_INST(store_clock)
999 {
1000 int b2; /* Base of effective addr */
1001 VADR effective_addr2; /* Effective address */
1002 U64 dreg; /* Double word work area */
1003
1004 S(inst, regs, b2, effective_addr2);
1005
1006 #if defined(_FEATURE_SIE)
1007 if(SIE_STATB(regs, IC2, STCK))
1008 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1009 #endif /*defined(_FEATURE_SIE)*/
1010
1011 #if defined(FEATURE_STORE_CLOCK_FAST)
1012 if(inst[1] == 0x05) // STCK only
1013 #endif /*defined(FEATURE_STORE_CLOCK_FAST)*/
1014 /* Perform serialization before fetching clock */
1015 PERFORM_SERIALIZATION (regs);
1016
1017 /* Retrieve the TOD clock value and shift out the epoch */
1018 dreg = tod_clock(regs) << 8;
1019
1020 #if defined(FEATURE_STORE_CLOCK_FAST)
1021 if(inst[1] == 0x05) // STCK only
1022 #endif /*defined(FEATURE_STORE_CLOCK_FAST)*/
1023 /* Insert the cpu address to ensure a unique value */
1024 dreg |= regs->cpuad;
1025
1026 // /*debug*/logmsg("Store TOD clock=%16.16" I64_FMT "X\n", dreg);
1027
1028 /* Store TOD clock value at operand address */
1029 ARCH_DEP(vstore8) ( dreg, effective_addr2, b2, regs );
1030
1031 #if defined(FEATURE_STORE_CLOCK_FAST)
1032 if(inst[1] == 0x05) // STCK only
1033 #endif /*defined(FEATURE_STORE_CLOCK_FAST)*/
1034 /* Perform serialization after storing clock */
1035 PERFORM_SERIALIZATION (regs);
1036
1037 /* Set condition code zero */
1038 regs->psw.cc = 0;
1039
1040 }
1041
1042
1043 #if defined(FEATURE_EXTENDED_TOD_CLOCK)
1044 /*-------------------------------------------------------------------*/
1045 /* B278 STCKE - Store Clock Extended [S] */
1046 /*-------------------------------------------------------------------*/
DEF_INST(store_clock_extended)1047 DEF_INST(store_clock_extended)
1048 {
1049 int b2; /* Base of effective addr */
1050 VADR effective_addr2; /* Effective address */
1051 U64 dreg; /* Double word work area */
1052
1053 S(inst, regs, b2, effective_addr2);
1054
1055 #if defined(_FEATURE_SIE)
1056 if(SIE_STATB(regs, IC2, STCK))
1057 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1058 #endif /*defined(_FEATURE_SIE)*/
1059
1060 /* Perform serialization before fetching clock */
1061 PERFORM_SERIALIZATION (regs);
1062
1063 /* Retrieve the TOD epoch, clock bits 0-51, and 4 zeroes */
1064 dreg = 0x00ffffffffffffffULL & tod_clock(regs);
1065
1066 /* Check that all 16 bytes of the operand are accessible */
1067 ARCH_DEP(validate_operand) (effective_addr2, b2, 15, ACCTYPE_WRITE, regs);
1068
1069 // /*debug*/logmsg("Store TOD clock extended: +0=%16.16" I64_FMT "X\n",
1070 // /*debug*/ dreg);
1071
1072 /* Store the 8 bit TOD epoch, clock bits 0-51, and bits
1073 20-23 of the TOD uniqueness value at operand address */
1074 ARCH_DEP(vstore8) ( dreg, effective_addr2, b2, regs );
1075
1076 // /*debug*/logmsg("Store TOD clock extended: +8=%16.16" I64_FMT "X\n",
1077 // /*debug*/ dreg);
1078
1079 /* Store second doubleword value at operand+8 */
1080 effective_addr2 += 8;
1081 effective_addr2 &= ADDRESS_MAXWRAP(regs);
1082
1083 /* Store nonzero value in pos 72 to 111 */
1084 dreg = 0x0000000001000000ULL | (regs->cpuad << 16) | regs->todpr;
1085
1086 ARCH_DEP(vstore8) ( dreg, effective_addr2, b2, regs );
1087
1088 /* Perform serialization after storing clock */
1089 PERFORM_SERIALIZATION (regs);
1090
1091 /* Set condition code zero */
1092 regs->psw.cc = 0;
1093 }
1094 #endif /*defined(FEATURE_EXTENDED_TOD_CLOCK)*/
1095
1096
1097 /*-------------------------------------------------------------------*/
1098 /* 40 STH - Store Halfword [RX] */
1099 /*-------------------------------------------------------------------*/
DEF_INST(store_halfword)1100 DEF_INST(store_halfword)
1101 {
1102 int r1; /* Value of R field */
1103 int b2; /* Base of effective addr */
1104 VADR effective_addr2; /* Effective address */
1105
1106 RX(inst, regs, r1, b2, effective_addr2);
1107
1108 /* Store rightmost 2 bytes of R1 register at operand address */
1109 ARCH_DEP(vstore2) ( regs->GR_LHL(r1), effective_addr2, b2, regs );
1110 }
1111
1112
1113 /*-------------------------------------------------------------------*/
1114 /* 90 STM - Store Multiple [RS] */
1115 /*-------------------------------------------------------------------*/
DEF_INST(store_multiple)1116 DEF_INST(store_multiple)
1117 {
1118 int r1, r3; /* Register numbers */
1119 int b2; /* effective address base */
1120 VADR effective_addr2; /* effective address */
1121 int i, m, n; /* Integer work areas */
1122 U32 *p1, *p2; /* Mainstor pointers */
1123 BYTE *bp1; /* Unaligned mainstor ptr */
1124
1125 RS(inst, regs, r1, r3, b2, effective_addr2);
1126
1127 /* Calculate number of bytes to store */
1128 n = (((r3 - r1) & 0xF) + 1) << 2;
1129
1130 /* Calculate number of bytes to next boundary */
1131 m = 0x800 - ((VADR_L)effective_addr2 & 0x7ff);
1132
1133 /* Get address of first page */
1134 bp1 = (BYTE*)MADDRL(effective_addr2, n, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
1135 p1 = (U32*)bp1;
1136
1137 if (likely(n <= m))
1138 {
1139 /* boundary not crossed */
1140 n >>= 2;
1141 #if defined(OPTION_STRICT_ALIGNMENT)
1142 if(likely(!(((uintptr_t)effective_addr2)&0x03)))
1143 {
1144 #endif
1145 for (i = 0; i < n; i++)
1146 store_fw (p1++, regs->GR_L((r1 + i) & 0xF));
1147 #if defined(OPTION_STRICT_ALIGNMENT)
1148 }
1149 else
1150 {
1151 for (i = 0; i < n; i++,bp1+=4)
1152 store_fw (bp1, regs->GR_L((r1 + i) & 0xF));
1153 }
1154 #endif
1155
1156 ITIMER_UPDATE(effective_addr2,(n*4)-1,regs);
1157 }
1158 else
1159 {
1160 /* boundary crossed, get address of the 2nd page */
1161 effective_addr2 += m;
1162 effective_addr2 &= ADDRESS_MAXWRAP(regs);
1163 p2 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
1164
1165 if (likely((m & 0x3) == 0))
1166 {
1167 /* word aligned */
1168 m >>= 2;
1169 for (i = 0; i < m; i++)
1170 store_fw (p1++, regs->GR_L((r1 + i) & 0xF));
1171 n >>= 2;
1172 for ( ; i < n; i++)
1173 store_fw (p2++, regs->GR_L((r1 + i) & 0xF));
1174 }
1175 else
1176 {
1177 /* worst case */
1178 U32 rwork[16];
1179 BYTE *b1, *b2;
1180
1181 for (i = 0; i < (n >> 2); i++)
1182 rwork[i] = CSWAP32(regs->GR_L((r1 + i) & 0xF));
1183 b1 = (BYTE *)&rwork[0];
1184
1185 b2 = (BYTE *)p1;
1186 for (i = 0; i < m; i++)
1187 *b2++ = *b1++;
1188
1189 b2 = (BYTE *)p2;
1190 for ( ; i < n; i++)
1191 *b2++ = *b1++;
1192 }
1193 }
1194
1195 } /* end DEF_INST(store_multiple) */
1196
1197
1198 /*-------------------------------------------------------------------*/
1199 /* 1B SR - Subtract Register [RR] */
1200 /*-------------------------------------------------------------------*/
DEF_INST(subtract_register)1201 DEF_INST(subtract_register)
1202 {
1203 int r1, r2; /* Values of R fields */
1204
1205 RR(inst, regs, r1, r2);
1206
1207 /* Subtract signed operands and set condition code */
1208 regs->psw.cc =
1209 sub_signed (&(regs->GR_L(r1)),
1210 regs->GR_L(r1),
1211 regs->GR_L(r2));
1212
1213 /* Program check if fixed-point overflow */
1214 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
1215 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
1216 }
1217
1218
1219 /*-------------------------------------------------------------------*/
1220 /* 5B S - Subtract [RX] */
1221 /*-------------------------------------------------------------------*/
DEF_INST(subtract)1222 DEF_INST(subtract)
1223 {
1224 int r1; /* Value of R field */
1225 int b2; /* Base of effective addr */
1226 VADR effective_addr2; /* Effective address */
1227 U32 n; /* 32-bit operand values */
1228
1229 RX(inst, regs, r1, b2, effective_addr2);
1230
1231 /* Load second operand from operand address */
1232 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
1233
1234 /* Subtract signed operands and set condition code */
1235 regs->psw.cc =
1236 sub_signed (&(regs->GR_L(r1)),
1237 regs->GR_L(r1),
1238 n);
1239
1240 /* Program check if fixed-point overflow */
1241 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
1242 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
1243 }
1244
1245
1246 /*-------------------------------------------------------------------*/
1247 /* 4B SH - Subtract Halfword [RX] */
1248 /*-------------------------------------------------------------------*/
DEF_INST(subtract_halfword)1249 DEF_INST(subtract_halfword)
1250 {
1251 int r1; /* Value of R field */
1252 int b2; /* Base of effective addr */
1253 VADR effective_addr2; /* Effective address */
1254 U32 n; /* 32-bit operand values */
1255
1256 RX(inst, regs, r1, b2, effective_addr2);
1257
1258 /* Load 2 bytes from operand address */
1259 n = (S16)ARCH_DEP(vfetch2) ( effective_addr2, b2, regs );
1260
1261 /* Subtract signed operands and set condition code */
1262 regs->psw.cc =
1263 sub_signed (&(regs->GR_L(r1)),
1264 regs->GR_L(r1),
1265 n);
1266
1267 /* Program check if fixed-point overflow */
1268 if ( regs->psw.cc == 3 && FOMASK(®s->psw) )
1269 regs->program_interrupt (regs, PGM_FIXED_POINT_OVERFLOW_EXCEPTION);
1270 }
1271
1272
1273 /*-------------------------------------------------------------------*/
1274 /* 1F SLR - Subtract Logical Register [RR] */
1275 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical_register)1276 DEF_INST(subtract_logical_register)
1277 {
1278 int r1, r2; /* Values of R fields */
1279
1280 RR0(inst, regs, r1, r2);
1281
1282 /* Subtract unsigned operands and set condition code */
1283 if (likely(r1 == r2))
1284 {
1285 regs->psw.cc = 2;
1286 regs->GR_L(r1) = 0;
1287 }
1288 else
1289 regs->psw.cc =
1290 sub_logical (&(regs->GR_L(r1)),
1291 regs->GR_L(r1),
1292 regs->GR_L(r2));
1293 }
1294
1295
1296 /*-------------------------------------------------------------------*/
1297 /* 5F SL - Subtract Logical [RX] */
1298 /*-------------------------------------------------------------------*/
DEF_INST(subtract_logical)1299 DEF_INST(subtract_logical)
1300 {
1301 int r1; /* Value of R field */
1302 int b2; /* Base of effective addr */
1303 VADR effective_addr2; /* Effective address */
1304 U32 n; /* 32-bit operand values */
1305
1306 RX(inst, regs, r1, b2, effective_addr2);
1307
1308 /* Load second operand from operand address */
1309 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
1310
1311 /* Subtract unsigned operands and set condition code */
1312 regs->psw.cc =
1313 sub_logical (&(regs->GR_L(r1)),
1314 regs->GR_L(r1),
1315 n);
1316 }
1317
1318
1319 /*-------------------------------------------------------------------*/
1320 /* 0A SVC - Supervisor Call [RR] */
1321 /*-------------------------------------------------------------------*/
DEF_INST(supervisor_call)1322 DEF_INST(supervisor_call)
1323 {
1324 BYTE i; /* Instruction byte 1 */
1325 PSA *psa; /* -> prefixed storage area */
1326 RADR px; /* prefix */
1327 int rc; /* Return code */
1328
1329 RR_SVC(inst, regs, i);
1330 #if defined(FEATURE_ECPSVM)
1331 if(ecpsvm_dosvc(regs,i)==0)
1332 {
1333 return;
1334 }
1335 #endif
1336
1337 #if defined(_FEATURE_SIE)
1338 if(SIE_MODE(regs) &&
1339 ( (regs->siebk->svc_ctl[0] & SIE_SVC0_ALL)
1340 || ( (regs->siebk->svc_ctl[0] & SIE_SVC0_1N) &&
1341 regs->siebk->svc_ctl[1] == i)
1342 || ( (regs->siebk->svc_ctl[0] & SIE_SVC0_2N) &&
1343 regs->siebk->svc_ctl[2] == i)
1344 || ( (regs->siebk->svc_ctl[0] & SIE_SVC0_3N) &&
1345 regs->siebk->svc_ctl[3] == i) ))
1346 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1347 #endif /*defined(_FEATURE_SIE)*/
1348
1349 px = regs->PX;
1350 SIE_TRANSLATE(&px, ACCTYPE_WRITE, regs);
1351
1352 /* Set the main storage reference and change bits */
1353 STORAGE_KEY(px, regs) |= (STORKEY_REF | STORKEY_CHANGE);
1354
1355 /* Use the I-byte to set the SVC interruption code */
1356 regs->psw.intcode = i;
1357
1358 /* Point to PSA in main storage */
1359 psa = (void*)(regs->mainstor + px);
1360
1361 #if defined(FEATURE_BCMODE)
1362 /* For ECMODE, store SVC interrupt code at PSA+X'88' */
1363 if ( ECMODE(®s->psw) )
1364 #endif /*defined(FEATURE_BCMODE)*/
1365 {
1366 psa->svcint[0] = 0;
1367 psa->svcint[1] = REAL_ILC(regs);
1368 psa->svcint[2] = 0;
1369 psa->svcint[3] = i;
1370 }
1371
1372 /* Store current PSW at PSA+X'20' */
1373 ARCH_DEP(store_psw) ( regs, psa->svcold );
1374
1375 /* Load new PSW from PSA+X'60' */
1376 if ( (rc = ARCH_DEP(load_psw) ( regs, psa->svcnew ) ) )
1377 regs->program_interrupt (regs, rc);
1378
1379 /* Perform serialization and checkpoint synchronization */
1380 PERFORM_SERIALIZATION (regs);
1381 PERFORM_CHKPT_SYNC (regs);
1382
1383 RETURN_INTCHECK(regs);
1384
1385 }
1386
1387
1388 /*-------------------------------------------------------------------*/
1389 /* 93 TS - Test and Set [S] */
1390 /*-------------------------------------------------------------------*/
DEF_INST(test_and_set)1391 DEF_INST(test_and_set)
1392 {
1393 int b2; /* Base of effective addr */
1394 VADR effective_addr2; /* Effective address */
1395 BYTE *main2; /* Mainstor address */
1396 BYTE old; /* Old value */
1397
1398 S(inst, regs, b2, effective_addr2);
1399
1400 ITIMER_SYNC(effective_addr2,0,regs);
1401 /* Perform serialization before starting operation */
1402 PERFORM_SERIALIZATION (regs);
1403
1404 /* Get operand absolute address */
1405 main2 = MADDR (effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
1406
1407 /* Obtain main-storage access lock */
1408 OBTAIN_MAINLOCK(regs);
1409
1410 /* Get old value */
1411 old = *main2;
1412
1413 /* Attempt to exchange the values */
1414 /* The WHILE statement that follows could lead to a @PJJ */
1415 /* TS-style lock release never being noticed, because @PJJ */
1416 /* because such release statements are implemented using @PJJ */
1417 /* regular instructions such as MVI or even ST which set @PJJ */
1418 /* [the most significant bit of] the mem_lockbyte to zero; @PJJ */
1419 /* these are NOT being protected using _MAINLOCK. In the @PJJ */
1420 /* absence of a machine assist for "cmpxchg1" it is then @PJJ */
1421 /* possible that this reset occurs in between the test @PJJ */
1422 /* IF (old == mem_lockbyte), and the updating of @PJJ */
1423 /* mem_lockbyte = 255; As this update in the case @PJJ */
1424 /* old == 255 is not needed to start with, we have @PJJ */
1425 /* inserted the test IF (old != 255) in front of the @PJJ */
1426 /* original WHILE statement. @PJJ */
1427 /* (The above bug WAS experienced running VM on an ARM @PJJ */
1428 /* Raspberry PI; this correction fixed it.) @PJJ */
1429 /* (Peter J. Jansen, May 2015) @PJJ */
1430 if (old != 255)
1431 while (cmpxchg1(&old, 255, main2));
1432 regs->psw.cc = old >> 7;
1433
1434 /* Release main-storage access lock */
1435 RELEASE_MAINLOCK(regs);
1436
1437 /* Perform serialization after completing operation */
1438 PERFORM_SERIALIZATION (regs);
1439
1440 if (regs->psw.cc == 1)
1441 {
1442 #if defined(_FEATURE_SIE)
1443 if(SIE_STATB(regs, IC0, TS1))
1444 {
1445 if( !OPEN_IC_PER(regs) )
1446 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1447 else
1448 longjmp(regs->progjmp, SIE_INTERCEPT_INSTCOMP);
1449 }
1450 else
1451 #endif /*defined(_FEATURE_SIE)*/
1452 if (sysblk.cpus > 1)
1453 sched_yield();
1454 }
1455 else
1456 {
1457 ITIMER_UPDATE(effective_addr2,0,regs);
1458 }
1459 }
1460
1461
1462 /*-------------------------------------------------------------------*/
1463 /* 91 TM - Test under Mask [SI] */
1464 /*-------------------------------------------------------------------*/
DEF_INST(test_under_mask)1465 DEF_INST(test_under_mask)
1466 {
1467 BYTE i2; /* Immediate operand */
1468 int b1; /* Base of effective addr */
1469 VADR effective_addr1; /* Effective address */
1470 BYTE tbyte; /* Work byte */
1471
1472 SI(inst, regs, i2, b1, effective_addr1);
1473
1474 /* Fetch byte from operand address */
1475 tbyte = ARCH_DEP(vfetchb) ( effective_addr1, b1, regs );
1476
1477 /* AND with immediate operand mask */
1478 tbyte &= i2;
1479
1480 /* Set condition code according to result */
1481 regs->psw.cc =
1482 ( tbyte == 0 ) ? 0 : /* result all zeroes */
1483 ( tbyte == i2) ? 3 : /* result all ones */
1484 1 ; /* result mixed */
1485 }
1486
1487
1488 #if defined(FEATURE_IMMEDIATE_AND_RELATIVE)
1489 /*-------------------------------------------------------------------*/
1490 /* A7x0 TMH - Test under Mask High [RI] */
1491 /*-------------------------------------------------------------------*/
DEF_INST(test_under_mask_high)1492 DEF_INST(test_under_mask_high)
1493 {
1494 int r1; /* Register number */
1495 U16 i2; /* 16-bit operand values */
1496 U16 h1; /* 16-bit operand values */
1497 U16 h2; /* 16-bit operand values */
1498
1499 RI0(inst, regs, r1, i2);
1500
1501 /* AND register bits 0-15 with immediate operand */
1502 h1 = i2 & regs->GR_LHH(r1);
1503
1504 /* Isolate leftmost bit of immediate operand */
1505 for ( h2 = 0x8000; h2 != 0 && (h2 & i2) == 0; h2 >>= 1 );
1506
1507 /* Set condition code according to result */
1508 regs->psw.cc =
1509 ( h1 == 0 ) ? 0 : /* result all zeroes */
1510 ( h1 == i2) ? 3 : /* result all ones */
1511 ((h1 & h2) == 0) ? 1 : /* leftmost bit zero */
1512 2; /* leftmost bit one */
1513 }
1514 #endif /*defined(FEATURE_IMMEDIATE_AND_RELATIVE)*/
1515
1516
1517 #if defined(FEATURE_IMMEDIATE_AND_RELATIVE)
1518 /*-------------------------------------------------------------------*/
1519 /* A7x1 TML - Test under Mask Low [RI] */
1520 /*-------------------------------------------------------------------*/
DEF_INST(test_under_mask_low)1521 DEF_INST(test_under_mask_low)
1522 {
1523 int r1; /* Register number */
1524 U16 i2; /* 16-bit operand values */
1525 U16 h1; /* 16-bit operand values */
1526 U16 h2; /* 16-bit operand values */
1527
1528 RI0(inst, regs, r1, i2);
1529
1530 /* AND register bits 16-31 with immediate operand */
1531 h1 = i2 & regs->GR_LHL(r1);
1532
1533 /* Isolate leftmost bit of immediate operand */
1534 for ( h2 = 0x8000; h2 != 0 && (h2 & i2) == 0; h2 >>= 1 );
1535
1536 /* Set condition code according to result */
1537 regs->psw.cc =
1538 ( h1 == 0 ) ? 0 : /* result all zeroes */
1539 ( h1 == i2) ? 3 : /* result all ones */
1540 ((h1 & h2) == 0) ? 1 : /* leftmost bit zero */
1541 2; /* leftmost bit one */
1542
1543 }
1544 #endif /*defined(FEATURE_IMMEDIATE_AND_RELATIVE)*/
1545
1546
1547 /*-------------------------------------------------------------------*/
1548 /* DC TR - Translate [SS] */
1549 /*-------------------------------------------------------------------*/
DEF_INST(translate)1550 DEF_INST(translate)
1551 {
1552 int len, len2 = -1; /* Lengths */
1553 int b1, b2; /* Values of base field */
1554 int i, b, n; /* Work variables */
1555 VADR addr1, addr2; /* Effective addresses */
1556 BYTE *dest, *dest2 = NULL, *tab, *tab2; /* Mainstor pointers */
1557
1558 SS_L(inst, regs, len, b1, addr1, b2, addr2);
1559
1560 /* Get destination pointer */
1561 dest = MADDRL (addr1, len+1, b1, regs, ACCTYPE_WRITE, regs->psw.pkey);
1562
1563 /* Get pointer to next page if destination crosses a boundary */
1564 if (CROSS2K (addr1, len))
1565 {
1566 len2 = len;
1567 len = 0x7FF - (addr1 & 0x7FF);
1568 len2 -= (len + 1);
1569 dest2 = MADDR ((addr1+len+1) & ADDRESS_MAXWRAP(regs),
1570 b1, regs, ACCTYPE_WRITE, regs->psw.pkey);
1571 }
1572
1573 /* Fast path if table does not cross a boundary */
1574 if (NOCROSS2K (addr2, 255))
1575 {
1576 tab = MADDR (addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
1577 /* Perform translate function */
1578 for (i = 0; i <= len; i++)
1579 dest[i] = tab[dest[i]];
1580 for (i = 0; i <= len2; i++)
1581 dest2[i] = tab[dest2[i]];
1582 }
1583 else
1584 {
1585 n = 0x800 - (addr2 & 0x7FF);
1586 b = dest[0];
1587
1588 /* Referenced part of the table may or may not span boundary */
1589 if (b < n)
1590 {
1591 tab = MADDR (addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
1592 for (i = 1; i <= len && b < n; i++)
1593 b = dest[i];
1594 for (i = 0; i <= len2 && b < n; i++)
1595 b = dest2[i];
1596 tab2 = b < n
1597 ? NULL
1598 : MADDR ((addr2+n) & ADDRESS_MAXWRAP(regs),
1599 b2, regs, ACCTYPE_READ, regs->psw.pkey);
1600 }
1601 else
1602 {
1603 tab2 = MADDR ((addr2+n) & ADDRESS_MAXWRAP(regs),
1604 b2, regs, ACCTYPE_READ, regs->psw.pkey);
1605 for (i = 1; i <= len && b >= n; i++)
1606 b = dest[i];
1607 for (i = 0; i <= len2 && b >= n; i++)
1608 b = dest2[i];
1609 tab = b >= n
1610 ? NULL
1611 : MADDR (addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
1612 }
1613
1614 /* Perform translate function */
1615 for (i = 0; i <= len; i++)
1616 dest[i] = dest[i] < n ? tab[dest[i]] : tab2[dest[i]-n];
1617 for (i = 0; i <= len2; i++)
1618 dest2[i] = dest2[i] < n ? tab[dest2[i]] : tab2[dest2[i]-n];
1619 } /* Translate table spans a boundary */
1620 }
1621
1622
1623 /*-------------------------------------------------------------------*/
1624 /* DD TRT - Translate and Test [SS] */
1625 /*-------------------------------------------------------------------*/
DEF_INST(translate_and_test)1626 DEF_INST(translate_and_test)
1627 {
1628 int l; /* Lenght byte */
1629 int b1, b2; /* Values of base field */
1630 VADR effective_addr1,
1631 effective_addr2; /* Effective addresses */
1632 int cc = 0; /* Condition code */
1633 BYTE sbyte; /* Byte work areas */
1634 BYTE dbyte; /* Byte work areas */
1635 int i; /* Integer work areas */
1636
1637 SS_L(inst, regs, l, b1, effective_addr1,
1638 b2, effective_addr2);
1639
1640 /* Process first operand from left to right */
1641 for ( i = 0; i <= l; i++ )
1642 {
1643 /* Fetch argument byte from first operand */
1644 dbyte = ARCH_DEP(vfetchb) ( effective_addr1, b1, regs );
1645
1646 /* Fetch function byte from second operand */
1647 sbyte = ARCH_DEP(vfetchb) ( (effective_addr2 + dbyte)
1648 & ADDRESS_MAXWRAP(regs), b2, regs );
1649
1650 /* Test for non-zero function byte */
1651 if (sbyte != 0) {
1652
1653 /* Store address of argument byte in register 1 */
1654 #if defined(FEATURE_ESAME)
1655 if(regs->psw.amode64)
1656 regs->GR_G(1) = effective_addr1;
1657 else
1658 #endif
1659 if ( regs->psw.amode )
1660 regs->GR_L(1) = effective_addr1;
1661 else
1662 regs->GR_LA24(1) = effective_addr1;
1663
1664 /* Store function byte in low-order byte of reg.2 */
1665 regs->GR_LHLCL(2) = sbyte;
1666
1667 /* Set condition code 2 if argument byte was last byte
1668 of first operand, otherwise set condition code 1 */
1669 cc = (i == l) ? 2 : 1;
1670
1671 /* Terminate the operation at this point */
1672 break;
1673
1674 } /* end if(sbyte) */
1675
1676 /* Increment first operand address */
1677 effective_addr1++;
1678 effective_addr1 &= ADDRESS_MAXWRAP(regs);
1679
1680 } /* end for(i) */
1681
1682 /* Update the condition code */
1683 regs->psw.cc = cc;
1684 }
1685
1686
1687 #ifdef FEATURE_EXTENDED_TRANSLATION
1688 /*-------------------------------------------------------------------*/
1689 /* B2A5 TRE - Translate Extended [RRE] */
1690 /*-------------------------------------------------------------------*/
DEF_INST(translate_extended)1691 DEF_INST(translate_extended)
1692 {
1693 int r1, r2; /* Values of R fields */
1694 int i; /* Loop counter */
1695 int cc = 0; /* Condition code */
1696 VADR addr1, addr2; /* Operand addresses */
1697 GREG len1; /* Operand length */
1698 BYTE byte1, byte2; /* Operand bytes */
1699 BYTE tbyte; /* Test byte */
1700 BYTE trtab[256]; /* Translate table */
1701
1702 RRE(inst, regs, r1, r2);
1703
1704 ODD_CHECK(r1, regs);
1705
1706 /* Load the test byte from bits 24-31 of register 0 */
1707
1708 tbyte = regs->GR_LHLCL(0);
1709
1710 /* Load the operand addresses */
1711 addr1 = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
1712 addr2 = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
1713
1714 /* Load first operand length from R1+1 */
1715 len1 = GR_A(r1+1, regs);
1716
1717 /* Fetch second operand into work area.
1718 [7.5.101] Access exceptions for all 256 bytes of the second
1719 operand may be recognized, even if not all bytes are used */
1720 ARCH_DEP(vfetchc) ( trtab, 255, addr2, r2, regs );
1721
1722 /* Process first operand from left to right */
1723 for (i = 0; len1 > 0; i++)
1724 {
1725 /* If 4096 bytes have been compared, exit with condition code 3 */
1726 if (i >= 4096)
1727 {
1728 cc = 3;
1729 break;
1730 }
1731
1732 /* Fetch byte from first operand */
1733 byte1 = ARCH_DEP(vfetchb) ( addr1, r1, regs );
1734
1735 /* If equal to test byte, exit with condition code 1 */
1736 if (byte1 == tbyte)
1737 {
1738 cc = 1;
1739 break;
1740 }
1741
1742 /* Load indicated byte from translate table */
1743 byte2 = trtab[byte1];
1744
1745 /* Store result at first operand address */
1746 ARCH_DEP(vstoreb) ( byte2, addr1, r1, regs );
1747 addr1++;
1748 addr1 &= ADDRESS_MAXWRAP(regs);
1749 len1--;
1750
1751 /* Update the registers */
1752 SET_GR_A(r1, regs, addr1);
1753 SET_GR_A(r1+1, regs, len1);
1754
1755 } /* end for(i) */
1756
1757 /* Set condition code */
1758 regs->psw.cc = cc;
1759
1760 } /* end translate_extended */
1761 #endif /*FEATURE_EXTENDED_TRANSLATION*/
1762
1763
1764 /*-------------------------------------------------------------------*/
1765 /* F3 UNPK - Unpack [SS] */
1766 /*-------------------------------------------------------------------*/
DEF_INST(unpack)1767 DEF_INST(unpack)
1768 {
1769 int l1, l2; /* Register numbers */
1770 int b1, b2; /* Base registers */
1771 VADR effective_addr1,
1772 effective_addr2; /* Effective addressES */
1773 int i, j; /* Loop counters */
1774 BYTE sbyte; /* Source operand byte */
1775 BYTE rbyte; /* Right result byte of pair */
1776 BYTE lbyte; /* Left result byte of pair */
1777
1778 SS(inst, regs, l1, l2, b1, effective_addr1,
1779 b2, effective_addr2);
1780
1781 /* If operand 1 crosses a page, make sure both pages are accessable */
1782 if((effective_addr1 & PAGEFRAME_PAGEMASK) !=
1783 ((effective_addr1 + l1) & PAGEFRAME_PAGEMASK))
1784 ARCH_DEP(validate_operand) (effective_addr1, b1, l1, ACCTYPE_WRITE_SKP, regs);
1785
1786 /* If operand 2 crosses a page, make sure both pages are accessable */
1787 if((effective_addr2 & PAGEFRAME_PAGEMASK) !=
1788 ((effective_addr2 + l2) & PAGEFRAME_PAGEMASK))
1789 ARCH_DEP(validate_operand) (effective_addr2, b2, l2, ACCTYPE_READ, regs);
1790
1791 /* Exchange the digits in the rightmost byte */
1792 effective_addr1 += l1;
1793 effective_addr2 += l2;
1794 sbyte = ARCH_DEP(vfetchb) ( effective_addr2, b2, regs );
1795 rbyte = (sbyte << 4) | (sbyte >> 4);
1796 ARCH_DEP(vstoreb) ( rbyte, effective_addr1, b1, regs );
1797
1798 /* Process remaining bytes from right to left */
1799 for (i = l1, j = l2; i > 0; i--)
1800 {
1801 /* Fetch source byte from second operand */
1802 if (j-- > 0)
1803 {
1804 sbyte = ARCH_DEP(vfetchb) ( --effective_addr2, b2, regs );
1805 rbyte = (sbyte & 0x0F) | 0xF0;
1806 lbyte = (sbyte >> 4) | 0xF0;
1807 }
1808 else
1809 {
1810 rbyte = 0xF0;
1811 lbyte = 0xF0;
1812 }
1813
1814 /* Store unpacked bytes at first operand address */
1815 ARCH_DEP(vstoreb) ( rbyte, --effective_addr1, b1, regs );
1816 if (--i > 0)
1817 {
1818 effective_addr1 &= ADDRESS_MAXWRAP(regs);
1819 ARCH_DEP(vstoreb) ( lbyte, --effective_addr1, b1, regs );
1820 }
1821
1822 /* Wraparound according to addressing mode */
1823 effective_addr1 &= ADDRESS_MAXWRAP(regs);
1824 effective_addr2 &= ADDRESS_MAXWRAP(regs);
1825
1826 } /* end for(i) */
1827
1828 }
1829
1830
1831 /*-------------------------------------------------------------------*/
1832 /* 0102 UPT - Update Tree [E] */
1833 /* (c) Copyright Peter Kuschnerus, 1999-2009 */
1834 /* (c) Copyright "Fish" (David B. Trout), 2005-2009 */
1835 /*-------------------------------------------------------------------*/
DEF_INST(update_tree)1836 DEF_INST(update_tree)
1837 {
1838 GREG index; /* tree index */
1839 GREG nodecode; /* current node's codeword */
1840 GREG nodedata; /* current node's other data */
1841 VADR nodeaddr; /* work addr of current node */
1842 #if defined(FEATURE_ESAME)
1843 BYTE a64 = regs->psw.amode64; /* 64-bit mode flag */
1844 #endif
1845
1846 E(inst, regs);
1847
1848 /*
1849 ** GR0, GR1 node values (codeword and other data) of node
1850 ** with "highest encountered codeword value"
1851 ** GR2, GR3 node values (codeword and other data) from whichever
1852 ** node we happened to have encountered that had a code-
1853 ** word value equal to our current "highest encountered
1854 ** codeword value" (e.g. GR0) (cc0 only)
1855 ** GR4 pointer to one node BEFORE the beginning of the tree
1856 ** GR5 current node index (tree displacement to current node)
1857 */
1858
1859 /* Check GR4, GR5 for proper alignment */
1860 if (0
1861 || ( GR_A(4,regs) & UPT_ALIGN_MASK )
1862 || ( GR_A(5,regs) & UPT_ALIGN_MASK )
1863 )
1864 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
1865
1866 /* Bubble the tree by moving successively higher nodes towards the
1867 front (beginning) of the tree, only stopping whenever we either:
1868
1869 1. reach the beginning of the tree, -OR-
1870 2. encounter a node with a negative codeword value, -OR-
1871 3. encounter a node whose codeword is equal to
1872 our current "highest encountered codeword".
1873
1874 Thus, when we're done, GR0 & GR1 will then contain the node values
1875 of the node with the highest encountered codeword value, and all
1876 other traversed nodes will have been reordered into descending code-
1877 word sequence (i.e. from highest codeword value to lowest codeword
1878 value; this is after all an instruction used for sorting/merging).
1879 */
1880
1881 for (;;)
1882 {
1883 /* Calculate index value of next node to be examined (half
1884 as far from beginning of tree to where we currently are)
1885 */
1886 index = (GR_A(5,regs) >> 1) & UPT_SHIFT_MASK;
1887
1888 /* Exit with cc1 when we've gone as far as we can go */
1889 if ( !index )
1890 {
1891 regs->psw.cc = 1;
1892 break;
1893 }
1894
1895 /* Exit with cc3 when we encounter a negative codeword value
1896 (i.e. any codeword value with its highest-order bit on)
1897 */
1898 if ( GR_A(0,regs) & UPT_HIGH_BIT )
1899 {
1900 regs->psw.cc = 3;
1901 break;
1902 }
1903
1904 /* Retrieve this node's values for closer examination... */
1905
1906 nodeaddr = regs->GR(4) + index;
1907
1908 #if defined(FEATURE_ESAME)
1909 if ( a64 )
1910 {
1911 nodecode = ARCH_DEP(vfetch8) ( (nodeaddr+0) & ADDRESS_MAXWRAP(regs), AR4, regs );
1912 nodedata = ARCH_DEP(vfetch8) ( (nodeaddr+8) & ADDRESS_MAXWRAP(regs), AR4, regs );
1913 }
1914 else
1915 #endif
1916 {
1917 nodecode = ARCH_DEP(vfetch4) ( (nodeaddr+0) & ADDRESS_MAXWRAP(regs), AR4, regs );
1918 nodedata = ARCH_DEP(vfetch4) ( (nodeaddr+4) & ADDRESS_MAXWRAP(regs), AR4, regs );
1919 }
1920
1921 /* GR5 must remain UNCHANGED if the execution of a unit of operation
1922 is nullified or suppressed! Thus it must ONLY be updated/committed
1923 AFTER we've successfully retrieved the node data (since the storage
1924 access could cause a program-check thereby nullifying/suppressing
1925 the instruction's "current unit of operation")
1926 */
1927 SET_GR_A(5,regs,index); // (do AFTER node data is accessed!)
1928
1929 /* Exit with cc0 whenever we reach a node whose codeword is equal
1930 to our current "highest encountered" codeword value (i.e. any
1931 node whose codeword matches our current "highest" (GR0) value)
1932 */
1933 if ( nodecode == GR_A(0,regs) )
1934 {
1935 /* Load GR2 and GR3 with the equal codeword node's values */
1936 SET_GR_A(2,regs,nodecode);
1937 SET_GR_A(3,regs,nodedata);
1938 regs->psw.cc = 0;
1939 return;
1940 }
1941
1942 /* Keep resequencing the tree's nodes, moving successively higher
1943 nodes to the front (beginning of tree)...
1944 */
1945 if ( nodecode < GR_A(0,regs) )
1946 continue;
1947
1948 /* This node has a codeword value higher than our currently saved
1949 highest encountered codeword value (GR0). Swap our GR0/1 values
1950 with this node's values, such that GR0/1 always hold the values
1951 from the node with the highest encountered codeword value...
1952 */
1953
1954 /* Store obsolete GR0 and GR1 values into this node's entry */
1955 #if defined(FEATURE_ESAME)
1956 if ( a64 )
1957 {
1958 ARCH_DEP(vstore8) ( GR_A(0,regs), (nodeaddr+0) & ADDRESS_MAXWRAP(regs), AR4, regs );
1959 ARCH_DEP(vstore8) ( GR_A(1,regs), (nodeaddr+8) & ADDRESS_MAXWRAP(regs), AR4, regs );
1960 }
1961 else
1962 #endif
1963 {
1964 ARCH_DEP(vstore4) ( GR_A(0,regs), (nodeaddr+0) & ADDRESS_MAXWRAP(regs), AR4, regs );
1965 ARCH_DEP(vstore4) ( GR_A(1,regs), (nodeaddr+4) & ADDRESS_MAXWRAP(regs), AR4, regs );
1966 }
1967
1968 /* Update GR0 and GR1 with the new "highest encountered" values */
1969 SET_GR_A(0,regs,nodecode);
1970 SET_GR_A(1,regs,nodedata);
1971 }
1972
1973 /* Commit GR5 with the actual index value we stopped on */
1974 SET_GR_A(5,regs,index);
1975
1976 } /* end DEF_INST(update_tree) */
1977
1978
1979 #if defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_3)
1980 /*-------------------------------------------------------------------*/
1981 /* B9B0 CU14 - Convert UTF-8 to UTF-32 [RRF] */
1982 /*-------------------------------------------------------------------*/
DEF_INST(convert_utf8_to_utf32)1983 DEF_INST(convert_utf8_to_utf32)
1984 {
1985 VADR dest; /* Destination address */
1986 GREG destlen; /* Destination length */
1987 int r1;
1988 int r2;
1989 int read; /* Bytes read */
1990 VADR srce; /* Source address */
1991 GREG srcelen; /* Source length */
1992 BYTE utf32[4]; /* utf32 character(s) */
1993 BYTE utf8[4]; /* utf8 character(s) */
1994 #if defined(FEATURE_ETF3_ENHANCEMENT)
1995 int wfc; /* Well-Formedness-Checking (W) */
1996 #endif /*defined(FEATURE_ETF3_ENHANCEMENT)*/
1997 int xlated; /* characters translated */
1998
1999 // NOTE: it's faster to decode with RRE format
2000 // and then to handle the 'wfc' flag separately...
2001
2002 //RRF_M(inst, regs, r1, r2, wfc);
2003 RRE(inst, regs, r1, r2);
2004 ODD2_CHECK(r1, r2, regs);
2005
2006 /* Get paramaters */
2007 dest = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
2008 destlen = GR_A(r1 + 1, regs);
2009 srce = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
2010 srcelen = GR_A(r2 + 1, regs);
2011 #if defined(FEATURE_ETF3_ENHANCEMENT)
2012 if(inst[2] & 0x10)
2013 wfc = 1;
2014 else
2015 wfc = 0;
2016 #endif /*defined(FEATURE_ETF3_ENHANCEMENT)*/
2017
2018 /* Every valid utf-32 starts with 0x00 */
2019 utf32[0] = 0x00;
2020
2021 /* Initialize number of translated charachters */
2022 xlated = 0;
2023 while(xlated < 4096)
2024 {
2025 /* Check end of source or destination */
2026 if(srcelen < 1)
2027 {
2028 regs->psw.cc = 0;
2029 return;
2030 }
2031 if(destlen < 4)
2032 {
2033 regs->psw.cc = 1;
2034 return;
2035 }
2036
2037 /* Fetch a byte */
2038 utf8[0] = ARCH_DEP(vfetchb)(srce, r2, regs);
2039 if(utf8[0] < 0x80)
2040 {
2041 /* xlate range 00-7f */
2042 /* 0jklmnop -> 00000000 00000000 00000000 0jklmnop */
2043 utf32[1] = 0x00;
2044 utf32[2] = 0x00;
2045 utf32[3] = utf8[0];
2046 read = 1;
2047 }
2048 else if(utf8[0] >= 0xc0 && utf8[0] <= 0xdf)
2049 {
2050 #if defined(FEATURE_ETF3_ENHANCEMENT)
2051 /* WellFormednessChecking */
2052 if(wfc)
2053 {
2054 if(utf8[0] <= 0xc1)
2055 {
2056 regs->psw.cc = 2;
2057 return;
2058 }
2059 }
2060 #endif /*defined(FEATURE_ETF3_ENHANCEMENT)*/
2061
2062 /* Check end of source */
2063 if(srcelen < 2)
2064 {
2065 regs->psw.cc = 0; /* Strange but stated in POP */
2066 return;
2067 }
2068
2069 /* Get the next byte */
2070 utf8[1] = ARCH_DEP(vfetchb)(srce + 1, r2, regs);
2071
2072 #if defined(FEATURE_ETF3_ENHANCEMENT)
2073 /* WellFormednessChecking */
2074 if(wfc)
2075 {
2076 if(utf8[1] < 0x80 || utf8[1] > 0xbf)
2077 {
2078 regs->psw.cc = 2;
2079 return;
2080 }
2081 }
2082 #endif /*defined(FEATURE_ETF3_ENHANCEMENT)*/
2083
2084 /* xlate range c000-dfff */
2085 /* 110fghij 10klmnop -> 00000000 00000000 00000fgh ijklmnop */
2086 utf32[1] = 0x00;
2087 utf32[2] = (utf8[0] & 0x1c) >> 2;
2088 utf32[3] = (utf8[0] << 6) | (utf8[1] & 0x3f);
2089 read = 2;
2090 }
2091 else if(utf8[0] >= 0xe0 && utf8[0] <= 0xef)
2092 {
2093 /* Check end of source */
2094 if(srcelen < 3)
2095 {
2096 regs->psw.cc = 0; /* Strange but stated in POP */
2097 return;
2098 }
2099
2100 /* Get the next 2 bytes */
2101 ARCH_DEP(vfetchc)(&utf8[1], 1, srce + 1, r2, regs);
2102
2103 #if defined(FEATURE_ETF3_ENHANCEMENT)
2104 /* WellformednessChecking */
2105 if(wfc)
2106 {
2107 if(utf8[0] == 0xe0)
2108 {
2109 if(utf8[1] < 0xa0 || utf8[1] > 0xbf || utf8[2] < 0x80 || utf8[2] > 0xbf)
2110 {
2111 regs->psw.cc = 2;
2112 return;
2113 }
2114 }
2115 if((utf8[0] >= 0xe1 && utf8[0] <= 0xec) || (utf8[0] >= 0xee && utf8[0] <= 0xef))
2116 {
2117 if(utf8[1] < 0x80 || utf8[1] > 0xbf || utf8[2] < 0x80 || utf8[2] > 0xbf)
2118 {
2119 regs->psw.cc = 2;
2120 return;
2121 }
2122 }
2123 if(utf8[0] == 0xed)
2124 {
2125 if(utf8[1] < 0x80 || utf8[1] > 0x9f || utf8[2] < 0x80 || utf8[2] > 0xbf)
2126 {
2127 regs->psw.cc = 2;
2128 return;
2129 }
2130 }
2131 }
2132 #endif /*defined(FEATURE_ETF3_ENHANCEMENT)*/
2133
2134 /* xlate range e00000-efffff */
2135 /* 1110abcd 10efghij 10klmnop -> 00000000 00000000 abcdefgh ijklmnop */
2136 utf32[1] = 0x00;
2137 utf32[2] = (utf8[0] << 4) | ((utf8[1] & 0x3c) >> 2);
2138 utf32[3] = (utf8[1] << 6) | (utf8[2] & 0x3f);
2139 read = 3;
2140 }
2141 else if(utf8[0] >= 0xf0 && utf8[0] <= 0xf7)
2142 {
2143 #if defined(FEATURE_ETF3_ENHANCEMENT)
2144 /* WellFormednessChecking */
2145 if(wfc)
2146 {
2147 if(utf8[0] > 0xf4)
2148 {
2149 regs->psw.cc = 2;
2150 return;
2151 }
2152 }
2153 #endif /*defined(FEATURE_ETF3_ENHANCEMENT)*/
2154
2155 /* Check end of source */
2156 if(srcelen < 4)
2157 {
2158 regs->psw.cc = 0; /* Strange but stated in POP */
2159 return;
2160 }
2161
2162 /* Get the next 3 bytes */
2163 ARCH_DEP(vfetchc)(&utf8[1], 2, srce + 1, r2, regs);
2164
2165 #if defined(FEATURE_ETF3_ENHANCEMENT)
2166 /* WellFormdnessChecking */
2167 if(wfc)
2168 {
2169 if(utf8[0] == 0xf0)
2170 {
2171 if(utf8[1] < 0x90 || utf8[1] > 0xbf || utf8[2] < 0x80 || utf8[2] > 0xbf || utf8[3] < 0x80 || utf8[3] > 0xbf)
2172 {
2173 regs->psw.cc = 2;
2174 return;
2175 }
2176 }
2177 if(utf8[0] >= 0xf1 && utf8[0] <= 0xf3)
2178 {
2179 if(utf8[1] < 0x80 || utf8[1] > 0xbf || utf8[2] < 0x80 || utf8[2] > 0xbf || utf8[3] < 0x80 || utf8[3] > 0xbf)
2180 {
2181 regs->psw.cc = 2;
2182 return;
2183 }
2184 }
2185 if(utf8[0] == 0xf4)
2186 {
2187 if(utf8[1] < 0x80 || utf8[1] > 0x8f || utf8[2] < 0x80 || utf8[2] > 0xbf || utf8[3] < 0x80 || utf8[3] > 0xbf)
2188 {
2189 regs->psw.cc = 2;
2190 return;
2191 }
2192 }
2193 }
2194 #endif /*defined(FEATURE_ETF3_ENHANCEMENT)*/
2195
2196 /* xlate range f0000000-f7000000 */
2197 /* 1110uvw 10xyefgh 10ijklmn 10opqrst -> 00000000 000uvwxy efghijkl mnopqrst */
2198 utf32[1] = ((utf8[0] & 0x07) << 2) | ((utf8[1] & 0x30) >> 4);
2199 utf32[2] = (utf8[1] << 4) | ((utf8[2] & 0x3c) >> 2);
2200 utf32[3] = (utf8[2] << 6) | (utf8[3] & 0x3f);
2201 read = 4;
2202 }
2203 else
2204 {
2205 regs->psw.cc = 2;
2206 return;
2207 }
2208
2209 /* Write and commit registers */
2210 ARCH_DEP(vstorec)(utf32, 3, dest, r1, regs);
2211 SET_GR_A(r1, regs, (dest += 4) & ADDRESS_MAXWRAP(regs));
2212 SET_GR_A(r1 + 1, regs, destlen -= 4);
2213 SET_GR_A(r2, regs, (srce += read) & ADDRESS_MAXWRAP(regs));
2214 SET_GR_A(r2 + 1, regs, srcelen -= read);
2215
2216 xlated += read;
2217 }
2218
2219 /* CPU determined number of characters reached */
2220 regs->psw.cc = 3;
2221 }
2222
2223 /*-------------------------------------------------------------------*/
2224 /* B9B1 CU24 - Convert UTF-16 to UTF-32 [RRF] */
2225 /*-------------------------------------------------------------------*/
DEF_INST(convert_utf16_to_utf32)2226 DEF_INST(convert_utf16_to_utf32)
2227 {
2228 VADR dest; /* Destination address */
2229 GREG destlen; /* Destination length */
2230 int r1;
2231 int r2;
2232 int read; /* Bytes read */
2233 VADR srce; /* Source address */
2234 GREG srcelen; /* Source length */
2235 BYTE utf16[4]; /* utf16 character(s) */
2236 BYTE utf32[4]; /* utf328 character(s) */
2237 BYTE uvwxy; /* Work value */
2238 #if defined(FEATURE_ETF3_ENHANCEMENT)
2239 int wfc; /* Well-Formedness-Checking (W) */
2240 #endif /*defined(FEATURE_ETF3_ENHANCEMENT)*/
2241 int xlated; /* characters translated */
2242
2243 // NOTE: it's faster to decode with RRE format
2244 // and then to handle the 'wfc' flag separately...
2245
2246 //RRF_M(inst, regs, r1, r2, wfc);
2247 RRE(inst, regs, r1, r2);
2248 ODD2_CHECK(r1, r2, regs);
2249
2250 /* Get paramaters */
2251 dest = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
2252 destlen = GR_A(r1 + 1, regs);
2253 srce = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
2254 srcelen = GR_A(r2 + 1, regs);
2255 #if defined(FEATURE_ETF3_ENHANCEMENT)
2256 if(inst[2] & 0x10)
2257 wfc = 1;
2258 else
2259 wfc = 0;
2260 #endif /*defined(FEATURE_ETF3_ENHANCEMENT)*/
2261
2262 /* Every valid utf-32 starts with 0x00 */
2263 utf32[0] = 0x00;
2264
2265 /* Initialize number of translated charachters */
2266 xlated = 0;
2267 while(xlated < 4096)
2268 {
2269 /* Check end of source or destination */
2270 if(srcelen < 2)
2271 {
2272 regs->psw.cc = 0;
2273 return;
2274 }
2275 if(destlen < 4)
2276 {
2277 regs->psw.cc = 1;
2278 return;
2279 }
2280
2281 /* Fetch 2 bytes */
2282 ARCH_DEP(vfetchc)(utf16, 1, srce, r2, regs);
2283 if(utf16[0] <= 0xd7 || utf16[0] >= 0xdc)
2284 {
2285 /* xlate range 0000-d7fff and dc00-ffff */
2286 /* abcdefgh ijklmnop -> 00000000 00000000 abcdefgh ijklmnop */
2287 utf32[1] = 0x00;
2288 utf32[2] = utf16[0];
2289 utf32[3] = utf16[1];
2290 read = 2;
2291 }
2292 else
2293 {
2294 /* Check end of source */
2295 if(srcelen < 4)
2296 {
2297 regs->psw.cc = 0; /* Strange but stated in POP */
2298 return;
2299 }
2300
2301 /* Fetch another 2 bytes */
2302 ARCH_DEP(vfetchc)(&utf16[2], 1, srce, r2, regs);
2303
2304 #if defined(FEATURE_ETF3_ENHANCEMENT)
2305 /* WellFormednessChecking */
2306 if(wfc)
2307 {
2308 if(utf16[2] < 0xdc && utf16[2] > 0xdf)
2309 {
2310 regs->psw.cc = 2;
2311 return;
2312 }
2313 }
2314 #endif /*defined(FEATURE_ETF3_ENHANCEMENT)*/
2315
2316 /* xlate range d800-dbff */
2317 /* 110110ab cdefghij 110111kl mnopqrst -> 00000000 000uvwxy efghijkl mnopqrst */
2318 /* 000uvwxy = 0000abcde + 1 */
2319 uvwxy = (((utf16[0] & 0x03) << 2) | (utf16[1] >> 6)) + 1;
2320 utf32[1] = uvwxy;
2321 utf32[2] = (utf16[1] << 2) | (utf16[2] & 0x03);
2322 utf32[3] = utf16[3];
2323 read = 4;
2324 }
2325
2326 /* Write and commit registers */
2327 ARCH_DEP(vstorec)(utf32, 3, dest, r1, regs);
2328 SET_GR_A(r1, regs, (dest += 4) & ADDRESS_MAXWRAP(regs));
2329 SET_GR_A(r1 + 1, regs, destlen -= 4);
2330 SET_GR_A(r2, regs, (srce += read) & ADDRESS_MAXWRAP(regs));
2331 SET_GR_A(r2 + 1, regs, srcelen -= read);
2332
2333 xlated += read;
2334 }
2335
2336 /* CPU determined number of characters reached */
2337 regs->psw.cc = 3;
2338 }
2339
2340 /*-------------------------------------------------------------------*/
2341 /* B9B2 CU41 - Convert UTF-32 to UTF-8 [RRE] */
2342 /*-------------------------------------------------------------------*/
DEF_INST(convert_utf32_to_utf8)2343 DEF_INST(convert_utf32_to_utf8)
2344 {
2345 VADR dest; /* Destination address */
2346 GREG destlen; /* Destination length */
2347 int r1;
2348 int r2;
2349 VADR srce; /* Source address */
2350 GREG srcelen; /* Source length */
2351 BYTE utf32[4]; /* utf32 character(s) */
2352 BYTE utf8[4]; /* utf8 character(s) */
2353 int write; /* Bytes written */
2354 int xlated; /* characters translated */
2355
2356 RRE(inst, regs, r1, r2);
2357 ODD2_CHECK(r1, r2, regs);
2358
2359 /* Get paramaters */
2360 dest = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
2361 destlen = GR_A(r1 + 1, regs);
2362 srce = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
2363 srcelen = GR_A(r2 + 1, regs);
2364
2365 /* Initialize number of translated charachters */
2366 xlated = 0;
2367 write = 0;
2368 while(xlated < 4096)
2369 {
2370 /* Check end of source or destination */
2371 if(srcelen < 4)
2372 {
2373 regs->psw.cc = 0;
2374 return;
2375 }
2376 if(destlen < 1)
2377 {
2378 regs->psw.cc = 1;
2379 return;
2380 }
2381
2382 /* Get 4 bytes */
2383 ARCH_DEP(vfetchc)(utf32, 3, srce, r2, regs);
2384
2385 if(utf32[0] != 0x00)
2386 {
2387 regs->psw.cc = 2;
2388 return;
2389 }
2390 else if(utf32[1] == 0x00)
2391 {
2392 if(utf32[2] == 0x00)
2393 {
2394 if(utf32[3] <= 0x7f)
2395 {
2396 /* xlate range 00000000-0000007f */
2397 /* 00000000 00000000 00000000 0jklmnop -> 0jklmnop */
2398 utf8[0] = utf32[3];
2399 write = 1;
2400 }
2401 }
2402 else if(utf32[2] <= 0x07)
2403 {
2404 /* Check destination length */
2405 if(destlen < 2)
2406 {
2407 regs->psw.cc = 1;
2408 return;
2409 }
2410
2411 /* xlate range 00000080-000007ff */
2412 /* 00000000 00000000 00000fgh ijklmnop -> 110fghij 10klmnop */
2413 utf8[0] = 0xc0 | (utf32[2] << 2) | (utf32[2] >> 6);
2414 utf8[1] = 0x80 | (utf32[2] & 0x3f);
2415 write = 2;
2416 }
2417 else if(utf32[2] <= 0xd7 || utf32[2] > 0xdc)
2418 {
2419 /* Check destination length */
2420 if(destlen < 3)
2421 {
2422 regs->psw.cc = 1;
2423 return;
2424 }
2425
2426 /* xlate range 00000800-0000d7ff and 0000dc00-0000ffff */
2427 /* 00000000 00000000 abcdefgh ijklnmop -> 1110abcd 10efghij 10klmnop */
2428 utf8[0] = 0xe0 | (utf32[2] >> 4);
2429 utf8[1] = 0x80 | ((utf32[2] & 0x0f) << 2) | (utf32[3] >> 6);
2430 utf8[2] = 0x80 | (utf32[3] & 0x3f);
2431 write = 3;
2432 }
2433 else
2434 {
2435 regs->psw.cc = 2;
2436 return;
2437 }
2438 }
2439 else if(utf32[1] >= 0x01 && utf32[1] <= 0x10)
2440 {
2441 /* Check destination length */
2442 if(destlen < 4)
2443 {
2444 regs->psw.cc = 1;
2445 return;
2446 }
2447
2448 /* xlate range 00010000-0010ffff */
2449 /* 00000000 000uvwxy efghijkl mnopqrst -> 11110uvw 10xyefgh 10ijklmn 10opqrst */
2450 utf8[0] = 0xf0 | (utf32[1] >> 2);
2451 utf8[1] = 0x80 | ((utf32[1] & 0x03) << 4) | (utf32[2] >> 4);
2452 utf8[2] = 0x80 | ((utf32[2] & 0x0f) << 2) | (utf32[3] >> 6);
2453 utf8[3] = 0x80 | (utf32[3] & 0x3f);
2454 write = 4;
2455 }
2456 else
2457 {
2458 regs->psw.cc = 2;
2459 return;
2460 }
2461
2462 /* Write and commit registers */
2463 ARCH_DEP(vstorec)(utf8, write - 1, dest, r1, regs);
2464 SET_GR_A(r1, regs, (dest += write) & ADDRESS_MAXWRAP(regs));
2465 SET_GR_A(r1 + 1, regs, destlen -= write);
2466 SET_GR_A(r2, regs, (srce += 4) & ADDRESS_MAXWRAP(regs));
2467 SET_GR_A(r2 + 1, regs, srcelen -= 4);
2468
2469 xlated += 4;
2470 }
2471
2472 /* CPU determined number of characters reached */
2473 regs->psw.cc = 3;
2474 }
2475
2476 /*-------------------------------------------------------------------*/
2477 /* B9B3 CU42 - Convert UTF-32 to UTF-16 [RRE] */
2478 /*-------------------------------------------------------------------*/
DEF_INST(convert_utf32_to_utf16)2479 DEF_INST(convert_utf32_to_utf16)
2480 {
2481 VADR dest; /* Destination address */
2482 GREG destlen; /* Destination length */
2483 int r1;
2484 int r2;
2485 VADR srce; /* Source address */
2486 GREG srcelen; /* Source length */
2487 BYTE utf16[4]; /* utf16 character(s) */
2488 BYTE utf32[4]; /* utf32 character(s) */
2489 int write; /* Bytes written */
2490 int xlated; /* characters translated */
2491 BYTE zabcd; /* Work value */
2492
2493 RRE(inst, regs, r1, r2);
2494 ODD2_CHECK(r1, r2, regs);
2495
2496 /* Get paramaters */
2497 dest = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
2498 destlen = GR_A(r1 + 1, regs);
2499 srce = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
2500 srcelen = GR_A(r2 + 1, regs);
2501
2502 /* Initialize number of translated charachters */
2503 xlated = 0;
2504 while(xlated < 4096)
2505 {
2506 /* Check end of source or destination */
2507 if(srcelen < 4)
2508 {
2509 regs->psw.cc = 0;
2510 return;
2511 }
2512 if(destlen < 2)
2513 {
2514 regs->psw.cc = 1;
2515 return;
2516 }
2517
2518 /* Get 4 bytes */
2519 ARCH_DEP(vfetchc)(utf32, 3, srce, r2, regs);
2520
2521 if(utf32[0] != 0x00)
2522 {
2523 regs->psw.cc = 2;
2524 return;
2525 }
2526 else if(utf32[1] == 0x00 && (utf32[2] <= 0xd7 || utf32[2] >= 0xdc))
2527 {
2528 /* xlate range 00000000-0000d7ff and 0000dc00-0000ffff */
2529 /* 00000000 00000000 abcdefgh ijklmnop -> abcdefgh ijklmnop */
2530 utf16[0] = utf32[2];
2531 utf16[1] = utf32[3];
2532 write = 2;
2533 }
2534 else if(utf32[1] >= 0x01 && utf32[1] <= 0x10)
2535 {
2536 /* Check end of destination */
2537 if(destlen < 4)
2538 {
2539 regs->psw.cc = 1;
2540 return;
2541 }
2542
2543 /* xlate range 00010000-0010ffff */
2544 /* 00000000 000uvwxy efghijkl mnopqrst -> 110110ab cdefghij 110111kl mnopqrst */
2545 /* 000zabcd = 000uvwxy - 1 */
2546 zabcd = (utf32[1] - 1) & 0x0f;
2547 utf16[0] = 0xd8 | (zabcd >> 2);
2548 utf16[1] = (zabcd << 6) | (utf32[2] >> 2);
2549 utf16[2] = 0xdc | (utf32[2] & 0x03);
2550 utf16[3] = utf32[3];
2551 write = 4;
2552 }
2553 else
2554 {
2555 regs->psw.cc = 2;
2556 return;
2557 }
2558
2559 /* Write and commit registers */
2560 ARCH_DEP(vstorec)(utf16, write - 1, dest, r1, regs);
2561 SET_GR_A(r1, regs, (dest += write) & ADDRESS_MAXWRAP(regs));
2562 SET_GR_A(r1 + 1, regs, destlen -= write);
2563 SET_GR_A(r2, regs, (srce += 4) & ADDRESS_MAXWRAP(regs));
2564 SET_GR_A(r2 + 1, regs, srcelen -= 4);
2565
2566 xlated += 4;
2567 }
2568
2569 /* CPU determined number of characters reached */
2570 regs->psw.cc = 3;
2571 }
2572
2573 /*-------------------------------------------------------------------*/
2574 /* B9BE SRSTU - Search String Unicode [RRE] */
2575 /*-------------------------------------------------------------------*/
DEF_INST(search_string_unicode)2576 DEF_INST(search_string_unicode)
2577 {
2578 VADR addr1, addr2; /* End/start addresses */
2579 int i; /* Loop counter */
2580 int r1, r2; /* Values of R fields */
2581 U16 sbyte; /* String character */
2582 U16 termchar; /* Terminating character */
2583
2584 RRE(inst, regs, r1, r2);
2585
2586 /* Program check if bits 0-15 of register 0 not zero */
2587 if(regs->GR_L(0) & 0xFFFF0000)
2588 regs->program_interrupt (regs, PGM_SPECIFICATION_EXCEPTION);
2589
2590 /* Load string terminating character from register 0 bits 16-31 */
2591 termchar = (U16) regs->GR(0);
2592
2593 /* Determine the operand end and start addresses */
2594 addr1 = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
2595 addr2 = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
2596
2597 /* Search up to 256 bytes or until end of operand */
2598 for(i = 0; i < 0x100; i++)
2599 {
2600 /* If operand end address has been reached, return condition
2601 code 2 and leave the R1 and R2 registers unchanged */
2602 if(addr2 == addr1)
2603 {
2604 regs->psw.cc = 2;
2605 return;
2606 }
2607
2608 /* Fetch 2 bytes from the operand */
2609 sbyte = ARCH_DEP(vfetch2)(addr2, r2, regs );
2610
2611 /* If the terminating character was found, return condition
2612 code 1 and load the address of the character into R1 */
2613 if(sbyte == termchar)
2614 {
2615 SET_GR_A(r1, regs, addr2);
2616 regs->psw.cc = 1;
2617 return;
2618 }
2619
2620 /* Increment operand address */
2621 addr2 += 2;
2622 addr2 &= ADDRESS_MAXWRAP(regs);
2623
2624 } /* end for(i) */
2625
2626 /* Set R2 to point to next character of operand */
2627 SET_GR_A(r2, regs, addr2);
2628
2629 /* Return condition code 3 */
2630 regs->psw.cc = 3;
2631 }
2632
2633 /*-------------------------------------------------------------------*/
2634 /* D0 TRTR - Translate and Test Reverse [SS] */
2635 /*-------------------------------------------------------------------*/
DEF_INST(translate_and_test_reverse)2636 DEF_INST(translate_and_test_reverse)
2637 {
2638 int b1, b2; /* Values of base field */
2639 int cc = 0; /* Condition code */
2640 BYTE dbyte; /* Byte work areas */
2641 VADR effective_addr1;
2642 VADR effective_addr2; /* Effective addresses */
2643 int i; /* Integer work areas */
2644 int l; /* Lenght byte */
2645 BYTE sbyte; /* Byte work areas */
2646
2647 SS_L(inst, regs, l, b1, effective_addr1, b2, effective_addr2);
2648
2649 /* Process first operand from right to left*/
2650 for(i = 0; i <= l; i++)
2651 {
2652 /* Fetch argument byte from first operand */
2653 dbyte = ARCH_DEP(vfetchb)(effective_addr1, b1, regs);
2654
2655 /* Fetch function byte from second operand */
2656 sbyte = ARCH_DEP(vfetchb)((effective_addr2 + dbyte) & ADDRESS_MAXWRAP(regs), b2, regs);
2657
2658 /* Test for non-zero function byte */
2659 if(sbyte != 0)
2660 {
2661 /* Store address of argument byte in register 1 */
2662 #if defined(FEATURE_ESAME)
2663 if(regs->psw.amode64)
2664 regs->GR_G(1) = effective_addr1;
2665 else
2666 #endif
2667 if(regs->psw.amode)
2668 {
2669 /* Note: TRTR differs from TRT in 31 bit mode.
2670 TRTR leaves bit 32 unchanged, TRT clears bit 32 */
2671 regs->GR_L(1) &= 0x80000000;
2672 regs->GR_L(1) |= effective_addr1;
2673 }
2674 else
2675 regs->GR_LA24(1) = effective_addr1;
2676
2677 /* Store function byte in low-order byte of reg.2 */
2678 regs->GR_LHLCL(2) = sbyte;
2679
2680 /* Set condition code 2 if argument byte was last byte
2681 of first operand, otherwise set condition code 1 */
2682 cc = (i == l) ? 2 : 1;
2683
2684 /* Terminate the operation at this point */
2685 break;
2686
2687 } /* end if(sbyte) */
2688
2689 /* Decrement first operand address */
2690 effective_addr1--; /* Another difference with TRT */
2691 effective_addr1 &= ADDRESS_MAXWRAP(regs);
2692
2693 } /* end for(i) */
2694
2695 /* Update the condition code */
2696 regs->psw.cc = cc;
2697 }
2698 #endif /*defined(FEATURE_EXTENDED_TRANSLATION_FACILITY_3)*/
2699
2700 #ifdef FEATURE_PARSING_ENHANCEMENT_FACILITY
2701 /*-------------------------------------------------------------------*/
2702 /* B9BF TRTE - Translate and Test Extended [RRF] */
2703 /*-------------------------------------------------------------------*/
DEF_INST(translate_and_test_extended)2704 DEF_INST(translate_and_test_extended)
2705 {
2706 int a_bit; /* Argument-Character Control (A) */
2707 U32 arg_ch; /* Argument character */
2708 VADR buf_addr; /* first argument address */
2709 GREG buf_len; /* First argument length */
2710 int f_bit; /* Function-Code Control (F) */
2711 U32 fc; /* Function-Code */
2712 VADR fct_addr; /* Function-code table address */
2713 int l_bit; /* Argument-Character Limit (L) */
2714 int m3;
2715 int processed; /* # bytes processed */
2716 int r1;
2717 int r2;
2718
2719 RRF_M(inst, regs, r1, r2, m3);
2720
2721 a_bit = ((m3 & 0x08) ? 1 : 0);
2722 f_bit = ((m3 & 0x04) ? 1 : 0);
2723 l_bit = ((m3 & 0x02) ? 1 : 0);
2724
2725 buf_addr = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
2726 buf_len = GR_A(r1 + 1, regs);
2727
2728 fct_addr = regs->GR(1) & ADDRESS_MAXWRAP(regs);
2729
2730 if(unlikely((a_bit && (buf_len % 1)) || r1 & 0x01))
2731 regs->program_interrupt(regs, PGM_SPECIFICATION_EXCEPTION);
2732
2733 fc = 0;
2734 processed = 0;
2735 while(buf_len && !fc && processed < 16384)
2736 {
2737 if(a_bit)
2738 {
2739 arg_ch = ARCH_DEP(vfetch2)(buf_addr, r1, regs);
2740 }
2741 else
2742 {
2743 arg_ch = ARCH_DEP(vfetchb)(buf_addr, r1, regs);
2744 }
2745
2746 if(l_bit && arg_ch > 255)
2747 fc = 0;
2748 else
2749 {
2750 if(f_bit)
2751 fc = ARCH_DEP(vfetch2)((fct_addr + (arg_ch * 2)) & ADDRESS_MAXWRAP(regs), 1, regs);
2752 else
2753 fc = ARCH_DEP(vfetchb)((fct_addr + arg_ch) & ADDRESS_MAXWRAP(regs), 1, regs);
2754 }
2755
2756 if(!fc)
2757 {
2758 if(a_bit)
2759 {
2760 buf_len -= 2;
2761 processed += 2;
2762 buf_addr = (buf_addr + 2) & ADDRESS_MAXWRAP(regs);
2763 }
2764 else
2765 {
2766 buf_len--;
2767 processed++;
2768 buf_addr = (buf_addr + 1) & ADDRESS_MAXWRAP(regs);
2769 }
2770 }
2771 }
2772
2773 /* Commit registers */
2774 SET_GR_A(r1, regs, buf_addr);
2775 SET_GR_A(r1 + 1, regs, buf_len);
2776
2777 /* Check if CPU determined number of bytes have been processed */
2778 if(buf_len && !fc)
2779 {
2780 regs->psw.cc = 3;
2781 return;
2782 }
2783
2784 /* Set function code */
2785 if(likely(r2 != r1 && r2 != r1 + 1))
2786 SET_GR_A(r2, regs, fc);
2787
2788 /* Set condition code */
2789 if(fc)
2790 regs->psw.cc = 1;
2791 else
2792 regs->psw.cc = 0;
2793 }
2794
2795 /*-------------------------------------------------------------------*/
2796 /* B9BD TRTRE - Translate and Test Reverse Extended [RRF] */
2797 /*-------------------------------------------------------------------*/
DEF_INST(translate_and_test_reverse_extended)2798 DEF_INST(translate_and_test_reverse_extended)
2799 {
2800 int a_bit; /* Argument-Character Control (A) */
2801 U32 arg_ch; /* Argument character */
2802 VADR buf_addr; /* first argument address */
2803 GREG buf_len; /* First argument length */
2804 int f_bit; /* Function-Code Control (F) */
2805 U32 fc; /* Function-Code */
2806 VADR fct_addr; /* Function-code table address */
2807 int l_bit; /* Argument-Character Limit (L) */
2808 int m3;
2809 int processed; /* # bytes processed */
2810 int r1;
2811 int r2;
2812
2813 RRF_M(inst, regs, r1, r2, m3);
2814
2815 a_bit = ((m3 & 0x08) ? 1 : 0);
2816 f_bit = ((m3 & 0x04) ? 1 : 0);
2817 l_bit = ((m3 & 0x02) ? 1 : 0);
2818
2819 buf_addr = regs->GR(r1) & ADDRESS_MAXWRAP(regs);
2820 buf_len = GR_A(r1 + 1, regs);
2821
2822 fct_addr = regs->GR(1) & ADDRESS_MAXWRAP(regs);
2823
2824 if(unlikely((a_bit && (buf_len % 1)) || r1 & 0x01))
2825 regs->program_interrupt(regs, PGM_SPECIFICATION_EXCEPTION);
2826
2827 fc = 0;
2828 processed = 0;
2829 while(buf_len && !fc && processed < 16384)
2830 {
2831 if(a_bit)
2832 {
2833 arg_ch = ARCH_DEP(vfetch2)(buf_addr, r1, regs);
2834 }
2835 else
2836 {
2837 arg_ch = ARCH_DEP(vfetchb)(buf_addr, r1, regs);
2838 }
2839
2840 if(l_bit && arg_ch > 255)
2841 fc = 0;
2842 else
2843 {
2844 if(f_bit)
2845 fc = ARCH_DEP(vfetch2)((fct_addr + (arg_ch * 2)) & ADDRESS_MAXWRAP(regs), 1, regs);
2846 else
2847 fc = ARCH_DEP(vfetchb)((fct_addr + arg_ch) & ADDRESS_MAXWRAP(regs), 1, regs);
2848 }
2849
2850 if(!fc)
2851 {
2852 if(a_bit)
2853 {
2854 buf_len -= 2;
2855 processed += 2;
2856 buf_addr = (buf_addr - 2) & ADDRESS_MAXWRAP(regs);
2857 }
2858 else
2859 {
2860 buf_len--;
2861 processed++;
2862 buf_addr = (buf_addr - 1) & ADDRESS_MAXWRAP(regs);
2863 }
2864 }
2865 }
2866
2867 /* Commit registers */
2868 SET_GR_A(r1, regs, buf_addr);
2869 SET_GR_A(r1 + 1, regs, buf_len);
2870
2871 /* Check if CPU determined number of bytes have been processed */
2872 if(buf_len && !fc)
2873 {
2874 regs->psw.cc = 3;
2875 return;
2876 }
2877
2878 /* Set function code */
2879 if(likely(r2 != r1 && r2 != r1 + 1))
2880 SET_GR_A(r2, regs, fc);
2881
2882 /* Set condition code */
2883 if(fc)
2884 regs->psw.cc = 1;
2885 else
2886 regs->psw.cc = 0;
2887 }
2888 #endif /* FEATURE_PARSING_ENHANCEMENT_FACILITY */
2889
2890 #if !defined(_GEN_ARCH)
2891
2892 #if defined(_ARCHMODE2)
2893 #define _GEN_ARCH _ARCHMODE2
2894 #include "general2.c"
2895 #endif
2896
2897 #if defined(_ARCHMODE3)
2898 #undef _GEN_ARCH
2899 #define _GEN_ARCH _ARCHMODE3
2900 #include "general2.c"
2901 #endif
2902
2903 #endif /*!defined(_GEN_ARCH)*/
2904