1 /* IO.C (c) Copyright Roger Bowler, 1994-2009 */
2 /* ESA/390 CPU Emulator */
3
4 /* Interpretive Execution - (c) Copyright Jan Jaeger, 1999-2009 */
5 /* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2009 */
6
7 /*-------------------------------------------------------------------*/
8 /* This module implements all I/O instructions of the */
9 /* S/370 and ESA/390 architectures, as described in the manuals */
10 /* GA22-7000-03 System/370 Principles of Operation */
11 /* SA22-7201-06 ESA/390 Principles of Operation */
12 /*-------------------------------------------------------------------*/
13
14 /*-------------------------------------------------------------------*/
15 /* Additional credits: */
16 /* STCPS and SCHM instructions by Jan Jaeger */
17 /* STCRW instruction by Jan Jaeger */
18 /* Instruction decode by macros - Jan Jaeger */
19 /* Instruction decode rework - Jan Jaeger */
20 /* Correct nullification of TIO and TSCH - Jan Jaeger */
21 /* Lock device during MSCH update - Jan Jaeger */
22 /* SIE support - Jan Jaeger */
23 /* SAL instruction added - Jan Jaeger */
24 /* RCHP instruction added - Jan Jaeger */
25 /* CONCS instruction added - Jan Jaeger */
26 /* DISCS instruction added - Jan Jaeger */
27 /* TPI fix - Jay Maynard, found by Greg Smith */
28 /* STCRW instruction nullification correction - Jan Jaeger */
29 /* I/O rate counter - Valery Pogonchenko */
30 /* 64-bit IDAW support - Roger Bowler v209 @IWZ*/
31 /*-------------------------------------------------------------------*/
32
33 #include "hstdinc.h"
34
35 #if !defined(_HENGINE_DLL_)
36 #define _HENGINE_DLL_
37 #endif
38
39 #if !defined(_IO_C_)
40 #define _IO_C_
41 #endif
42
43 #include "hercules.h"
44
45 #include "opcode.h"
46
47 #include "inline.h"
48
49 #undef PTIO
50 #if defined(FEATURE_CHANNEL_SUBSYSTEM)
51 #define PTIO(_class, _name) \
52 PTT(PTT_CL_ ## _class,_name,regs->GR_L(1),(U32)(effective_addr2 & 0xffffffff),regs->psw.IA_L)
53 #else
54 #define PTIO(_class, _name) \
55 PTT(PTT_CL_ ## _class,_name,(U32)(effective_addr2 & 0xffffffff),0,regs->psw.IA_L)
56 #endif
57
58 #if defined(FEATURE_CHANNEL_SUBSYSTEM)
59
60 /*-------------------------------------------------------------------*/
61 /* B230 CSCH - Clear Subchannel [S] */
62 /*-------------------------------------------------------------------*/
DEF_INST(clear_subchannel)63 DEF_INST(clear_subchannel)
64 {
65 int b2; /* Effective addr base */
66 VADR effective_addr2; /* Effective address */
67 DEVBLK *dev; /* -> device block */
68
69 S(inst, regs, b2, effective_addr2);
70
71 PRIV_CHECK(regs);
72
73 #if defined(_FEATURE_IO_ASSIST)
74 if(SIE_STATNB(regs, EC0, IOA) && !regs->sie_pref)
75 #endif
76 SIE_INTERCEPT(regs);
77
78 PTIO(IO,"CSCH");
79
80 /* Program check if the ssid including lcss is invalid */
81 SSID_CHECK(regs);
82
83 /* Locate the device block for this subchannel */
84 dev = find_device_by_subchan (regs->GR_L(1));
85
86 /* Condition code 3 if subchannel does not exist,
87 is not valid, or is not enabled */
88 if (dev == NULL
89 || (dev->pmcw.flag5 & PMCW5_V) == 0
90 || (dev->pmcw.flag5 & PMCW5_E) == 0)
91 {
92 PTIO(ERR,"*CSCH");
93 #if defined(_FEATURE_IO_ASSIST)
94 SIE_INTERCEPT(regs);
95 #endif
96 regs->psw.cc = 3;
97 return;
98 }
99
100 /* Perform clear subchannel and set condition code zero */
101 clear_subchan (regs, dev);
102
103 regs->psw.cc = 0;
104
105 }
106
107
108 /*-------------------------------------------------------------------*/
109 /* B231 HSCH - Halt Subchannel [S] */
110 /*-------------------------------------------------------------------*/
DEF_INST(halt_subchannel)111 DEF_INST(halt_subchannel)
112 {
113 int b2; /* Effective addr base */
114 VADR effective_addr2; /* Effective address */
115 DEVBLK *dev; /* -> device block */
116
117 S(inst, regs, b2, effective_addr2);
118
119 PRIV_CHECK(regs);
120
121 #if defined(_FEATURE_IO_ASSIST)
122 if(SIE_STATNB(regs, EC0, IOA) && !regs->sie_pref)
123 #endif
124 SIE_INTERCEPT(regs);
125
126 PTIO(IO,"HSCH");
127
128 /* Program check if the ssid including lcss is invalid */
129 SSID_CHECK(regs);
130
131 /* Locate the device block for this subchannel */
132 dev = find_device_by_subchan (regs->GR_L(1));
133
134 /* Condition code 3 if subchannel does not exist,
135 is not valid, or is not enabled */
136 if (dev == NULL
137 || (dev->pmcw.flag5 & PMCW5_V) == 0
138 || (dev->pmcw.flag5 & PMCW5_E) == 0)
139 {
140 PTIO(ERR,"*HSCH");
141 #if defined(_FEATURE_IO_ASSIST)
142 SIE_INTERCEPT(regs);
143 #endif
144 regs->psw.cc = 3;
145 return;
146 }
147
148 /* Perform halt subchannel and set condition code */
149 regs->psw.cc = halt_subchan (regs, dev);
150
151 }
152
153
154 /*-------------------------------------------------------------------*/
155 /* B232 MSCH - Modify Subchannel [S] */
156 /*-------------------------------------------------------------------*/
DEF_INST(modify_subchannel)157 DEF_INST(modify_subchannel)
158 {
159 int b2; /* Effective addr base */
160 VADR effective_addr2; /* Effective address */
161 DEVBLK *dev; /* -> device block */
162 PMCW pmcw; /* Path management ctl word */
163
164 S(inst, regs, b2, effective_addr2);
165
166 PRIV_CHECK(regs);
167
168 SIE_INTERCEPT(regs);
169
170 PTIO(IO,"MSCH");
171
172 FW_CHECK(effective_addr2, regs);
173
174 /* Fetch the updated path management control word */
175 ARCH_DEP(vfetchc) ( &pmcw, sizeof(PMCW)-1, effective_addr2, b2, regs );
176
177 /* Program check if reserved bits are not zero */
178 if ((pmcw.flag4 & PMCW4_RESV)
179 || (pmcw.flag5 & PMCW5_LM) == PMCW5_LM_RESV
180 #if !defined(_FEATURE_IO_ASSIST)
181 || (pmcw.flag4 & PMCW4_A)
182 || (pmcw.zone != 0)
183 || (pmcw.flag25 & PMCW25_VISC)
184 || (pmcw.flag27 & PMCW27_I)
185 #endif
186 || (pmcw.flag26 != 0)
187 || (pmcw.flag27 & PMCW27_RESV))
188 ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
189
190 /* Program check if the ssid including lcss is invalid */
191 SSID_CHECK(regs);
192
193 /* Locate the device block for this subchannel */
194 dev = find_device_by_subchan (regs->GR_L(1));
195
196 /* Condition code 3 if subchannel does not exist */
197 if (dev == NULL)
198 {
199 PTIO(ERR,"*MSCH");
200 regs->psw.cc = 3;
201 return;
202 }
203
204 /* If the subchannel is invalid then return cc0 */
205 if (!(dev->pmcw.flag5 & PMCW5_V))
206 {
207 PTIO(ERR,"*MSCH");
208 regs->psw.cc = 0;
209 return;
210 }
211
212 /* Perform serialization and checkpoint-synchronization */
213 PERFORM_SERIALIZATION (regs);
214 PERFORM_CHKPT_SYNC (regs);
215
216 /* Obtain the device lock */
217 obtain_lock (&dev->lock);
218
219 /* Condition code 1 if subchannel is status pending
220 with other than intermediate status */
221 if ((dev->scsw.flag3 & SCSW3_SC_PEND)
222 && !(dev->scsw.flag3 & SCSW3_SC_INTER))
223 {
224 PTIO(ERR,"*MSCH");
225 regs->psw.cc = 1;
226 release_lock (&dev->lock);
227 return;
228 }
229
230 /* Condition code 2 if subchannel is busy */
231 if (dev->busy || IOPENDING(dev))
232 {
233 PTIO(ERR,"*MSCH");
234 regs->psw.cc = 2;
235 release_lock (&dev->lock);
236 return;
237 }
238
239 /* Update the enabled (E), limit mode (LM),
240 and measurement mode (MM), and multipath (D) bits */
241 dev->pmcw.flag5 &=
242 ~(PMCW5_E | PMCW5_LM | PMCW5_MM | PMCW5_D);
243 dev->pmcw.flag5 |= (pmcw.flag5 &
244 (PMCW5_E | PMCW5_LM | PMCW5_MM | PMCW5_D));
245
246 /* Update the measurement block index */
247 memcpy (dev->pmcw.mbi, pmcw.mbi, sizeof(HWORD));
248
249 /* Update the interruption parameter */
250 memcpy (dev->pmcw.intparm, pmcw.intparm, sizeof(FWORD));
251
252 /* Update the ISC and A fields */
253 dev->pmcw.flag4 &= ~(PMCW4_ISC | PMCW4_A);
254 dev->pmcw.flag4 |= (pmcw.flag4 & (PMCW4_ISC | PMCW4_A));
255
256 /* Update the path management (LPM and POM) fields */
257 dev->pmcw.lpm = pmcw.lpm;
258 dev->pmcw.pom = pmcw.pom;
259
260 /* Update zone, VISC, I and S bit */
261 dev->pmcw.zone = pmcw.zone;
262 dev->pmcw.flag25 &= ~(PMCW25_VISC);
263 dev->pmcw.flag25 |= (pmcw.flag25 & PMCW25_VISC);
264 dev->pmcw.flag26 = pmcw.flag26;
265 dev->pmcw.flag27 = pmcw.flag27;
266
267 #if defined(_FEATURE_IO_ASSIST)
268 /* Relate the device storage view to the requested zone */
269 { RADR mso, msl;
270 mso = sysblk.zpb[dev->pmcw.zone].mso << 20;
271 msl = (sysblk.zpb[dev->pmcw.zone].msl << 20) | 0xFFFFF;
272
273 /* Ensure channel program checks on incorrect zone defs */
274 if(mso > (sysblk.mainsize-1) || msl > (sysblk.mainsize-1) || mso > msl)
275 mso = msl = 0;
276
277 dev->mainstor = &(sysblk.mainstor[mso]);
278 dev->mainlim = msl - mso;
279 dev->storkeys = &(STORAGE_KEY(mso, &sysblk));
280 }
281 #endif /*defined(_FEATURE_IO_ASSIST)*/
282
283 /* Set device priority from the interruption subclass bits */
284 dev->priority = (dev->pmcw.flag4 & PMCW4_ISC) >> 3;
285
286 release_lock (&dev->lock);
287
288 /* Set condition code 0 */
289 regs->psw.cc = 0;
290
291 }
292
293
294 /*-------------------------------------------------------------------*/
295 /* B23B RCHP - Reset Channel Path [S] */
296 /*-------------------------------------------------------------------*/
DEF_INST(reset_channel_path)297 DEF_INST(reset_channel_path)
298 {
299 int b2; /* Base of effective addr */
300 VADR effective_addr2; /* Effective address */
301 BYTE chpid;
302
303 S(inst, regs, b2, effective_addr2);
304
305 PRIV_CHECK(regs);
306
307 SIE_INTERCEPT(regs);
308
309 PTIO(IO,"RCHP");
310
311 /* Program check if reg 1 bits 0-23 not zero */
312 if(regs->GR_L(1) & 0xFFFFFF00)
313 ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
314
315 chpid = regs->GR_L(1) & 0xFF;
316
317 if( !(regs->psw.cc = chp_reset(regs, chpid)) )
318 {
319 OBTAIN_INTLOCK(regs);
320 sysblk.chp_reset[chpid/32] |= 0x80000000 >> (chpid % 32);
321 ON_IC_CHANRPT;
322 WAKEUP_CPUS_MASK (sysblk.waiting_mask);
323 RELEASE_INTLOCK(regs);
324 }
325
326 RETURN_INTCHECK(regs);
327
328 }
329
330
331 /*-------------------------------------------------------------------*/
332 /* B238 RSCH - Resume Subchannel [S] */
333 /*-------------------------------------------------------------------*/
DEF_INST(resume_subchannel)334 DEF_INST(resume_subchannel)
335 {
336 int b2; /* Effective addr base */
337 VADR effective_addr2; /* Effective address */
338 DEVBLK *dev; /* -> device block */
339
340 S(inst, regs, b2, effective_addr2);
341
342 PRIV_CHECK(regs);
343
344 #if defined(_FEATURE_IO_ASSIST)
345 if(SIE_STATNB(regs, EC0, IOA) && !regs->sie_pref)
346 #endif
347 SIE_INTERCEPT(regs);
348
349 PTIO(IO,"RSCH");
350
351 /* Program check if the ssid including lcss is invalid */
352 SSID_CHECK(regs);
353
354 /* Locate the device block for this subchannel */
355 dev = find_device_by_subchan (regs->GR_L(1));
356
357 /* Condition code 3 if subchannel does not exist,
358 is not valid, or is not enabled */
359 if (dev == NULL
360 || (dev->pmcw.flag5 & PMCW5_V) == 0
361 || (dev->pmcw.flag5 & PMCW5_E) == 0)
362 {
363 PTIO(ERR,"*RSCH");
364 #if defined(_FEATURE_IO_ASSIST)
365 SIE_INTERCEPT(regs);
366 #endif
367 regs->psw.cc = 3;
368 return;
369 }
370
371 /* Perform resume subchannel and set condition code */
372 regs->psw.cc = resume_subchan (regs, dev);
373
374 regs->siocount++;
375 }
376
377
378 /*-------------------------------------------------------------------*/
379 /* B237 SAL - Set Address Limit [S] */
380 /*-------------------------------------------------------------------*/
DEF_INST(set_address_limit)381 DEF_INST(set_address_limit)
382 {
383 int b2; /* Effective addr base */
384 VADR effective_addr2; /* Effective address */
385
386 S(inst, regs, b2, effective_addr2);
387
388 PRIV_CHECK(regs);
389
390 SIE_INTERCEPT(regs);
391
392 PTIO(IO,"SAL");
393
394 if(regs->GR_L(1) & 0x8000FFFF)
395 ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
396 else
397 sysblk.addrlimval = regs->GR_L(1);
398 }
399
400
401 /*-------------------------------------------------------------------*/
402 /* B23C SCHM - Set Channel Monitor [S] */
403 /*-------------------------------------------------------------------*/
DEF_INST(set_channel_monitor)404 DEF_INST(set_channel_monitor)
405 {
406 int b2; /* Effective addr base */
407 VADR effective_addr2; /* Effective address */
408
409 S(inst, regs, b2, effective_addr2);
410
411 PRIV_CHECK(regs);
412
413 #if defined(_FEATURE_IO_ASSIST)
414 if(SIE_STATNB(regs, EC0, IOA) && !regs->sie_pref)
415 #endif
416 SIE_INTERCEPT(regs);
417
418 PTIO(IO,"SCHM");
419
420 /* Reserved bits in gpr1 must be zero */
421 if (regs->GR_L(1) & CHM_GPR1_RESV)
422 ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
423
424 /* Program check if M bit one and gpr2 address not on
425 a 32 byte boundary or highorder bit set in ESA/390 mode */
426 if ((regs->GR_L(1) & CHM_GPR1_M)
427 && (regs->GR_L(2) & CHM_GPR2_RESV))
428 ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
429
430 #if defined(_FEATURE_IO_ASSIST)
431 /* Virtual use of I/O Assist features must be intercepted */
432 if(SIE_MODE(regs)
433 && ( (regs->GR_L(1) & CHM_GPR1_ZONE)
434 || (regs->GR_L(1) & CHM_GPR1_A) ))
435 SIE_INTERCEPT(regs);
436
437 /* Zone must be a valid zone number */
438 if (((regs->GR_L(1) & CHM_GPR1_ZONE) >> 16) >= FEATURE_SIE_MAXZONES)
439 ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
440
441 if(regs->GR_L(1) & CHM_GPR1_A)
442 #endif /*defined(_FEATURE_IO_ASSIST)*/
443 {
444 /* Set the measurement block origin address */
445 if (regs->GR_L(1) & CHM_GPR1_M)
446 {
447 sysblk.mbo = regs->GR(2);
448 sysblk.mbk = (regs->GR_L(1) & CHM_GPR1_MBK) >> 24;
449 sysblk.mbm = 1;
450 }
451 else
452 sysblk.mbm = 0;
453
454 sysblk.mbd = regs->GR_L(1) & CHM_GPR1_D;
455
456 }
457 #if defined(_FEATURE_IO_ASSIST)
458 else
459 {
460 int zone = SIE_MODE(regs) ? regs->siebk->zone :
461 ((regs->GR_L(1) & CHM_GPR1_ZONE) >> 16);
462
463 /* Set the measurement block origin address */
464 if (regs->GR_L(1) & CHM_GPR1_M)
465 {
466 sysblk.zpb[zone].mbo = regs->GR(2);
467 sysblk.zpb[zone].mbk = (regs->GR_L(1) & CHM_GPR1_MBK) >> 24;
468 sysblk.zpb[zone].mbm = 1;
469 }
470 else
471 sysblk.zpb[zone].mbm = 0;
472
473 sysblk.zpb[zone].mbd = regs->GR_L(1) & CHM_GPR1_D;
474
475 }
476 #endif /*defined(_FEATURE_IO_ASSIST)*/
477
478 }
479
480
481 /*-------------------------------------------------------------------*/
482 /* B233 SSCH - Start Subchannel [S] */
483 /*-------------------------------------------------------------------*/
DEF_INST(start_subchannel)484 DEF_INST(start_subchannel)
485 {
486 int b2; /* Effective addr base */
487 VADR effective_addr2; /* Effective address */
488 DEVBLK *dev; /* -> device block */
489 ORB orb; /* Operation request block */
490
491 S(inst, regs, b2, effective_addr2);
492
493 PRIV_CHECK(regs);
494
495 #if defined(_FEATURE_IO_ASSIST)
496 if(SIE_STATNB(regs, EC0, IOA) && !regs->sie_pref)
497 #endif
498 SIE_INTERCEPT(regs);
499
500 PTIO(IO,"SSCH");
501
502 FW_CHECK(effective_addr2, regs);
503
504 /* Fetch the operation request block */
505 ARCH_DEP(vfetchc) ( &orb, sizeof(ORB)-1, effective_addr2, b2, regs );
506
507 /* Program check if reserved bits are not zero */
508 if (orb.flag5 & ORB5_RESV
509 || orb.flag7 & ORB7_RESV
510 || orb.ccwaddr[0] & 0x80)
511 ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
512
513 #if !defined(FEATURE_INCORRECT_LENGTH_INDICATION_SUPPRESSION)
514 /* Program check if incorrect length suppression */
515 if (orb.flag7 & ORB7_L)
516 ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
517 #endif /*!defined(FEATURE_INCORRECT_LENGTH_INDICATION_SUPPRESSION)*/
518
519 #if !defined(FEATURE_MIDAW) /*@MW*/
520 /* Program check if modified indirect data addressing requested */
521 if (orb.flag7 & ORB7_D)
522 ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
523 #endif /*!defined(FEATURE_MIDAW)*/ /*@MW*/
524
525 /* Program check if the ssid including lcss is invalid */
526 SSID_CHECK(regs);
527
528 /* Locate the device block for this subchannel */
529 dev = find_device_by_subchan (regs->GR_L(1));
530
531 /* Condition code 3 if subchannel does not exist,
532 is not valid, is not enabled, or no path available */
533 if (dev == NULL
534 || (dev->pmcw.flag5 & PMCW5_V) == 0
535 || (dev->pmcw.flag5 & PMCW5_E) == 0
536 || (orb.lpm & dev->pmcw.pam) == 0)
537 {
538 PTIO(ERR,"*SSCH");
539 #if defined(_FEATURE_IO_ASSIST)
540 SIE_INTERCEPT(regs);
541 #endif
542 regs->psw.cc = 3;
543 return;
544 }
545
546 /* Perform serialization and checkpoint-synchronization */
547 PERFORM_SERIALIZATION (regs);
548 PERFORM_CHKPT_SYNC (regs);
549
550 /* Clear the path not operational mask */
551 dev->pmcw.pnom = 0;
552
553 /* Copy the logical path mask */
554 dev->pmcw.lpm = orb.lpm;
555
556 /* Start the channel program and set the condition code */
557 regs->psw.cc = ARCH_DEP(startio) (regs, dev, &orb); /*@IWZ*/
558
559 regs->siocount++;
560
561 /* Set the last path used mask */
562 if (regs->psw.cc == 0) dev->pmcw.lpum = 0x80;
563
564 }
565
566
567 /*-------------------------------------------------------------------*/
568 /* B23A STCPS - Store Channel Path Status [S] */
569 /*-------------------------------------------------------------------*/
DEF_INST(store_channel_path_status)570 DEF_INST(store_channel_path_status)
571 {
572 int b2; /* Effective addr base */
573 VADR effective_addr2; /* Effective address */
574 BYTE work[32]; /* Work area */
575
576 S(inst, regs, b2, effective_addr2);
577
578 PRIV_CHECK(regs);
579
580 SIE_INTERCEPT(regs);
581
582 PTIO(IO,"STCPS");
583
584 /* Program check if operand not on 32 byte boundary */
585 if ( effective_addr2 & 0x0000001F )
586 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
587
588 /*INCOMPLETE, SET TO ALL ZEROS*/
589 memset(work,0x00,32);
590
591 /* Store channel path status word at operand address */
592 ARCH_DEP(vstorec) ( work, 32-1, effective_addr2, b2, regs );
593
594 }
595
596
597 /*-------------------------------------------------------------------*/
598 /* B239 STCRW - Store Channel Report Word [S] */
599 /*-------------------------------------------------------------------*/
DEF_INST(store_channel_report_word)600 DEF_INST(store_channel_report_word)
601 {
602 int b2; /* Effective addr base */
603 VADR effective_addr2; /* Effective address */
604 U32 n; /* Integer work area */
605
606 S(inst, regs, b2, effective_addr2);
607
608 PTIO(IO,"STCRW");
609
610 PRIV_CHECK(regs);
611
612 SIE_INTERCEPT(regs);
613
614 FW_CHECK(effective_addr2, regs);
615
616 /* Validate write access to operand before taking any
617 pending channel report word off the queue */
618 ARCH_DEP(validate_operand) (effective_addr2, b2, 0, ACCTYPE_WRITE, regs);
619
620 /* Obtain any pending channel report */
621 n = channel_report(regs);
622
623 /* Store channel report word at operand address */
624 ARCH_DEP(vstore4) ( n, effective_addr2, b2, regs );
625
626 /* Indicate if channel report or zeros were stored */
627 regs->psw.cc = (n == 0) ? 1 : 0;
628
629 }
630
631
632 /*-------------------------------------------------------------------*/
633 /* B234 STSCH - Store Subchannel [S] */
634 /*-------------------------------------------------------------------*/
DEF_INST(store_subchannel)635 DEF_INST(store_subchannel)
636 {
637 int b2; /* Effective addr base */
638 VADR effective_addr2; /* Effective address */
639 DEVBLK *dev; /* -> device block */
640 SCHIB schib; /* Subchannel information blk*/
641
642 S(inst, regs, b2, effective_addr2);
643
644 PRIV_CHECK(regs);
645
646 SIE_INTERCEPT(regs);
647
648 PTIO(IO,"STSCH");
649
650 /* Program check if the ssid including lcss is invalid */
651 SSID_CHECK(regs);
652
653 /* Locate the device block for this subchannel */
654 dev = find_device_by_subchan (regs->GR_L(1));
655
656 /* Set condition code 3 if subchannel does not exist */
657 if (dev == NULL)
658 {
659 PTIO(ERR,"*STSCH");
660 regs->psw.cc = 3;
661 return;
662 }
663
664 FW_CHECK(effective_addr2, regs);
665
666 /* Perform serialization and checkpoint-synchronization */
667 PERFORM_SERIALIZATION (regs);
668 PERFORM_CHKPT_SYNC (regs);
669
670 /* Build the subchannel information block */
671 schib.pmcw = dev->pmcw;
672
673 obtain_lock (&dev->lock);
674 if (dev->pciscsw.flag3 & SCSW3_SC_PEND)
675 schib.scsw = dev->pciscsw;
676 else
677 schib.scsw = dev->scsw;
678 release_lock (&dev->lock);
679
680 memset (schib.moddep, 0x00, sizeof(schib.moddep));
681
682 /* Store the subchannel information block */
683 ARCH_DEP(vstorec) ( &schib, sizeof(SCHIB)-1, effective_addr2,
684 b2, regs );
685
686 /* Set condition code 0 */
687 regs->psw.cc = 0;
688
689 }
690
691
692 /*-------------------------------------------------------------------*/
693 /* B236 TPI - Test Pending Interruption [S] */
694 /*-------------------------------------------------------------------*/
DEF_INST(test_pending_interruption)695 DEF_INST(test_pending_interruption)
696 {
697 int b2; /* Effective addr base */
698 VADR effective_addr2; /* Effective address */
699 PSA *psa; /* -> Prefixed storage area */
700 U64 dreg; /* Double register work area */
701 U32 ioid; /* I/O interruption address */
702 U32 ioparm; /* I/O interruption parameter*/
703 U32 iointid; /* I/O interruption ident */
704 int icode; /* Intercept code */
705 RADR pfx; /* Prefix */
706
707 S(inst, regs, b2, effective_addr2);
708
709 PRIV_CHECK(regs);
710
711 #if defined(_FEATURE_IO_ASSIST)
712 if(SIE_STATNB(regs, EC0, IOA) && !regs->sie_pref)
713 #endif
714 SIE_INTERCEPT(regs);
715
716 PTIO(IO,"TPI");
717
718 FW_CHECK(effective_addr2, regs);
719
720 /* validate operand before taking any action */
721 if ( effective_addr2 != 0 )
722 ARCH_DEP(validate_operand) (effective_addr2, b2, 8-1,
723 ACCTYPE_WRITE, regs);
724
725 /* Perform serialization and checkpoint-synchronization */
726 PERFORM_SERIALIZATION (regs);
727 PERFORM_CHKPT_SYNC (regs);
728
729 if( IS_IC_IOPENDING )
730 {
731 /* Obtain the interrupt lock */
732 OBTAIN_INTLOCK(regs);
733
734 /* Test and clear pending interrupt, set condition code */
735 icode = ARCH_DEP(present_io_interrupt) (regs, &ioid, &ioparm,
736 &iointid, NULL);
737
738 /* Release the interrupt lock */
739 RELEASE_INTLOCK(regs);
740
741 /* Store the SSID word and I/O parameter if an interrupt was pending */
742 if (icode)
743 {
744 if ( effective_addr2 == 0
745 #if defined(_FEATURE_IO_ASSIST)
746 || icode != SIE_NO_INTERCEPT
747 #endif
748 )
749 {
750 #if defined(_FEATURE_IO_ASSIST)
751 if(icode != SIE_NO_INTERCEPT)
752 {
753 /* Point to SIE copy of PSA in state descriptor */
754 psa = (void*)(regs->hostregs->mainstor + SIE_STATE(regs) + SIE_II_PSA_OFFSET);
755 STORAGE_KEY(SIE_STATE(regs), regs->hostregs) |= (STORKEY_REF | STORKEY_CHANGE);
756 }
757 else
758 #endif
759 {
760 /* Point to PSA in main storage */
761 pfx = regs->PX;
762 SIE_TRANSLATE(&pfx, ACCTYPE_SIE, regs);
763 psa = (void*)(regs->mainstor + pfx);
764 STORAGE_KEY(pfx, regs) |= (STORKEY_REF | STORKEY_CHANGE);
765 }
766
767 /* If operand address is zero, store in PSA */
768 STORE_FW(psa->ioid,ioid);
769 STORE_FW(psa->ioparm,ioparm);
770 #if defined(FEATURE_ESAME) || defined(_FEATURE_IO_ASSIST)
771 STORE_FW(psa->iointid,iointid);
772 #endif /*defined(FEATURE_ESAME)*/
773
774 #if defined(_FEATURE_IO_ASSIST)
775 if(icode != SIE_NO_INTERCEPT)
776 longjmp(regs->progjmp,SIE_INTERCEPT_IOINST);
777 #endif
778 }
779 else
780 {
781 /* Otherwise store at operand location */
782 dreg = ((U64)ioid << 32) | ioparm;
783 ARCH_DEP(vstore8) ( dreg, effective_addr2, b2, regs );
784 }
785 }
786 }
787 else
788 {
789 #if defined(_FEATURE_IO_ASSIST)
790 /* If no I/O assisted devices have pending interrupts
791 then we must intercept */
792 SIE_INTERCEPT(regs);
793 #endif
794 icode = 0;
795 }
796
797 regs->psw.cc = (icode == 0) ? 0 : 1;
798 }
799
800
801 /*-------------------------------------------------------------------*/
802 /* B235 TSCH - Test Subchannel [S] */
803 /*-------------------------------------------------------------------*/
DEF_INST(test_subchannel)804 DEF_INST(test_subchannel)
805 {
806 int b2; /* Effective addr base */
807 VADR effective_addr2; /* Effective address */
808 DEVBLK *dev; /* -> device block */
809 IRB irb; /* Interruption response blk */
810 int cc; /* Condition Code */
811
812 S(inst, regs, b2, effective_addr2);
813
814 PRIV_CHECK(regs);
815
816 #if defined(_FEATURE_IO_ASSIST)
817 if(SIE_STATNB(regs, EC0, IOA) && !regs->sie_pref)
818 #endif
819 SIE_INTERCEPT(regs);
820
821 PTIO(IO,"TSCH");
822
823 FW_CHECK(effective_addr2, regs);
824
825 /* Program check if the ssid including lcss is invalid */
826 SSID_CHECK(regs);
827
828 /* Locate the device block for this subchannel */
829 dev = find_device_by_subchan (regs->GR_L(1));
830
831 /* Condition code 3 if subchannel does not exist,
832 is not valid, or is not enabled */
833 if (dev == NULL
834 || (dev->pmcw.flag5 & PMCW5_V) == 0
835 || (dev->pmcw.flag5 & PMCW5_E) == 0)
836 {
837 PTIO(ERR,"*TSCH");
838 #if defined(_FEATURE_IO_ASSIST)
839 SIE_INTERCEPT(regs);
840 #endif
841 regs->psw.cc = 3;
842 return;
843 }
844
845 /* validate operand before taking any action */
846 ARCH_DEP(validate_operand) (effective_addr2, b2, sizeof(IRB)-1,
847 ACCTYPE_WRITE_SKP, regs);
848
849 /* Perform serialization and checkpoint-synchronization */
850 PERFORM_SERIALIZATION (regs);
851 PERFORM_CHKPT_SYNC (regs);
852
853 /* Test and clear pending status, set condition code */
854 cc = test_subchan (regs, dev, &irb);
855
856 /* Store the interruption response block */
857 ARCH_DEP(vstorec) ( &irb, sizeof(IRB)-1, effective_addr2, b2, regs );
858
859 regs->psw.cc = cc;
860
861 }
862
863
864 #if defined(FEATURE_CANCEL_IO_FACILITY)
865 /*-------------------------------------------------------------------*/
866 /* B276 XSCH - Cancel Subchannel [S] */
867 /*-------------------------------------------------------------------*/
DEF_INST(cancel_subchannel)868 DEF_INST(cancel_subchannel)
869 {
870 int b2; /* Base of effective addr */
871 VADR effective_addr2; /* Effective address */
872 DEVBLK *dev; /* -> device block */
873
874 S(inst, regs, b2, effective_addr2);
875
876 PRIV_CHECK(regs);
877
878 #if defined(_FEATURE_IO_ASSIST)
879 if(SIE_STATNB(regs, EC0, IOA) && !regs->sie_pref)
880 #endif
881 SIE_INTERCEPT(regs);
882
883 PTIO(IO,"XSCH");
884
885 /* Program check if the ssid including lcss is invalid */
886 SSID_CHECK(regs);
887
888 /* Locate the device block for this subchannel */
889 dev = find_device_by_subchan (regs->GR_L(1));
890
891 /* Condition code 3 if subchannel does not exist,
892 is not valid, or is not enabled */
893 if (dev == NULL
894 || (dev->pmcw.flag5 & PMCW5_V) == 0
895 || (dev->pmcw.flag5 & PMCW5_E) == 0)
896 {
897 PTIO(ERR,"*XSCH");
898 #if defined(_FEATURE_IO_ASSIST)
899 SIE_INTERCEPT(regs);
900 #endif
901 regs->psw.cc = 3;
902 return;
903 }
904
905 /* Perform cancel subchannel and set condition code */
906 regs->psw.cc = cancel_subchan (regs, dev);
907
908 }
909 #endif /*defined(FEATURE_CANCEL_IO_FACILITY)*/
910 #endif /*defined(FEATURE_CHANNEL_SUBSYSTEM)*/
911
912
913 #if defined(FEATURE_S370_CHANNEL)
914
915 /*-------------------------------------------------------------------*/
916 /* 9C00 SIO - Start I/O [S] */
917 /* 9C01 SIOF - Start I/O Fast Release [S] */
918 /* 9C02 RIO - Resume I/O - ZZ INCOMPLETE [S] */
919 /*-------------------------------------------------------------------*/
DEF_INST(start_io)920 DEF_INST(start_io)
921 {
922 int b2; /* Effective addr base */
923 VADR effective_addr2; /* Effective address */
924 PSA *psa; /* -> prefixed storage area */
925 DEVBLK *dev; /* -> device block for SIO */
926 ORB orb; /* Operation request blk @IZW*/
927 VADR ccwaddr; /* CCW address for start I/O */
928 BYTE ccwkey; /* Bits 0-3=key, 4=7=zeroes */
929
930 S(inst, regs, b2, effective_addr2);
931
932 #if defined(FEATURE_ECPSVM)
933 if((inst[1])!=0x02)
934 {
935 if(ecpsvm_dosio(regs,b2,effective_addr2)==0)
936 {
937 return;
938 }
939 }
940 #endif
941
942 PRIV_CHECK(regs);
943
944 SIE_INTERCEPT(regs);
945
946 PTIO(IO,"SIO");
947
948 /* Locate the device block */
949 if(regs->chanset == 0xFFFF
950 || !(dev = find_device_by_devnum (regs->chanset,effective_addr2)) )
951 {
952 PTIO(ERR,"*SIO");
953 regs->psw.cc = 3;
954 return;
955 }
956
957 /* Fetch key and CCW address from the CAW at PSA+X'48' */
958 psa = (PSA*)(regs->mainstor + regs->PX);
959 ccwkey = psa->caw[0] & 0xF0;
960 ccwaddr = (psa->caw[1] << 16) | (psa->caw[2] << 8)
961 | psa->caw[3];
962
963 /* Build the I/O operation request block */ /*@IZW*/
964 memset (&orb, 0, sizeof(ORB)); /*@IZW*/
965 orb.flag4 = ccwkey & ORB4_KEY; /*@IZW*/
966 STORE_FW(orb.ccwaddr,ccwaddr); /*@IZW*/
967
968 /* Start the channel program and set the condition code */
969 regs->psw.cc = ARCH_DEP(startio) (regs, dev, &orb); /*@IZW*/
970
971 regs->siocount++;
972
973 }
974
975
976 /*-------------------------------------------------------------------*/
977 /* 9D00 TIO - Test I/O [S] */
978 /* 9D01 CLRIO - Clear I/O [S] */
979 /*-------------------------------------------------------------------*/
DEF_INST(test_io)980 DEF_INST(test_io)
981 {
982 int b2; /* Base of effective addr */
983 VADR effective_addr2; /* Effective address */
984 DEVBLK *dev; /* -> device block for SIO */
985
986 S(inst, regs, b2, effective_addr2);
987
988 PRIV_CHECK(regs);
989
990 SIE_INTERCEPT(regs);
991
992 PTIO(IO,"TIO");
993
994 /* Locate the device block */
995 if(regs->chanset == 0xFFFF
996 || !(dev = find_device_by_devnum (regs->chanset,effective_addr2)) )
997 {
998 PTIO(ERR,"*TIO");
999 regs->psw.cc = 3;
1000 return;
1001 }
1002
1003 /* Test the device and set the condition code */
1004 regs->psw.cc = testio (regs, dev, inst[1]);
1005 /* Yield time slice so that device handler may get some time */
1006 /* to possibly complete an I/O - to prevent a TIO Busy Loop */
1007 if(regs->psw.cc == 2)
1008 {
1009 sched_yield();
1010 }
1011
1012 }
1013
1014
1015 /*-------------------------------------------------------------------*/
1016 /* 9E00 HIO - Halt I/O [S] */
1017 /* 9E01 HDV - Halt Device [S] */
1018 /*-------------------------------------------------------------------*/
DEF_INST(halt_io)1019 DEF_INST(halt_io)
1020 {
1021 int b2; /* Base of effective addr */
1022 VADR effective_addr2; /* Effective address */
1023 DEVBLK *dev; /* -> device block for SIO */
1024
1025 S(inst, regs, b2, effective_addr2);
1026
1027 PRIV_CHECK(regs);
1028
1029 SIE_INTERCEPT(regs);
1030
1031 PTIO(IO,"HIO");
1032
1033 /* Locate the device block */
1034 if(regs->chanset == 0xFFFF
1035 || !(dev = find_device_by_devnum (regs->chanset,effective_addr2)) )
1036 {
1037 PTIO(ERR,"*HIO");
1038 regs->psw.cc = 3;
1039 return;
1040 }
1041
1042 /* Test the device and set the condition code */
1043 regs->psw.cc = haltio (regs, dev, inst[1]);
1044
1045 }
1046
1047
1048 /*-------------------------------------------------------------------*/
1049 /* 9F00 TCH - Test Channel [S] */
1050 /*-------------------------------------------------------------------*/
DEF_INST(test_channel)1051 DEF_INST(test_channel)
1052 {
1053 int b2; /* Base of effective addr */
1054 VADR effective_addr2; /* Effective address */
1055 #if defined(_FEATURE_SIE)
1056 BYTE channelid;
1057 U16 tch_ctl;
1058 #endif /*defined(_FEATURE_SIE)*/
1059
1060 S(inst, regs, b2, effective_addr2);
1061
1062 PRIV_CHECK(regs);
1063
1064 PTIO(IO,"TCH");
1065
1066 #if defined(_FEATURE_SIE)
1067 if(!SIE_MODE(regs))
1068 {
1069 #endif /*defined(_FEATURE_SIE)*/
1070 /* Test for pending interrupt and set condition code */
1071 regs->psw.cc = testch (regs, effective_addr2 & 0xFF00);
1072 #if defined(_FEATURE_SIE)
1073 }
1074 else
1075 {
1076 channelid = (effective_addr2 >> 8) & 0xFF;
1077 FETCH_HW(tch_ctl,((SIEBK*)(regs->siebk))->tch_ctl);
1078 if((channelid > 15)
1079 || ((0x8000 >> channelid) & tch_ctl))
1080 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1081 else
1082 regs->psw.cc = 0;
1083 }
1084 #endif /*defined(_FEATURE_SIE)*/
1085
1086 }
1087
1088
1089 /*-------------------------------------------------------------------*/
1090 /* B203 STIDC - Store Channel ID [S] */
1091 /*-------------------------------------------------------------------*/
DEF_INST(store_channel_id)1092 DEF_INST(store_channel_id)
1093 {
1094 int b2; /* Base of effective addr */
1095 VADR effective_addr2; /* Effective address */
1096
1097 S(inst, regs, b2, effective_addr2);
1098
1099 PRIV_CHECK(regs);
1100
1101 SIE_INTERCEPT(regs);
1102
1103 PTIO(IO,"STIDC");
1104
1105 /* Store Channel ID and set condition code */
1106 regs->psw.cc =
1107 stchan_id (regs, effective_addr2 & 0xFF00);
1108
1109 }
1110
1111
1112 #if defined(FEATURE_CHANNEL_SWITCHING)
1113 /*-------------------------------------------------------------------*/
1114 /* B200 CONCS - Connect Channel Set [S] */
1115 /*-------------------------------------------------------------------*/
DEF_INST(connect_channel_set)1116 DEF_INST(connect_channel_set)
1117 {
1118 int b2; /* Base of effective addr */
1119 VADR effective_addr2; /* Effective address */
1120 int i;
1121
1122 S(inst, regs, b2, effective_addr2);
1123
1124 PRIV_CHECK(regs);
1125
1126 SIE_INTERCEPT(regs);
1127
1128 PTIO(IO,"CONCS");
1129
1130 effective_addr2 &= 0xFFFF;
1131
1132 /* Hercules has as many channelsets as CSS's */
1133 if(effective_addr2 >= FEATURE_LCSS_MAX)
1134 {
1135 PTIO(ERR,"*CONCS");
1136 regs->psw.cc = 3;
1137 return;
1138 }
1139
1140 /* If the addressed channel set is currently connected
1141 then return with cc0 */
1142 if(regs->chanset == effective_addr2)
1143 {
1144 regs->psw.cc = 0;
1145 return;
1146 }
1147
1148 /* Disconnect channel set */
1149 regs->chanset = 0xFFFF;
1150
1151 OBTAIN_INTLOCK(regs);
1152
1153 /* If the addressed channelset is connected to another
1154 CPU then return with cc1 */
1155 for (i = 0; i < MAX_CPU; i++)
1156 {
1157 if (IS_CPU_ONLINE(i)
1158 && sysblk.regs[i]->chanset == effective_addr2)
1159 {
1160 RELEASE_INTLOCK(regs);
1161 regs->psw.cc = 1;
1162 return;
1163 }
1164 }
1165
1166 /* Set channel set connected to current CPU */
1167 regs->chanset = effective_addr2;
1168
1169 /* Interrupts may be pending on this channelset */
1170 ON_IC_IOPENDING;
1171
1172 RELEASE_INTLOCK(regs);
1173
1174 regs->psw.cc = 0;
1175
1176 }
1177
1178
1179 /*-------------------------------------------------------------------*/
1180 /* B201 DISCS - Disconnect Channel Set [S] */
1181 /*-------------------------------------------------------------------*/
DEF_INST(disconnect_channel_set)1182 DEF_INST(disconnect_channel_set)
1183 {
1184 int b2; /* Base of effective addr */
1185 VADR effective_addr2; /* Effective address */
1186 int i;
1187
1188 S(inst, regs, b2, effective_addr2);
1189
1190 PRIV_CHECK(regs);
1191
1192 SIE_INTERCEPT(regs);
1193
1194 PTIO(IO,"DISCS");
1195
1196 /* Hercules has as many channelsets as CSS's */
1197 if(effective_addr2 >= FEATURE_LCSS_MAX)
1198 {
1199 PTIO(ERR,"*DISCS");
1200 regs->psw.cc = 3;
1201 return;
1202 }
1203
1204 /* If the addressed channel set is currently connected
1205 then disconect channel set and return with cc0 */
1206 if(regs->chanset == effective_addr2 && regs->chanset != 0xFFFF)
1207 {
1208 regs->chanset = 0xFFFF;
1209 regs->psw.cc = 0;
1210 return;
1211 }
1212
1213 OBTAIN_INTLOCK(regs);
1214
1215 /* If the addressed channelset is connected to another
1216 CPU then return with cc0 */
1217 for(i = 0; i < MAX_CPU; i++)
1218 {
1219 if (IS_CPU_ONLINE(i)
1220 && sysblk.regs[i]->chanset == effective_addr2)
1221 {
1222 if(sysblk.regs[i]->cpustate != CPUSTATE_STARTED)
1223 {
1224 sysblk.regs[i]->chanset = 0xFFFF;
1225 regs->psw.cc = 0;
1226 }
1227 else
1228 regs->psw.cc = 1;
1229 RELEASE_INTLOCK(regs);
1230 return;
1231 }
1232 }
1233
1234 RELEASE_INTLOCK(regs);
1235
1236 /* The channel set is not connected, no operation
1237 is performed */
1238 regs->psw.cc = 0;
1239
1240 }
1241 #endif /*defined(FEATURE_CHANNEL_SWITCHING)*/
1242
1243 #endif /*defined(FEATURE_S370_CHANNEL)*/
1244
1245
1246 #if !defined(_GEN_ARCH)
1247
1248 #if defined(_ARCHMODE2)
1249 #define _GEN_ARCH _ARCHMODE2
1250 #include "io.c"
1251 #endif
1252
1253 #if defined(_ARCHMODE3)
1254 #undef _GEN_ARCH
1255 #define _GEN_ARCH _ARCHMODE3
1256 #include "io.c"
1257 #endif
1258
1259 #endif /*!defined(_GEN_ARCH)*/
1260