1 /* IPL.C (c) Copyright Roger Bowler, 1999-2009 */
2 /* ESA/390 Initial Program Loader */
3
4 /* Interpretive Execution - (c) Copyright Jan Jaeger, 1999-2009 */
5 /* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2009 */
6
7 /*-------------------------------------------------------------------*/
8 /* This module implements the Initial Program Load (IPL) function of */
9 /* the S/370, ESA/390 and z/Architectures, described in the manuals: */
10 /* */
11 /* GA22-7000 System/370 Principles of Operation */
12 /* SA22-7201 ESA/390 Principles of Operation */
13 /* SA22-7832 z/Architecture Principles of Operation. */
14 /* */
15 /*-------------------------------------------------------------------*/
16
17 #include "hstdinc.h"
18
19 #define _IPL_C
20 #define _HENGINE_DLL_
21
22 #include "hercules.h"
23 #include "opcode.h"
24 #include "inline.h"
25 #if defined(OPTION_FISHIO)
26 #include "w32chan.h"
27 #endif // defined(OPTION_FISHIO)
28 #if defined(_FEATURE_MESSAGE_SECURITY_ASSIST)
29 #include "hexterns.h"
30 #endif
31
32 /*-------------------------------------------------------------------*/
33 /* Function to perform System Reset (either 'normal' or 'clear') */
34 /*-------------------------------------------------------------------*/
ARCH_DEP(system_reset)35 int ARCH_DEP(system_reset) (int cpu, int clear)
36 {
37 int rc = 0;
38 REGS *regs;
39
40 /* Configure the cpu if it is not online */
41 if (!IS_CPU_ONLINE(cpu))
42 {
43 if (configure_cpu(cpu) != 0)
44 {
45 /* ZZ FIXME: we should probably present a machine-check
46 if we encounter any errors during the reset (rc != 0) */
47 return -1;
48 }
49 ASSERT(IS_CPU_ONLINE(cpu));
50 }
51 regs = sysblk.regs[cpu];
52
53 HDC1(debug_cpu_state, regs);
54
55 /* Perform system-reset-normal or system-reset-clear function */
56 if (!clear)
57 {
58 /* Reset external interrupts */
59 OFF_IC_SERVSIG;
60 OFF_IC_INTKEY;
61
62 /* Reset all CPUs in the configuration */
63 for (cpu = 0; cpu < MAX_CPU; cpu++)
64 if (IS_CPU_ONLINE(cpu))
65 if (ARCH_DEP(cpu_reset) (sysblk.regs[cpu]))
66 rc = -1;
67
68 /* Perform I/O subsystem reset */
69 io_reset ();
70 }
71 else
72 {
73 /* Reset external interrupts */
74 OFF_IC_SERVSIG;
75 OFF_IC_INTKEY;
76
77 /* Reset all CPUs in the configuration */
78 for (cpu = 0; cpu < MAX_CPU; cpu++)
79 {
80 if (IS_CPU_ONLINE(cpu))
81 {
82 regs=sysblk.regs[cpu];
83 if (ARCH_DEP(initial_cpu_reset) (regs))
84 {
85 rc = -1;
86 }
87 /* Clear all the registers (AR, GPR, FPR, VR)
88 as part of the CPU CLEAR RESET operation */
89 memset (regs->ar,0,sizeof(regs->ar));
90 memset (regs->gr,0,sizeof(regs->gr));
91 memset (regs->fpr,0,sizeof(regs->fpr));
92 #if defined(_FEATURE_VECTOR_FACILITY)
93 memset (regs->vf->vr,0,sizeof(regs->vf->vr));
94 #endif /*defined(_FEATURE_VECTOR_FACILITY)*/
95 }
96 }
97
98 /* Perform I/O subsystem reset */
99 io_reset ();
100
101 #if defined(FEATURE_LOAD_PROGRAM_PARAMETER_FACILITY)
102 /* Clear the program-parameter register */
103 sysblk.program_parameter = 0;
104 #endif /*defined(FEATURE_LOAD_PROGRAM_PARAMETER_FACILITY)*/
105
106 /* Clear storage */
107 sysblk.main_clear = sysblk.xpnd_clear = 0;
108 storage_clear();
109 xstorage_clear();
110
111 }
112
113 #if defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)
114 /* Set horizontal polarization */
115 sysblk.topology = TOPOLOGY_HORIZ;
116
117 /* Clear topology-change-report-pending condition */
118 sysblk.topchnge = 0;
119 #endif /*defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)*/
120
121 /* ZZ FIXME: we should probably present a machine-check
122 if we encounter any errors during the reset (rc != 0) */
123 return rc;
124 } /* end function system_reset */
125
126 /*-------------------------------------------------------------------*/
127 /* LOAD (aka IPL) functions... */
128 /*-------------------------------------------------------------------*/
129 /* Performing an Initial Program Load (aka IPL) involves three */
130 /* distinct phases: in phase 1 the system is reset (registers */
131 /* and, for load-clear, storage), and in phase two the actual */
132 /* Initial Program Loading from the IPL device takes place. Finally,*/
133 /* in phase three, the IPL PSW is loaded and the CPU is started. */
134 /*-------------------------------------------------------------------*/
135
136 int orig_arch_mode; /* Saved architecture mode */
137 PSW captured_zpsw; /* Captured z/Arch PSW */
138
139 /*-------------------------------------------------------------------*/
140 /* Common LOAD (IPL) begin: system-reset (register/storage clearing) */
141 /*-------------------------------------------------------------------*/
ARCH_DEP(common_load_begin)142 int ARCH_DEP(common_load_begin) (int cpu, int clear)
143 {
144 REGS *regs;
145
146 /* Save the original architecture mode for later */
147 orig_arch_mode = sysblk.dummyregs.arch_mode = sysblk.arch_mode;
148 #if defined(OPTION_FISHIO)
149 ios_arch_mode = sysblk.arch_mode;
150 #endif // defined(OPTION_FISHIO)
151
152 /* Perform system-reset-normal or system-reset-clear function */
153 if (ARCH_DEP(system_reset(cpu,clear)) != 0)
154 return -1;
155 regs = sysblk.regs[cpu];
156
157 if (sysblk.arch_mode == ARCH_900)
158 {
159 /* Switch architecture mode to ESA390 mode for z/Arch IPL */
160 sysblk.arch_mode = ARCH_390;
161 /* Capture the z/Arch PSW if this is a Load-normal IPL */
162 if (!clear)
163 captured_zpsw = regs->psw;
164 }
165
166 /* Load-clear does a clear-reset (which does an initial-cpu-reset)
167 on all cpus in the configuration, but Load-normal does an initial-
168 cpu-reset only for the IPL CPU and a regular cpu-reset for all
169 other CPUs in the configuration. Thus if the above system_reset
170 call did a system-normal-reset for us, then we need to manually
171 do a clear-reset (initial-cpu-reset) on the IPL CPU...
172 */
173 if (!clear)
174 {
175 /* Perform initial reset on the IPL CPU */
176 if (ARCH_DEP(initial_cpu_reset) (regs) != 0)
177 return -1;
178 /* Save our captured-z/Arch-PSW if this is a Load-normal IPL
179 since the initial_cpu_reset call cleared it to zero. */
180 if (orig_arch_mode == ARCH_900)
181 regs->captured_zpsw = captured_zpsw;
182 }
183
184 /* The actual IPL (load) now begins... */
185 regs->loadstate = 1;
186
187 return 0;
188 } /* end function common_load_begin */
189
190 /*-------------------------------------------------------------------*/
191 /* Function to run initial CCW chain from IPL device and load IPLPSW */
192 /* Returns 0 if successful, -1 if error */
193 /* intlock MUST be held on entry */
194 /*-------------------------------------------------------------------*/
ARCH_DEP(load_ipl)195 int ARCH_DEP(load_ipl) (U16 lcss, U16 devnum, int cpu, int clear)
196 {
197 REGS *regs; /* -> Regs */
198 DEVBLK *dev; /* -> Device control block */
199 int i; /* Array subscript */
200 BYTE unitstat; /* IPL device unit status */
201 BYTE chanstat; /* IPL device channel status */
202
203 /* Get started */
204 if (ARCH_DEP(common_load_begin) (cpu, clear) != 0)
205 return -1;
206
207 /* The actual IPL proper starts here... */
208
209 regs = sysblk.regs[cpu]; /* Point to IPL CPU's registers */
210
211 /* Point to the device block for the IPL device */
212 dev = find_device_by_devnum (lcss,devnum);
213 if (dev == NULL)
214 {
215 logmsg (_("HHCCP027E Device %4.4X not in configuration%s\n"),
216 devnum,
217 (sysblk.arch_mode == ARCH_370 ?
218 " or not connected to channelset" : ""));
219 HDC1(debug_cpu_state, regs);
220 return -1;
221 }
222 #if defined(OPTION_IPLPARM)
223 if(sysblk.haveiplparm)
224 {
225 for(i=0;i<16;i++)
226 {
227 regs->GR_L(i)=fetch_fw(&sysblk.iplparmstring[i*4]);
228 }
229 sysblk.haveiplparm=0;
230 }
231 #endif
232
233 /* Set Main Storage Reference and Update bits */
234 STORAGE_KEY(regs->PX, regs) |= (STORKEY_REF | STORKEY_CHANGE);
235 sysblk.main_clear = sysblk.xpnd_clear = 0;
236
237 /* Build the IPL CCW at location 0 */
238 regs->psa->iplpsw[0] = 0x02; /* CCW command = Read */
239 regs->psa->iplpsw[1] = 0; /* Data address = zero */
240 regs->psa->iplpsw[2] = 0;
241 regs->psa->iplpsw[3] = 0;
242 regs->psa->iplpsw[4] = CCW_FLAGS_CC | CCW_FLAGS_SLI;
243 /* CCW flags */
244 regs->psa->iplpsw[5] = 0; /* Reserved byte */
245 regs->psa->iplpsw[6] = 0; /* Byte count = 24 */
246 regs->psa->iplpsw[7] = 24;
247
248 /* Enable the subchannel for the IPL device */
249 dev->pmcw.flag5 |= PMCW5_E;
250
251 /* Build the operation request block */ /*@IWZ*/
252 memset (&dev->orb, 0, sizeof(ORB)); /*@IWZ*/
253 dev->busy = 1;
254
255 RELEASE_INTLOCK(NULL);
256
257 /* Execute the IPL channel program */
258 ARCH_DEP(execute_ccw_chain) (dev);
259
260 OBTAIN_INTLOCK(NULL);
261
262 /* Clear the interrupt pending and device busy conditions */
263 obtain_lock (&sysblk.iointqlk);
264 DEQUEUE_IO_INTERRUPT_QLOCKED(&dev->ioint);
265 DEQUEUE_IO_INTERRUPT_QLOCKED(&dev->pciioint);
266 DEQUEUE_IO_INTERRUPT_QLOCKED(&dev->attnioint);
267 release_lock(&sysblk.iointqlk);
268 dev->busy = 0;
269 dev->scsw.flag2 = 0;
270 dev->scsw.flag3 = 0;
271
272 /* Check that load completed normally */
273 #ifdef FEATURE_S370_CHANNEL
274 unitstat = dev->csw[4];
275 chanstat = dev->csw[5];
276 #endif /*FEATURE_S370_CHANNEL*/
277
278 #ifdef FEATURE_CHANNEL_SUBSYSTEM
279 unitstat = dev->scsw.unitstat;
280 chanstat = dev->scsw.chanstat;
281 #endif /*FEATURE_CHANNEL_SUBSYSTEM*/
282
283 if (unitstat != (CSW_CE | CSW_DE) || chanstat != 0) {
284 logmsg (_("HHCCP029E %s mode IPL failed: CSW status=%2.2X%2.2X\n"
285 " Sense="),
286 get_arch_mode_string(regs), unitstat, chanstat);
287 for (i=0; i < (int)dev->numsense; i++)
288 {
289 logmsg ("%2.2X", dev->sense[i]);
290 if ((i & 3) == 3) logmsg(" ");
291 }
292 logmsg ("\n");
293 HDC1(debug_cpu_state, regs);
294 return -1;
295 }
296
297 #ifdef FEATURE_S370_CHANNEL
298 /* Test the EC mode bit in the IPL PSW */
299 if (regs->psa->iplpsw[1] & 0x08) {
300 /* In EC mode, store device address at locations 184-187 */
301 STORE_FW(regs->psa->ioid, dev->devnum);
302 } else {
303 /* In BC mode, store device address at locations 2-3 */
304 STORE_HW(regs->psa->iplpsw + 2, dev->devnum);
305 }
306 #endif /*FEATURE_S370_CHANNEL*/
307
308 #ifdef FEATURE_CHANNEL_SUBSYSTEM
309 /* Set LPUM */
310 dev->pmcw.lpum = 0x80;
311 STORE_FW(regs->psa->ioid, (dev->ssid<<16)|dev->subchan);
312
313 /* Store zeroes at locations 188-191 */
314 memset (regs->psa->ioparm, 0, 4);
315 #endif /*FEATURE_CHANNEL_SUBSYSTEM*/
316
317 /* Save IPL device number, cpu number and lcss */
318 sysblk.ipldev = devnum;
319 sysblk.iplcpu = regs->cpuad;
320 sysblk.ipllcss = lcss;
321
322 /* Finish up... */
323 return ARCH_DEP(common_load_finish) (regs);
324 } /* end function load_ipl */
325
326 /*-------------------------------------------------------------------*/
327 /* Common LOAD (IPL) finish: load IPL PSW and start CPU */
328 /*-------------------------------------------------------------------*/
ARCH_DEP(common_load_finish)329 int ARCH_DEP(common_load_finish) (REGS *regs)
330 {
331 /* Zeroize the interrupt code in the PSW */
332 regs->psw.intcode = 0;
333
334 /* Load IPL PSW from PSA+X'0' */
335 if (ARCH_DEP(load_psw) (regs, regs->psa->iplpsw) != 0)
336 {
337 logmsg (_("HHCCP030E %s mode IPL failed: Invalid IPL PSW: "
338 "%2.2X%2.2X%2.2X%2.2X %2.2X%2.2X%2.2X%2.2X\n"),
339 get_arch_mode_string(regs),
340 regs->psa->iplpsw[0], regs->psa->iplpsw[1],
341 regs->psa->iplpsw[2], regs->psa->iplpsw[3],
342 regs->psa->iplpsw[4], regs->psa->iplpsw[5],
343 regs->psa->iplpsw[6], regs->psa->iplpsw[7]);
344 HDC1(debug_cpu_state, regs);
345 return -1;
346 }
347
348 /* Set the CPU into the started state */
349 regs->opinterv = 0;
350 regs->cpustate = CPUSTATE_STARTED;
351
352 /* The actual IPL (load) is now completed... */
353 regs->loadstate = 0;
354
355 /* Signal the CPU to retest stopped indicator */
356 WAKEUP_CPU (regs);
357
358 HDC1(debug_cpu_state, regs);
359 return 0;
360 } /* end function common_load_finish */
361
362 /*-------------------------------------------------------------------*/
363 /* Function to perform CPU Reset */
364 /*-------------------------------------------------------------------*/
ARCH_DEP(cpu_reset)365 int ARCH_DEP(cpu_reset) (REGS *regs)
366 {
367 int i; /* Array subscript */
368
369 regs->ip = regs->inst;
370
371 /* Clear indicators */
372 regs->loadstate = 0;
373 regs->checkstop = 0;
374 regs->sigpreset = 0;
375 regs->extccpu = 0;
376 for (i = 0; i < MAX_CPU; i++)
377 regs->emercpu[i] = 0;
378 regs->instinvalid = 1;
379 regs->instcount = regs->prevcount = 0;
380
381 /* Clear interrupts */
382 SET_IC_INITIAL_MASK(regs);
383 SET_IC_INITIAL_STATE(regs);
384
385 /* Clear the translation exception identification */
386 regs->EA_G = 0;
387 regs->excarid = 0;
388
389 /* Clear monitor code */
390 regs->MC_G = 0;
391
392 /* Purge the lookaside buffers */
393 ARCH_DEP(purge_tlb) (regs);
394
395 #if defined(FEATURE_ACCESS_REGISTERS)
396 ARCH_DEP(purge_alb) (regs);
397 #endif /*defined(FEATURE_ACCESS_REGISTERS)*/
398
399 if(regs->host)
400 {
401 /* Put the CPU into the stopped state */
402 regs->opinterv = 0;
403 regs->cpustate = CPUSTATE_STOPPED;
404 ON_IC_INTERRUPT(regs);
405 }
406
407 #ifdef FEATURE_INTERVAL_TIMER
408 ARCH_DEP(store_int_timer_nolock) (regs);
409 #endif
410
411 if(regs->host && regs->guestregs)
412 {
413 ARCH_DEP(cpu_reset)(regs->guestregs);
414 /* CPU state of SIE copy cannot be controlled */
415 regs->guestregs->opinterv = 0;
416 regs->guestregs->cpustate = CPUSTATE_STARTED;
417 }
418
419 return 0;
420 } /* end function cpu_reset */
421
422 /*-------------------------------------------------------------------*/
423 /* Function to perform Initial CPU Reset */
424 /*-------------------------------------------------------------------*/
ARCH_DEP(initial_cpu_reset)425 int ARCH_DEP(initial_cpu_reset) (REGS *regs)
426 {
427 /* Clear reset pending indicators */
428 regs->sigpireset = regs->sigpreset = 0;
429
430
431 /* Clear the registers */
432 memset ( ®s->psw, 0, sizeof(regs->psw) );
433 memset ( ®s->captured_zpsw, 0, sizeof(regs->captured_zpsw) );
434 memset ( regs->cr, 0, sizeof(regs->cr) );
435 regs->fpc = 0;
436 regs->PX = 0;
437 regs->psw.AMASK_G = AMASK24;
438
439 /*
440 * ISW20060125 : Since we reset the prefix, we must also adjust
441 * the PSA ptr
442 */
443 regs->psa = (PSA_3XX *)regs->mainstor;
444
445 /* Perform a CPU reset (after setting PSA) */
446 ARCH_DEP(cpu_reset) (regs);
447
448 regs->todpr = 0;
449 regs->clkc = 0;
450 set_cpu_timer(regs, 0);
451 #ifdef _FEATURE_INTERVAL_TIMER
452 set_int_timer(regs, 0);
453 #endif
454
455 /* The breaking event address register is initialised to 1 */
456 regs->bear = 1;
457
458 /* Initialize external interrupt masks in control register 0 */
459 regs->CR(0) = CR0_XM_ITIMER | CR0_XM_INTKEY | CR0_XM_EXTSIG;
460
461 #ifdef FEATURE_S370_CHANNEL
462 /* For S/370 initialize the channel masks in CR2 */
463 regs->CR(2) = 0xFFFFFFFF;
464 #endif /*FEATURE_S370_CHANNEL*/
465
466 regs->chanset =
467 #if defined(FEATURE_CHANNEL_SWITCHING)
468 regs->cpuad < FEATURE_LCSS_MAX ? regs->cpuad :
469 #endif /*defined(FEATURE_CHANNEL_SWITCHING)*/
470 0xFFFF;
471
472 /* Initialize the machine check masks in control register 14 */
473 regs->CR(14) = CR14_CHKSTOP | CR14_SYNCMCEL | CR14_XDMGRPT;
474
475 #ifndef FEATURE_LINKAGE_STACK
476 /* For S/370 initialize the MCEL address in CR15 */
477 regs->CR(15) = 512;
478 #endif /*!FEATURE_LINKAGE_STACK*/
479
480 if(regs->host && regs->guestregs)
481 ARCH_DEP(initial_cpu_reset)(regs->guestregs);
482
483 #if defined(_FEATURE_MESSAGE_SECURITY_ASSIST)
484 renew_wrapping_keys();
485 #endif /*defined(_FEATURE_MESSAGE_SECURITY_ASSIST)*/
486
487 return 0;
488 } /* end function initial_cpu_reset */
489
490 #if !defined(_GEN_ARCH)
491
492 #if defined(_ARCHMODE2)
493 #define _GEN_ARCH _ARCHMODE2
494 #include "ipl.c"
495 #endif
496
497 #if defined(_ARCHMODE3)
498 #undef _GEN_ARCH
499 #define _GEN_ARCH _ARCHMODE3
500 #include "ipl.c"
501 #endif
502
503 /*********************************************************************/
504 /* Externally Initiated Functions... */
505 /*********************************************************************/
506
507 /*-------------------------------------------------------------------*/
508 /* Load / IPL (Load Normal -or- Load Clear) */
509 /*-------------------------------------------------------------------*/
510
load_ipl(U16 lcss,U16 devnum,int cpu,int clear)511 int load_ipl (U16 lcss, U16 devnum, int cpu, int clear)
512 {
513 switch(sysblk.arch_mode) {
514 #if defined(_370)
515 case ARCH_370:
516 return s370_load_ipl (lcss, devnum, cpu, clear);
517 #endif
518 #if defined(_390)
519 case ARCH_390:
520 return s390_load_ipl (lcss, devnum, cpu, clear);
521 #endif
522 #if defined(_900)
523 case ARCH_900:
524 /* z/Arch always starts out in ESA390 mode */
525 return s390_load_ipl (lcss, devnum, cpu, clear);
526 #endif
527 }
528 return -1;
529 }
530
531 /*-------------------------------------------------------------------*/
532 /* Initial CPU Reset */
533 /*-------------------------------------------------------------------*/
initial_cpu_reset(REGS * regs)534 int initial_cpu_reset (REGS *regs)
535 {
536 int rc = -1;
537 switch(sysblk.arch_mode) {
538 #if defined(_370)
539 case ARCH_370:
540 rc = s370_initial_cpu_reset (regs);
541 break;
542 #endif
543 #if defined(_390)
544 case ARCH_390:
545 rc = s390_initial_cpu_reset (regs);
546 break;
547 #endif
548 #if defined(_900)
549 case ARCH_900:
550 /* z/Arch always starts out in ESA390 mode */
551 rc = s390_initial_cpu_reset (regs);
552 break;
553 #endif
554 }
555 regs->arch_mode = sysblk.arch_mode;
556 return rc;
557 }
558
559 /*-------------------------------------------------------------------*/
560 /* System Reset ( Normal reset or Clear reset ) */
561 /*-------------------------------------------------------------------*/
system_reset(int cpu,int clear)562 int system_reset (int cpu, int clear)
563 {
564 switch(sysblk.arch_mode) {
565 #if defined(_370)
566 case ARCH_370:
567 return s370_system_reset (cpu, clear);
568 #endif
569 #if defined(_390)
570 case ARCH_390:
571 return s390_system_reset (cpu, clear);
572 #endif
573 #if defined(_900)
574 case ARCH_900:
575 /* z/Arch always starts out in ESA390 mode */
576 return s390_system_reset (cpu, clear);
577 #endif
578 }
579 return -1;
580 }
581
582 /*-------------------------------------------------------------------*/
583 /* ordinary CPU Reset (no clearing takes place) */
584 /*-------------------------------------------------------------------*/
cpu_reset(REGS * regs)585 int cpu_reset (REGS *regs)
586 {
587 switch(sysblk.arch_mode) {
588 #if defined(_370)
589 case ARCH_370:
590 return s370_cpu_reset (regs);
591 #endif
592 #if defined(_390)
593 case ARCH_390:
594 return s390_cpu_reset (regs);
595 #endif
596 #if defined(_900)
597 case ARCH_900:
598 /* z/Arch always starts out in ESA390 mode */
599 return s390_cpu_reset (regs);
600 #endif
601 }
602 return -1;
603 }
604
605 /*-------------------------------------------------------------------*/
606 /* Function to clear main storage */
607 /*-------------------------------------------------------------------*/
storage_clear()608 void storage_clear()
609 {
610 if (!sysblk.main_clear)
611 {
612 memset(sysblk.mainstor,0,sysblk.mainsize);
613 memset(sysblk.storkeys,0,sysblk.mainsize / STORAGE_KEY_UNITSIZE);
614 sysblk.main_clear = 1;
615 }
616 }
617
618 /*-------------------------------------------------------------------*/
619 /* Function to clear expanded storage */
620 /*-------------------------------------------------------------------*/
xstorage_clear()621 void xstorage_clear()
622 {
623 if(sysblk.xpndsize && !sysblk.xpnd_clear)
624 {
625 memset(sysblk.xpndstor,0,(size_t)sysblk.xpndsize * XSTORE_PAGESIZE);
626 sysblk.xpnd_clear = 1;
627 }
628 }
629
630 #endif /*!defined(_GEN_ARCH)*/
631