1 /* the ordering of these includes is important - stdio can have inline
2 functions - so can mem68k.h - and registers.h must appear before them */
3
4 #include "generator.h"
5 #include "registers.h"
6
7 #include <stdio.h>
8
9 #include "cpu68k.h"
10 #include "reg68k.h"
11
12
13 #define DATAREG(a) (reg68k_regs[a])
14 #define ADDRREG(a) (reg68k_regs[8+(a)])
15 #define PC (reg68k_pc)
16 #define SR (reg68k_sr.sr_int)
17 #define SP (regs.sp)
18 #define STOP (regs.stop)
19 #define TFLAG (reg68k_sr.sr_struct.t)
20 #define SFLAG (reg68k_sr.sr_struct.s)
21 #define XFLAG (reg68k_sr.sr_struct.x)
22 #define NFLAG (reg68k_sr.sr_struct.n)
23 #define ZFLAG (reg68k_sr.sr_struct.z)
24 #define VFLAG (reg68k_sr.sr_struct.v)
25 #define CFLAG (reg68k_sr.sr_struct.c)
26 #define IMASK ((SR>>8) & 7)
27
28
idxval_dst(t_ipc * ipc)29 static __inline__ sint32 idxval_dst(t_ipc *ipc) {
30 sint32 r;
31
32 //switch( ((ipc->dst>>27) & 1) | ((ipc->dst>>30) & 2) ) {
33 // 23,24,25,26,27,28,29,30,31
34 // -1, 0, 1, 2, 3, 4, 5, 6, 7
35 switch( ((ipc->reg>>3) & 1) | ((ipc->reg>>6) & 2) )
36 {
37 case 0: // data, word
38 //return ((sint16)DATAREG((ipc->dst>>28)&7)) + ((((sint32)(ipc->dst<<8)))>>8);
39 r=((sint16)DATAREG((ipc->reg>>4)&7)) + ((sint32)(ipc->dst)) ;
40 DEBUG_LOG(10,"r=%08x %ld =datareg(%d)=%08x + %08x",r,r,
41 (ipc->reg&7),
42 ((sint16)DATAREG(ipc->reg&7)),
43 ((sint32)(ipc->dst))
44 );
45 return r;
46
47 case 1: // data, long
48 r=((sint32)DATAREG((ipc->reg>>4)&7)) + ((sint32)(ipc->dst));
49 DEBUG_LOG(10,"r=%08x %ld = = datareg(%d) %08x + %08x",r,r,
50 (ipc->reg&7),
51 (sint32)DATAREG(ipc->reg&7),
52 ((sint32)(ipc->dst))
53 );
54 return r;
55
56 case 2: // addr, word ** this seems very strange *** ****BUGHERE?????**********
57 //return ((sint16)ADDRREG((ipc->dst>>28)&7)) + ((((sint32)(ipc->dst<<8)))>>8);
58 //** This doesn't work because the above is dst>>28. >>28 is equivalent to >>4
59 r=((sint16)ADDRREG((ipc->reg>>4)&7)) + ((sint32)(ipc->dst));
60 ALERT_LOG(0,"SUSPECT r=%08x %ld = addrreg(%d).w %04x + %08x DANGER HERE DANGER HERE DANGER HERE!!!",r,r,
61 (ipc->reg&7),
62 (sint16)ADDRREG(ipc->reg&7),
63 ((sint32)(ipc->dst))
64 );
65 return r;
66
67 case 3: // addr, long
68 r=((sint32)ADDRREG((ipc->reg>>4)&7) + ((sint32)(ipc->dst)) );
69 DEBUG_LOG(10,"r=%08x %ld = addrreg(%d) %08x + %08x",r,r,
70 (ipc->reg&7),
71 (sint32)ADDRREG(ipc->reg&7),
72 ((sint32)(ipc->dst))
73 );
74 return r;
75 }
76 return 0;
77 }
78
79
idxval_src(t_ipc * ipc)80 static __inline__ sint32 idxval_src(t_ipc *ipc) {
81 sint32 r;
82 // switch( ((ipc->src>>27) & 1) | ((ipc->src>>30) & 2) ) { // ra uncommented 20070704
83 // 24,25,26,27,28,29,30,31
84 // 0 1 2 3 4 5 6 7
85 switch( ((ipc->reg>>3) & 1) | ((ipc->reg>>6) & 2) )
86 {
87 case 0: // data, word
88 //20060130-RA// r=((sint16)DATAREG((ipc->src>>28)&7)) + ((((sint32)(ipc->src<<8)))>>8);
89 //20060203-RA// r=((sint16)DATAREG((ipc->src>>28)&7)) + ((sint32)(ipc->src));
90
91 r=((sint16)DATAREG((ipc->reg>>4)&7) + ((sint32)(ipc->src)) );
92 DEBUG_LOG(10,"idxval_src=%08x (%ld) = %04x+%08x",r,r,
93 ((sint16)DATAREG(ipc->reg&7) , ((sint32)(ipc->src)) ));
94
95 return r;
96 case 1: // data, long
97 //20060130-RA// r=((sint32)DATAREG((ipc->src>>28)&7)) + ((((sint32)(ipc->src<<8)))>>8);
98 //20060203-RA// r=((sint32)DATAREG((ipc->src>>28)&7)) + ((sint32)(ipc->src) );
99
100 r=((sint32)DATAREG((ipc->reg>>4)&7) + ((sint32)(ipc->src) ));
101 DEBUG_LOG(10,"idxval_src=%08x (%ld) = %08x+%08x",r,r,
102 ((sint32)DATAREG(ipc->reg&7)) , ((sint32)(ipc->src) ) );
103 return r;
104
105 case 2: // addr, word
106 //20060130-RA// r=((sint16)ADDRREG((ipc->src>>28)&7)) + ((((sint32)(ipc->src<<8)))>>8);
107 //20060203-RA// r=((sint16)ADDRREG((ipc->src>>28)&7)) + ((sint32)(ipc->src) );
108
109 r=((sint16)ADDRREG((ipc->reg>>4)&7)) + ((sint32)(ipc->src)) ;
110 DEBUG_LOG(10,"idxval_src=%08x (%ld) = %04x+%08x",r,r,
111 ((sint16)ADDRREG(ipc->reg&7)) , ((sint32)(ipc->src) ) );
112 return r;
113 case 3: // addr, long
114 //20060130-RA// r=((sint32)ADDRREG((ipc->src>>28)&7)) + ((((sint32)(ipc->src<<8)))>>8);
115 //20060203-RA// r=((sint32)ADDRREG((ipc->src>>28)&7)) + ((sint32)(ipc->src) );
116
117 r=((sint32)ADDRREG((ipc->reg>>4)&7) + ((sint32)(ipc->src)) );
118 DEBUG_LOG(10,"idxval_src=%08x (%ld) = %08x+%08x",r,r,
119 ((sint32)ADDRREG(ipc->reg&7)) , ((sint32)(ipc->src) ) );
120 return r;
121 }
122 return 0;
123 }
124
125
126
127 // Added by RA
128 #define SWAP_USP_SSP() {ADDRREG(7)^= SP; SP^= ADDRREG(7); ADDRREG(7)^= SP; DEBUG_LOG(5,"S mode change SP:%08x/A7:%08x swapped.",ADDRREG(7),SP);}
129 #define SYNC_PC_SR() {regs.pc = reg68k_pc; regs.sr = reg68k_sr;}
130
131
132 // Added by Ray Arachelian for Lisa Emulator to handle address errors and such without completion of the operation.
133 extern int abort_opcode;
134 #define ABORT_OPCODE_CHK() { if (abort_opcode==1) return; }
135
136 // Added by Ray Arachelian for Lisa Emulator: on S flag change, mmu may change context, etc.
137 // this does the following: 1. swap USP with SSP, 2. synchronize PC and SR to setjmp land, 3. does an MMU flush
138
139 #define SR_CHANGE() { SWAP_USP_SSP(); \
140 SYNC_PC_SR(); \
141 mmuflush(0x2000|(SFLAG ? 0x1000:0)); \
142 }
143
144 ////// #define IRQMASKLOWER() { DEBUG_LOG(0,"IRQMASK lowered, setting clocks_stop from:%016llx to %016llx ",cpu68k_clocks_stop,cpu68k_clocks-1); cpu68k_clocks_stop=cpu68k_clocks-1;}
145 #define IRQMASKLOWER() { DEBUG_LOG(0,"IRQMASK lowered"); }
146