1 // license:BSD-3-Clause
2 // copyright-holders:Curt Coder
3 /**********************************************************************
4
5 CMD SuperCPU v2 + SuperRAM emulation
6
7 **********************************************************************/
8
9 #include "emu.h"
10 #include "supercpu.h"
11
12
13
14 //**************************************************************************
15 // MACROS/CONSTANTS
16 //**************************************************************************
17
18 #define G65816_TAG "g65816"
19
20
21 //**************************************************************************
22 // DEVICE DEFINITIONS
23 //**************************************************************************
24
25 DEFINE_DEVICE_TYPE(C64_SUPERCPU, c64_supercpu_device, "c64_supercpu", "C64 SuperCPU v2 + SuperRAM")
26
27
28 //-------------------------------------------------
29 // ROM( c64_supercpu )
30 //-------------------------------------------------
31
ROM_START(c64_supercpu)32 ROM_START( c64_supercpu )
33 ROM_REGION( 0x20000, G65816_TAG, 0 )
34 ROM_LOAD( "supercpu_dos_204.bin", 0x00000, 0x20000, CRC(f4151454) SHA1(6aa529a7b1b6de53e8979e407a77b4d5657727f5) )
35 ROM_END
36
37
38 //-------------------------------------------------
39 // rom_region - device-specific ROM region
40 //-------------------------------------------------
41
42 const tiny_rom_entry *c64_supercpu_device::device_rom_region() const
43 {
44 return ROM_NAME( c64_supercpu );
45 }
46
47
48 //-------------------------------------------------
49 // ADDRESS_MAP( c64_supercpu_map )
50 //-------------------------------------------------
51
c64_supercpu_map(address_map & map)52 void c64_supercpu_device::c64_supercpu_map(address_map &map)
53 {
54 map(0x000000, 0x01ffff).ram().share("sram");
55 map(0x020000, 0xf7ffff).ram().share("dimm");
56 map(0xf80000, 0xf9ffff).mirror(0x60000).rom().region(G65816_TAG, 0);
57 }
58
59
60 //-------------------------------------------------
61 // device_add_mconfig - add device configuration
62 //-------------------------------------------------
63
device_add_mconfig(machine_config & config)64 void c64_supercpu_device::device_add_mconfig(machine_config &config)
65 {
66 G65816(config, m_maincpu, 1000000);
67 m_maincpu->set_addrmap(AS_PROGRAM, &c64_supercpu_device::c64_supercpu_map);
68
69 C64_EXPANSION_SLOT(config, m_exp, DERIVED_CLOCK(1, 1), c64_expansion_cards, nullptr);
70 m_exp->set_passthrough();
71 }
72
73
74 //-------------------------------------------------
75 // INPUT_PORTS( c64_supercpu )
76 //-------------------------------------------------
77
78 static INPUT_PORTS_START( c64_supercpu )
79 PORT_START("FRONT")
80 PORT_DIPNAME( 0x01, 0x01, "Unit" )
DEF_STR(Off)81 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
82 PORT_DIPSETTING( 0x01, DEF_STR( On ) )
83 PORT_DIPNAME( 0x02, 0x02, "JiffyDOS" )
84 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
85 PORT_DIPSETTING( 0x02, DEF_STR( On ) )
86 PORT_DIPNAME( 0x04, 0x00, "Speed" )
87 PORT_DIPSETTING( 0x04, "Normal" )
88 PORT_DIPSETTING( 0x00, "Turbo" )
89
90 PORT_START("RESET")
91 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Reset") PORT_CODE(KEYCODE_F11) PORT_WRITE_LINE_DEVICE_MEMBER(DEVICE_SELF_OWNER, c64_expansion_slot_device, reset_w)
92 INPUT_PORTS_END
93
94
95 //-------------------------------------------------
96 // input_ports - device-specific input ports
97 //-------------------------------------------------
98
99 ioport_constructor c64_supercpu_device::device_input_ports() const
100 {
101 return INPUT_PORTS_NAME( c64_supercpu );
102 }
103
104
105
106 //**************************************************************************
107 // LIVE DEVICE
108 //**************************************************************************
109
110 //-------------------------------------------------
111 // c64_supercpu_device - constructor
112 //-------------------------------------------------
113
c64_supercpu_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)114 c64_supercpu_device::c64_supercpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
115 device_t(mconfig, C64_SUPERCPU, tag, owner, clock),
116 device_c64_expansion_card_interface(mconfig, *this),
117 m_maincpu(*this, G65816_TAG),
118 m_exp(*this, "exp"),
119 m_sram(*this, "sram"),
120 m_dimm(*this, "dimm")
121 {
122 }
123
124
125 //-------------------------------------------------
126 // device_start - device-specific startup
127 //-------------------------------------------------
128
device_start()129 void c64_supercpu_device::device_start()
130 {
131 }
132
133
134 //-------------------------------------------------
135 // device_reset - device-specific reset
136 //-------------------------------------------------
137
device_reset()138 void c64_supercpu_device::device_reset()
139 {
140 }
141
142
143 //-------------------------------------------------
144 // c64_cd_r - cartridge data read
145 //-------------------------------------------------
146
c64_cd_r(offs_t offset,uint8_t data,int sphi2,int ba,int roml,int romh,int io1,int io2)147 uint8_t c64_supercpu_device::c64_cd_r(offs_t offset, uint8_t data, int sphi2, int ba, int roml, int romh, int io1, int io2)
148 {
149 data = m_exp->cd_r(offset, data, sphi2, ba, roml, romh, io1, io2);
150
151 switch (offset)
152 {
153 case 0xd0b0:
154 data = 0x40;
155 break;
156
157 case 0xd0b1:
158 break;
159
160 case 0xd0b2:
161 break;
162
163 case 0xd0b3:
164 case 0xd0b4:
165 break;
166
167 case 0xd0b5:
168 break;
169
170 case 0xd0b6:
171 break;
172
173 case 0xd0b7:
174 break;
175
176 case 0xd0b8:
177 case 0xd0b9:
178 break;
179
180 case 0xd0ba:
181 break;
182
183 case 0xd0bb:
184 break;
185
186 case 0xd0bc:
187 case 0xd0bd:
188 case 0xd0be:
189 case 0xd0bf:
190 break;
191 }
192
193 return data;
194 }
195
196
197 //-------------------------------------------------
198 // c64_cd_w - cartridge data write
199 //-------------------------------------------------
200
c64_cd_w(offs_t offset,uint8_t data,int sphi2,int ba,int roml,int romh,int io1,int io2)201 void c64_supercpu_device::c64_cd_w(offs_t offset, uint8_t data, int sphi2, int ba, int roml, int romh, int io1, int io2)
202 {
203 switch (offset)
204 {
205 case 0xd071:
206 break;
207
208 case 0xd072:
209 break;
210
211 case 0xd073:
212 break;
213
214 case 0xd074:
215 case 0xd075:
216 case 0xd076:
217 case 0xd077:
218 break;
219
220 case 0xd078:
221 break;
222
223 case 0xd07a:
224 break;
225
226 case 0xd079:
227 case 0xd07b:
228 break;
229
230 case 0xd07c:
231 break;
232
233 case 0xd07d:
234 case 0xd07f:
235 break;
236
237 case 0xd0b0:
238 case 0xd0b1:
239 break;
240
241 case 0xd0b2:
242 break;
243
244 case 0xd0b3:
245 break;
246
247 case 0xd0b4:
248 break;
249
250 case 0xd0b5:
251 break;
252
253 case 0xd0b6:
254 break;
255
256 case 0xd0b7:
257 break;
258
259 case 0xd0b8:
260 break;
261
262 case 0xd0b9:
263 case 0xd0ba:
264 case 0xd0bb:
265 break;
266
267 case 0xd0bc:
268 break;
269
270 case 0xd0be:
271 break;
272
273 case 0xd0bd:
274 case 0xd0bf:
275 break;
276 }
277
278 m_exp->cd_w(offset, data, sphi2, ba, roml, romh, io1, io2);
279 }
280
281
282 //-------------------------------------------------
283 // c64_game_r - GAME read
284 //-------------------------------------------------
285
c64_game_r(offs_t offset,int sphi2,int ba,int rw)286 int c64_supercpu_device::c64_game_r(offs_t offset, int sphi2, int ba, int rw)
287 {
288 return m_exp->game_r(offset, sphi2, ba, rw, m_slot->loram(), m_slot->hiram());
289 }
290
291
292 //-------------------------------------------------
293 // c64_exrom_r - EXROM read
294 //-------------------------------------------------
295
c64_exrom_r(offs_t offset,int sphi2,int ba,int rw)296 int c64_supercpu_device::c64_exrom_r(offs_t offset, int sphi2, int ba, int rw)
297 {
298 return m_exp->exrom_r(offset, sphi2, ba, rw, m_slot->loram(), m_slot->hiram());
299 }
300