1 // license:BSD-3-Clause 2 // copyright-holders:Ville Linde, Barry Rodewald, Carl, Philip Bennett 3 #pragma once 4 5 #ifndef __I386_H__ 6 #define __I386_H__ 7 8 #include "i386dasm.h" 9 10 //#define DEBUG_MISSING_OPCODE 11 12 #define I386OP(XX) i386_##XX 13 #define I486OP(XX) i486_##XX 14 #define PENTIUMOP(XX) pentium_##XX 15 #define MMXOP(XX) mmx_##XX 16 #define SSEOP(XX) sse_##XX 17 18 enum SREGS { ES, CS, SS, DS, FS, GS }; 19 20 enum BREGS 21 { 22 AL = NATIVE_ENDIAN_VALUE_LE_BE(0,3), 23 AH = NATIVE_ENDIAN_VALUE_LE_BE(1,2), 24 CL = NATIVE_ENDIAN_VALUE_LE_BE(4,7), 25 CH = NATIVE_ENDIAN_VALUE_LE_BE(5,6), 26 DL = NATIVE_ENDIAN_VALUE_LE_BE(8,11), 27 DH = NATIVE_ENDIAN_VALUE_LE_BE(9,10), 28 BL = NATIVE_ENDIAN_VALUE_LE_BE(12,15), 29 BH = NATIVE_ENDIAN_VALUE_LE_BE(13,14) 30 }; 31 32 enum WREGS 33 { 34 AX = NATIVE_ENDIAN_VALUE_LE_BE(0,1), 35 CX = NATIVE_ENDIAN_VALUE_LE_BE(2,3), 36 DX = NATIVE_ENDIAN_VALUE_LE_BE(4,5), 37 BX = NATIVE_ENDIAN_VALUE_LE_BE(6,7), 38 SP = NATIVE_ENDIAN_VALUE_LE_BE(8,9), 39 BP = NATIVE_ENDIAN_VALUE_LE_BE(10,11), 40 SI = NATIVE_ENDIAN_VALUE_LE_BE(12,13), 41 DI = NATIVE_ENDIAN_VALUE_LE_BE(14,15) 42 }; 43 44 enum DREGS { EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI }; 45 46 enum 47 { 48 I386_PC = 0, 49 50 /* 8-bit registers */ 51 I386_AL, 52 I386_AH, 53 I386_BL, 54 I386_BH, 55 I386_CL, 56 I386_CH, 57 I386_DL, 58 I386_DH, 59 60 /* 16-bit registers */ 61 I386_AX, 62 I386_BX, 63 I386_CX, 64 I386_DX, 65 I386_BP, 66 I386_SP, 67 I386_SI, 68 I386_DI, 69 I386_IP, 70 71 /* 32-bit registers */ 72 I386_EAX, 73 I386_ECX, 74 I386_EDX, 75 I386_EBX, 76 I386_EBP, 77 I386_ESP, 78 I386_ESI, 79 I386_EDI, 80 I386_EIP, 81 82 /* segment registers */ 83 I386_CS, 84 I386_CS_BASE, 85 I386_CS_LIMIT, 86 I386_CS_FLAGS, 87 I386_SS, 88 I386_SS_BASE, 89 I386_SS_LIMIT, 90 I386_SS_FLAGS, 91 I386_DS, 92 I386_DS_BASE, 93 I386_DS_LIMIT, 94 I386_DS_FLAGS, 95 I386_ES, 96 I386_ES_BASE, 97 I386_ES_LIMIT, 98 I386_ES_FLAGS, 99 I386_FS, 100 I386_FS_BASE, 101 I386_FS_LIMIT, 102 I386_FS_FLAGS, 103 I386_GS, 104 I386_GS_BASE, 105 I386_GS_LIMIT, 106 I386_GS_FLAGS, 107 108 /* other */ 109 I386_EFLAGS, 110 111 I386_CR0, 112 I386_CR1, 113 I386_CR2, 114 I386_CR3, 115 I386_CR4, 116 117 I386_DR0, 118 I386_DR1, 119 I386_DR2, 120 I386_DR3, 121 I386_DR4, 122 I386_DR5, 123 I386_DR6, 124 I386_DR7, 125 126 I386_TR6, 127 I386_TR7, 128 129 I386_GDTR_BASE, 130 I386_GDTR_LIMIT, 131 I386_IDTR_BASE, 132 I386_IDTR_LIMIT, 133 I386_TR, 134 I386_TR_BASE, 135 I386_TR_LIMIT, 136 I386_TR_FLAGS, 137 I386_LDTR, 138 I386_LDTR_BASE, 139 I386_LDTR_LIMIT, 140 I386_LDTR_FLAGS, 141 142 I386_CPL, 143 144 X87_CTRL, 145 X87_STATUS, 146 X87_TAG, 147 X87_ST0, 148 X87_ST1, 149 X87_ST2, 150 X87_ST3, 151 X87_ST4, 152 X87_ST5, 153 X87_ST6, 154 X87_ST7, 155 156 SSE_XMM0, 157 SSE_XMM1, 158 SSE_XMM2, 159 SSE_XMM3, 160 SSE_XMM4, 161 SSE_XMM5, 162 SSE_XMM6, 163 SSE_XMM7 164 }; 165 166 enum 167 { 168 /* mmx registers aliased to x87 ones */ 169 MMX_MM0 = X87_ST0, 170 MMX_MM1 = X87_ST1, 171 MMX_MM2 = X87_ST2, 172 MMX_MM3 = X87_ST3, 173 MMX_MM4 = X87_ST4, 174 MMX_MM5 = X87_ST5, 175 MMX_MM6 = X87_ST6, 176 MMX_MM7 = X87_ST7 177 }; 178 179 enum smram 180 { 181 SMRAM_SMBASE = 0xF8, 182 SMRAM_SMREV = 0xFC, 183 SMRAM_IORSRT = 0x100, 184 SMRAM_AHALT = 0x102, 185 SMRAM_IOEDI = 0x104, 186 SMRAM_IOECX = 0x108, 187 SMRAM_IOESI = 0x10C, 188 189 SMRAM_ES = 0x1A8, 190 SMRAM_CS = 0x1AC, 191 SMRAM_SS = 0x1B0, 192 SMRAM_DS = 0x1B4, 193 SMRAM_FS = 0x1B8, 194 SMRAM_GS = 0x1BC, 195 SMRAM_LDTR = 0x1C0, 196 SMRAM_TR = 0x1C4, 197 SMRAM_DR7 = 0x1C8, 198 SMRAM_DR6 = 0x1CC, 199 SMRAM_EAX = 0x1D0, 200 SMRAM_ECX = 0x1D4, 201 SMRAM_EDX = 0x1D8, 202 SMRAM_EBX = 0x1DC, 203 SMRAM_ESP = 0x1E0, 204 SMRAM_EBP = 0x1E4, 205 SMRAM_ESI = 0x1E8, 206 SMRAM_EDI = 0x1EC, 207 SMRAM_EIP = 0x1F0, 208 SMRAM_EFLAGS = 0x1F4, 209 SMRAM_CR3 = 0x1F8, 210 SMRAM_CR0 = 0x1FC 211 }; 212 213 enum smram_intel_p5 214 { 215 SMRAM_IP5_IOEIP = 0x110, 216 SMRAM_IP5_CR4 = 0x128, 217 SMRAM_IP5_ESLIM = 0x130, 218 SMRAM_IP5_ESBASE = 0x134, 219 SMRAM_IP5_ESACC = 0x138, 220 SMRAM_IP5_CSLIM = 0x13C, 221 SMRAM_IP5_CSBASE = 0x140, 222 SMRAM_IP5_CSACC = 0x144, 223 SMRAM_IP5_SSLIM = 0x148, 224 SMRAM_IP5_SSBASE = 0x14C, 225 SMRAM_IP5_SSACC = 0x150, 226 SMRAM_IP5_DSLIM = 0x154, 227 SMRAM_IP5_DSBASE = 0x158, 228 SMRAM_IP5_DSACC = 0x15C, 229 SMRAM_IP5_FSLIM = 0x160, 230 SMRAM_IP5_FSBASE = 0x164, 231 SMRAM_IP5_FSACC = 0x168, 232 SMRAM_IP5_GSLIM = 0x16C, 233 SMRAM_IP5_GSBASE = 0x170, 234 SMRAM_IP5_GSACC = 0x174, 235 SMRAM_IP5_LDTLIM = 0x178, 236 SMRAM_IP5_LDTBASE = 0x17C, 237 SMRAM_IP5_LDTACC = 0x180, 238 SMRAM_IP5_GDTLIM = 0x184, 239 SMRAM_IP5_GDTBASE = 0x188, 240 SMRAM_IP5_GDTACC = 0x18C, 241 SMRAM_IP5_IDTLIM = 0x190, 242 SMRAM_IP5_IDTBASE = 0x194, 243 SMRAM_IP5_IDTACC = 0x198, 244 SMRAM_IP5_TRLIM = 0x19C, 245 SMRAM_IP5_TRBASE = 0x1A0, 246 SMRAM_IP5_TRACC = 0x1A4 247 }; 248 249 /* Protected mode exceptions */ 250 enum pm_faults 251 { 252 FAULT_UD = 6, // Invalid Opcode 253 FAULT_NM = 7, // Coprocessor not available 254 FAULT_DF = 8, // Double Fault 255 FAULT_TS = 10, // Invalid TSS 256 FAULT_NP = 11, // Segment or Gate not present 257 FAULT_SS = 12, // Stack fault 258 FAULT_GP = 13, // General Protection Fault 259 FAULT_PF = 14, // Page Fault 260 FAULT_MF = 16 // Match (Coprocessor) Fault 261 }; 262 263 /* MXCSR Control and Status Register */ 264 enum mxcsr_bits 265 { 266 MXCSR_IE = 1 << 0, // Invalid Operation Flag 267 MXCSR_DE = 1 << 1, // Denormal Flag 268 MXCSR_ZE = 1 << 2, // Divide-by-Zero Flag 269 MXCSR_OE = 1 << 3, // Overflow Flag 270 MXCSR_UE = 1 << 4, // Underflow Flag 271 MXCSR_PE = 1 << 5, // Precision Flag 272 MXCSR_DAZ = 1 << 6, // Denormals Are Zeros 273 MXCSR_IM = 1 << 7, // Invalid Operation Mask 274 MXCSR_DM = 1 << 8, // Denormal Operation Mask 275 MXCSR_ZM = 1 << 9, // Divide-by-Zero Mask 276 MXCSR_OM = 1 << 10, // Overflow Mask 277 MXCSR_UM = 1 << 11, // Underflow Mask 278 MXCSR_PM = 1 << 12, // Precision Mask 279 MXCSR_RC = 3 << 13, // Rounding Control 280 MXCSR_FZ = 1 << 15 // Flush to Zero 281 }; 282 283 union MMX_REG { 284 uint32_t d[2]; 285 int32_t i[2]; 286 uint16_t w[4]; 287 int16_t s[4]; 288 uint8_t b[8]; 289 int8_t c[8]; 290 float f[2]; 291 uint64_t q; 292 int64_t l; 293 }; 294 295 extern int i386_parity_table[256]; 296 297 #define FAULT_THROW(fault,error) { throw (uint64_t)(fault | (uint64_t)error << 32); } 298 #define PF_THROW(error) { m_cr[2] = address; FAULT_THROW(FAULT_PF,error); } 299 300 #define PROTECTED_MODE (m_cr[0] & 0x1) 301 #define STACK_32BIT (m_sreg[SS].d) 302 #define V8086_MODE (m_VM) 303 #define NESTED_TASK (m_NT) 304 #define WP (m_cr[0] & 0x10000) 305 306 #define SetOF_Add32(r,s,d) (m_OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x80000000) ? 1: 0) 307 #define SetOF_Add16(r,s,d) (m_OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x8000) ? 1 : 0) 308 #define SetOF_Add8(r,s,d) (m_OF = (((r) ^ (s)) & ((r) ^ (d)) & 0x80) ? 1 : 0) 309 310 #define SetOF_Sub32(r,s,d) (m_OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x80000000) ? 1 : 0) 311 #define SetOF_Sub16(r,s,d) (m_OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x8000) ? 1 : 0) 312 #define SetOF_Sub8(r,s,d) (m_OF = (((d) ^ (s)) & ((d) ^ (r)) & 0x80) ? 1 : 0) 313 314 #define SetCF8(x) {m_CF = ((x) & 0x100) ? 1 : 0; } 315 #define SetCF16(x) {m_CF = ((x) & 0x10000) ? 1 : 0; } 316 #define SetCF32(x) {m_CF = ((x) & (((uint64_t)1) << 32)) ? 1 : 0; } 317 318 #define SetSF(x) (m_SF = (x)) 319 #define SetZF(x) (m_ZF = (x)) 320 #define SetAF(x,y,z) (m_AF = (((x) ^ ((y) ^ (z))) & 0x10) ? 1 : 0) 321 #define SetPF(x) (m_PF = i386_parity_table[(x) & 0xFF]) 322 323 #define SetSZPF8(x) {m_ZF = ((uint8_t)(x)==0); m_SF = ((x)&0x80) ? 1 : 0; m_PF = i386_parity_table[x & 0xFF]; } 324 #define SetSZPF16(x) {m_ZF = ((uint16_t)(x)==0); m_SF = ((x)&0x8000) ? 1 : 0; m_PF = i386_parity_table[x & 0xFF]; } 325 #define SetSZPF32(x) {m_ZF = ((uint32_t)(x)==0); m_SF = ((x)&0x80000000) ? 1 : 0; m_PF = i386_parity_table[x & 0xFF]; } 326 327 #define MMX(n) (*((MMX_REG *)(&m_x87_reg[(n)].low))) 328 #define XMM(n) m_sse_reg[(n)] 329 330 #define VTLB_FLAG_DIRTY 0x100 331 #define CYCLES_NUM(x) (m_cycles -= (x)) 332 333 #define FAULT(fault,error) {m_ext = 1; i386_trap_with_error(fault,0,0,error); return;} 334 #define FAULT_EXP(fault,error) {m_ext = 1; i386_trap_with_error(fault,0,trap_level+1,error); return;} 335 336 /***********************************************************************************/ 337 338 struct MODRM_TABLE { 339 struct { 340 int b; 341 int w; 342 int d; 343 } reg; 344 struct { 345 int b; 346 int w; 347 int d; 348 } rm; 349 }; 350 351 extern MODRM_TABLE i386_MODRM_table[256]; 352 353 #define REG8(x) (m_reg.b[x]) 354 #define REG16(x) (m_reg.w[x]) 355 #define REG32(x) (m_reg.d[x]) 356 357 #define LOAD_REG8(x) (REG8(i386_MODRM_table[x].reg.b)) 358 #define LOAD_REG16(x) (REG16(i386_MODRM_table[x].reg.w)) 359 #define LOAD_REG32(x) (REG32(i386_MODRM_table[x].reg.d)) 360 #define LOAD_RM8(x) (REG8(i386_MODRM_table[x].rm.b)) 361 #define LOAD_RM16(x) (REG16(i386_MODRM_table[x].rm.w)) 362 #define LOAD_RM32(x) (REG32(i386_MODRM_table[x].rm.d)) 363 364 #define STORE_REG8(x, value) (REG8(i386_MODRM_table[x].reg.b) = value) 365 #define STORE_REG16(x, value) (REG16(i386_MODRM_table[x].reg.w) = value) 366 #define STORE_REG32(x, value) (REG32(i386_MODRM_table[x].reg.d) = value) 367 #define STORE_RM8(x, value) (REG8(i386_MODRM_table[x].rm.b) = value) 368 #define STORE_RM16(x, value) (REG16(i386_MODRM_table[x].rm.w) = value) 369 #define STORE_RM32(x, value) (REG32(i386_MODRM_table[x].rm.d) = value) 370 371 #define SWITCH_ENDIAN_32(x) (((((x) << 24) & (0xff << 24)) | (((x) << 8) & (0xff << 16)) | (((x) >> 8) & (0xff << 8)) | (((x) >> 24) & (0xff << 0)))) 372 373 /***********************************************************************************/ 374 375 enum X86_CYCLES 376 { 377 CYCLES_MOV_REG_REG, 378 CYCLES_MOV_REG_MEM, 379 CYCLES_MOV_MEM_REG, 380 CYCLES_MOV_IMM_REG, 381 CYCLES_MOV_IMM_MEM, 382 CYCLES_MOV_ACC_MEM, 383 CYCLES_MOV_MEM_ACC, 384 CYCLES_MOV_REG_SREG, 385 CYCLES_MOV_MEM_SREG, 386 CYCLES_MOV_SREG_REG, 387 CYCLES_MOV_SREG_MEM, 388 CYCLES_MOVSX_REG_REG, 389 CYCLES_MOVSX_MEM_REG, 390 CYCLES_MOVZX_REG_REG, 391 CYCLES_MOVZX_MEM_REG, 392 CYCLES_PUSH_RM, 393 CYCLES_PUSH_REG_SHORT, 394 CYCLES_PUSH_SREG, 395 CYCLES_PUSH_IMM, 396 CYCLES_PUSHA, 397 CYCLES_POP_RM, 398 CYCLES_POP_REG_SHORT, 399 CYCLES_POP_SREG, 400 CYCLES_POPA, 401 CYCLES_XCHG_REG_REG, 402 CYCLES_XCHG_REG_MEM, 403 CYCLES_IN, 404 CYCLES_IN_VAR, 405 CYCLES_OUT, 406 CYCLES_OUT_VAR, 407 CYCLES_LEA, 408 CYCLES_LDS, 409 CYCLES_LES, 410 CYCLES_LFS, 411 CYCLES_LGS, 412 CYCLES_LSS, 413 CYCLES_CLC, 414 CYCLES_CLD, 415 CYCLES_CLI, 416 CYCLES_CLTS, 417 CYCLES_CMC, 418 CYCLES_LAHF, 419 CYCLES_POPF, 420 CYCLES_PUSHF, 421 CYCLES_SAHF, 422 CYCLES_STC, 423 CYCLES_STD, 424 CYCLES_STI, 425 CYCLES_ALU_REG_REG, 426 CYCLES_ALU_REG_MEM, 427 CYCLES_ALU_MEM_REG, 428 CYCLES_ALU_IMM_REG, 429 CYCLES_ALU_IMM_MEM, 430 CYCLES_ALU_IMM_ACC, 431 CYCLES_INC_REG, 432 CYCLES_INC_MEM, 433 CYCLES_DEC_REG, 434 CYCLES_DEC_MEM, 435 CYCLES_CMP_REG_REG, 436 CYCLES_CMP_REG_MEM, 437 CYCLES_CMP_MEM_REG, 438 CYCLES_CMP_IMM_REG, 439 CYCLES_CMP_IMM_MEM, 440 CYCLES_CMP_IMM_ACC, 441 CYCLES_TEST_REG_REG, 442 CYCLES_TEST_REG_MEM, 443 CYCLES_TEST_IMM_REG, 444 CYCLES_TEST_IMM_MEM, 445 CYCLES_TEST_IMM_ACC, 446 CYCLES_NEG_REG, 447 CYCLES_NEG_MEM, 448 CYCLES_AAA, 449 CYCLES_AAS, 450 CYCLES_DAA, 451 CYCLES_DAS, 452 CYCLES_MUL8_ACC_REG, 453 CYCLES_MUL8_ACC_MEM, 454 CYCLES_MUL16_ACC_REG, 455 CYCLES_MUL16_ACC_MEM, 456 CYCLES_MUL32_ACC_REG, 457 CYCLES_MUL32_ACC_MEM, 458 CYCLES_IMUL8_ACC_REG, 459 CYCLES_IMUL8_ACC_MEM, 460 CYCLES_IMUL16_ACC_REG, 461 CYCLES_IMUL16_ACC_MEM, 462 CYCLES_IMUL32_ACC_REG, 463 CYCLES_IMUL32_ACC_MEM, 464 CYCLES_IMUL8_REG_REG, 465 CYCLES_IMUL8_REG_MEM, 466 CYCLES_IMUL16_REG_REG, 467 CYCLES_IMUL16_REG_MEM, 468 CYCLES_IMUL32_REG_REG, 469 CYCLES_IMUL32_REG_MEM, 470 CYCLES_IMUL16_REG_IMM_REG, 471 CYCLES_IMUL16_MEM_IMM_REG, 472 CYCLES_IMUL32_REG_IMM_REG, 473 CYCLES_IMUL32_MEM_IMM_REG, 474 CYCLES_DIV8_ACC_REG, 475 CYCLES_DIV8_ACC_MEM, 476 CYCLES_DIV16_ACC_REG, 477 CYCLES_DIV16_ACC_MEM, 478 CYCLES_DIV32_ACC_REG, 479 CYCLES_DIV32_ACC_MEM, 480 CYCLES_IDIV8_ACC_REG, 481 CYCLES_IDIV8_ACC_MEM, 482 CYCLES_IDIV16_ACC_REG, 483 CYCLES_IDIV16_ACC_MEM, 484 CYCLES_IDIV32_ACC_REG, 485 CYCLES_IDIV32_ACC_MEM, 486 CYCLES_AAD, 487 CYCLES_AAM, 488 CYCLES_CBW, 489 CYCLES_CWD, 490 CYCLES_ROTATE_REG, 491 CYCLES_ROTATE_MEM, 492 CYCLES_ROTATE_CARRY_REG, 493 CYCLES_ROTATE_CARRY_MEM, 494 CYCLES_SHLD_REG, 495 CYCLES_SHLD_MEM, 496 CYCLES_SHRD_REG, 497 CYCLES_SHRD_MEM, 498 CYCLES_NOT_REG, 499 CYCLES_NOT_MEM, 500 CYCLES_CMPS, 501 CYCLES_INS, 502 CYCLES_LODS, 503 CYCLES_MOVS, 504 CYCLES_OUTS, 505 CYCLES_SCAS, 506 CYCLES_STOS, 507 CYCLES_XLAT, 508 CYCLES_REP_CMPS_BASE, 509 CYCLES_REP_INS_BASE, 510 CYCLES_REP_LODS_BASE, 511 CYCLES_REP_MOVS_BASE, 512 CYCLES_REP_OUTS_BASE, 513 CYCLES_REP_SCAS_BASE, 514 CYCLES_REP_STOS_BASE, 515 CYCLES_REP_CMPS, 516 CYCLES_REP_INS, 517 CYCLES_REP_LODS, 518 CYCLES_REP_MOVS, 519 CYCLES_REP_OUTS, 520 CYCLES_REP_SCAS, 521 CYCLES_REP_STOS, 522 CYCLES_BSF_BASE, 523 CYCLES_BSF, 524 CYCLES_BSR_BASE, 525 CYCLES_BSR, 526 CYCLES_BT_IMM_REG, 527 CYCLES_BT_IMM_MEM, 528 CYCLES_BT_REG_REG, 529 CYCLES_BT_REG_MEM, 530 CYCLES_BTC_IMM_REG, 531 CYCLES_BTC_IMM_MEM, 532 CYCLES_BTC_REG_REG, 533 CYCLES_BTC_REG_MEM, 534 CYCLES_BTR_IMM_REG, 535 CYCLES_BTR_IMM_MEM, 536 CYCLES_BTR_REG_REG, 537 CYCLES_BTR_REG_MEM, 538 CYCLES_BTS_IMM_REG, 539 CYCLES_BTS_IMM_MEM, 540 CYCLES_BTS_REG_REG, 541 CYCLES_BTS_REG_MEM, 542 CYCLES_CALL, // E8 543 CYCLES_CALL_REG, // FF /2 544 CYCLES_CALL_MEM, // FF /2 545 CYCLES_CALL_INTERSEG, // 9A 546 CYCLES_CALL_REG_INTERSEG, // FF /3 547 CYCLES_CALL_MEM_INTERSEG, // FF /3 548 CYCLES_JMP_SHORT, // EB 549 CYCLES_JMP, // E9 550 CYCLES_JMP_REG, // FF /4 551 CYCLES_JMP_MEM, // FF /4 552 CYCLES_JMP_INTERSEG, // EA 553 CYCLES_JMP_REG_INTERSEG, // FF /5 554 CYCLES_JMP_MEM_INTERSEG, // FF /5 555 CYCLES_RET, // C3 556 CYCLES_RET_IMM, // C2 557 CYCLES_RET_INTERSEG, // CB 558 CYCLES_RET_IMM_INTERSEG, // CA 559 CYCLES_JCC_DISP8, 560 CYCLES_JCC_FULL_DISP, 561 CYCLES_JCC_DISP8_NOBRANCH, 562 CYCLES_JCC_FULL_DISP_NOBRANCH, 563 CYCLES_JCXZ, 564 CYCLES_JCXZ_NOBRANCH, 565 CYCLES_LOOP, 566 CYCLES_LOOPZ, 567 CYCLES_LOOPNZ, 568 CYCLES_SETCC_REG, 569 CYCLES_SETCC_MEM, 570 CYCLES_ENTER, 571 CYCLES_LEAVE, 572 CYCLES_INT, 573 CYCLES_INT3, 574 CYCLES_INTO_OF1, 575 CYCLES_INTO_OF0, 576 CYCLES_BOUND_IN_RANGE, 577 CYCLES_BOUND_OUT_RANGE, 578 CYCLES_IRET, 579 CYCLES_HLT, 580 CYCLES_MOV_REG_CR0, 581 CYCLES_MOV_REG_CR2, 582 CYCLES_MOV_REG_CR3, 583 CYCLES_MOV_CR_REG, 584 CYCLES_MOV_REG_DR0_3, 585 CYCLES_MOV_REG_DR6_7, 586 CYCLES_MOV_DR6_7_REG, 587 CYCLES_MOV_DR0_3_REG, 588 CYCLES_MOV_REG_TR6_7, 589 CYCLES_MOV_TR6_7_REG, 590 CYCLES_NOP, 591 CYCLES_WAIT, 592 CYCLES_ARPL_REG, 593 CYCLES_ARPL_MEM, 594 CYCLES_LAR_REG, 595 CYCLES_LAR_MEM, 596 CYCLES_LGDT, 597 CYCLES_LIDT, 598 CYCLES_LLDT_REG, 599 CYCLES_LLDT_MEM, 600 CYCLES_LMSW_REG, 601 CYCLES_LMSW_MEM, 602 CYCLES_LSL_REG, 603 CYCLES_LSL_MEM, 604 CYCLES_LTR_REG, 605 CYCLES_LTR_MEM, 606 CYCLES_SGDT, 607 CYCLES_SIDT, 608 CYCLES_SLDT_REG, 609 CYCLES_SLDT_MEM, 610 CYCLES_SMSW_REG, 611 CYCLES_SMSW_MEM, 612 CYCLES_STR_REG, 613 CYCLES_STR_MEM, 614 CYCLES_VERR_REG, 615 CYCLES_VERR_MEM, 616 CYCLES_VERW_REG, 617 CYCLES_VERW_MEM, 618 CYCLES_LOCK, 619 620 CYCLES_BSWAP, 621 CYCLES_CMPXCHG8B, 622 CYCLES_CMPXCHG, 623 CYCLES_CPUID, 624 CYCLES_CPUID_EAX1, 625 CYCLES_INVD, 626 CYCLES_XADD, 627 CYCLES_RDTSC, 628 CYCLES_RSM, 629 CYCLES_RDMSR, 630 631 CYCLES_FABS, 632 CYCLES_FADD, 633 CYCLES_FBLD, 634 CYCLES_FBSTP, 635 CYCLES_FCHS, 636 CYCLES_FCLEX, 637 CYCLES_FCOM, 638 CYCLES_FCOS, 639 CYCLES_FDECSTP, 640 CYCLES_FDISI, 641 CYCLES_FDIV, 642 CYCLES_FDIVR, 643 CYCLES_FENI, 644 CYCLES_FFREE, 645 CYCLES_FIADD, 646 CYCLES_FICOM, 647 CYCLES_FIDIV, 648 CYCLES_FILD, 649 CYCLES_FIMUL, 650 CYCLES_FINCSTP, 651 CYCLES_FINIT, 652 CYCLES_FIST, 653 CYCLES_FISUB, 654 CYCLES_FLD, 655 CYCLES_FLDZ, 656 CYCLES_FLD1, 657 CYCLES_FLDL2E, 658 CYCLES_FLDL2T, 659 CYCLES_FLDLG2, 660 CYCLES_FLDLN2, 661 CYCLES_FLDPI, 662 CYCLES_FLDCW, 663 CYCLES_FLDENV, 664 CYCLES_FMUL, 665 CYCLES_FNOP, 666 CYCLES_FPATAN, 667 CYCLES_FPREM, 668 CYCLES_FPREM1, 669 CYCLES_FPTAN, 670 CYCLES_FRNDINT, 671 CYCLES_FRSTOR, 672 CYCLES_FSAVE, 673 CYCLES_FSCALE, 674 CYCLES_FSETPM, 675 CYCLES_FSIN, 676 CYCLES_FSINCOS, 677 CYCLES_FSQRT, 678 CYCLES_FST, 679 CYCLES_FSTCW, 680 CYCLES_FSTENV, 681 CYCLES_FSTSW, 682 CYCLES_FSUB, 683 CYCLES_FSUBR, 684 CYCLES_FTST, 685 CYCLES_FUCOM, 686 CYCLES_FXAM, 687 CYCLES_FXCH, 688 CYCLES_FXTRACT, 689 CYCLES_FYL2X, 690 CYCLES_FYL2XPI, 691 CYCLES_CMPXCHG_REG_REG_T, 692 CYCLES_CMPXCHG_REG_REG_F, 693 CYCLES_CMPXCHG_REG_MEM_T, 694 CYCLES_CMPXCHG_REG_MEM_F, 695 CYCLES_XADD_REG_REG, 696 CYCLES_XADD_REG_MEM, 697 698 CYCLES_NUM_OPCODES 699 }; 700 701 702 #define CPU_CYCLES_I386 0 703 #define CPU_CYCLES_I486 1 704 #define CPU_CYCLES_PENTIUM 2 705 #define CPU_CYCLES_MEDIAGX 3 706 707 #define OP_I386 0x1 708 #define OP_FPU 0x2 709 #define OP_I486 0x4 710 #define OP_PENTIUM 0x8 711 #define OP_MMX 0x10 712 #define OP_PPRO 0x20 713 #define OP_SSE 0x40 714 #define OP_SSE2 0x80 715 #define OP_SSE3 0x100 716 #define OP_CYRIX 0x8000 717 #define OP_2BYTE 0x80000000 718 #define OP_3BYTE66 0x40000000 719 #define OP_3BYTEF2 0x20000000 720 #define OP_3BYTEF3 0x10000000 721 #define OP_3BYTE38 0x08000000 722 #define OP_3BYTE3A 0x04000000 723 #define OP_4BYTE3866 0x02000000 724 #define OP_4BYTE3A66 0x01000000 725 #define OP_4BYTE38F2 0x00800000 726 #define OP_4BYTE3AF2 0x00400000 727 #define OP_4BYTE38F3 0x00200000 728 729 #endif /* __I386_H__ */ 730